US11569162B2 - Chip on film package with reinforcing sheet and manufacturing method of chip on film package with reinforcing sheet - Google Patents

Chip on film package with reinforcing sheet and manufacturing method of chip on film package with reinforcing sheet Download PDF

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Publication number
US11569162B2
US11569162B2 US16/988,741 US202016988741A US11569162B2 US 11569162 B2 US11569162 B2 US 11569162B2 US 202016988741 A US202016988741 A US 202016988741A US 11569162 B2 US11569162 B2 US 11569162B2
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chip
reinforcing sheet
film package
package according
circuit layer
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US20210098345A1 (en
Inventor
Chiao-Ling Huang
Tai-Hung Lin
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Novatek Microelectronics Corp
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Novatek Microelectronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

Definitions

  • the present disclosure generally relates to a chip package and a manufacturing method of the chip package, in particular, to a chip on film package and a manufacturing method of the chip on film package.
  • LCDs liquid crystal displays
  • IC driver integrated circuit
  • Packaging methods mainly used in a display device field include a tape carrier packaging (TCP) method, a chip on glass (COG) packaging method, a chip on film (COF) packaging method, and the like. These methods are referred to as wireless methods. To promote reduction in fabrication cost and improvement in yield due to a fine pitch, the share of COF technology in the packaging market has gradually increased since the late 1990s.
  • TCP tape carrier packaging
  • COG chip on glass
  • COF chip on film packaging method
  • COF technology uses a base film on which fine wiring patterns are formed, the distance and pitch between neighboring leads can be minimized, thus maximizing lead density. Further, this COF technology can employ semiconductor chips with a large number of chip pads and fine pitch or large-sized semiconductor chips. Therefore, the COF technology using the base film achieves high-integrated and multi-functional semiconductor device.
  • the COF package has an excellent bending force and a good flexibility, compared to the conventional chip package, is of high quality.
  • the external terminals of such IC package are required not only to be increased in number but also to be more fine pitch.
  • the circuits on the base film of COF package rises, naturally it becomes necessary for the circuits on the base film of COF package to have fine pitch contacts in order to electrically connect the external terminals of the IC package.
  • the thickness of the fine-pitch circuit is also reduces accordingly, which makes the fine-pitch circuit more vulnerable and easier to break.
  • the present disclosure is directed to a chip on film package and a manufacturing method of the chip on film package with favourable yield rate.
  • the present disclosure provides a chip on film package includes a base film, a patterned circuit layer, a chip and a reinforcing sheet.
  • the base film includes a first surface, a second surface opposite to the first surface and a mounting region located on the first surface.
  • the patterned circuit layer is disposed on the first surface.
  • the chip is mounted on the mounting region and electrically connected to the patterned circuit layer.
  • the reinforcing sheet is disposed on the first surface and/or the second surface and exposes the chip, wherein a flexibility of the reinforcing sheet is substantially equal to or greater than a flexibility of the base film.
  • the reinforcing sheet is disposed on the first surface and includes a first opening exposing the chip.
  • the reinforcing sheet directly disposed on the patterned circuit layer and the first opening exposes a part of the patterned circuit layer where the chip is mounted.
  • the chip on film package further includes a solder resist layer disposed on the patterned circuit layer and including a second opening exposing a part of the patterned circuit layer where the chip is mounted, the reinforcing sheet is disposed on the solder resist layer and exposes the second opening.
  • a size of the reinforcing sheet is substantially smaller than a size of the solder resist layer, and a gap maintains between an outer edge of the reinforcing sheet and an outer edge of the solder resist layer.
  • the chip on film package further includes an underfill disposed between the chip and the base film and covering the patterned circuit layer exposed by the first opening.
  • the reinforcing sheet is disposed on the second surface.
  • the reinforcing sheet includes a plurality of chamfered corners.
  • the chip on film package further includes an adhesive layer disposed between the reinforcing sheet and the base film.
  • the patterned circuit layer includes a plurality of circuit lines and a fine-pitch region, and the reinforcing sheet covers the circuit lines in the fine-pitch region.
  • a pitch between adjacent two of the circuit lines in the fine-pitch region is substantially smaller than 20 ⁇ m, and a width of each of the circuit lines ranges from 5 ⁇ m to 11 ⁇ m.
  • a material of the reinforcing sheet includes polyimide (PI).
  • a thickness of the reinforcing sheet ranges from 3 ⁇ m to 40 ⁇ m.
  • the present disclosure provides a manufacturing method of a chip on film package.
  • the method includes the following steps.
  • a base film is provided, wherein the base film includes a first surface, a second surface opposite to the first surface and a mounting region located on the first surface.
  • a patterned circuit layer is formed on the first surface.
  • a chip is mounted on the mounting region, wherein the chip is electrically connected to the patterned circuit layer.
  • a reinforcing sheet is laminated onto the first surface and/or the second surface, wherein a flexibility of the reinforcing sheet is substantially equal to or greater than a flexibility of the base film.
  • the reinforcing sheet is laminated onto the first surface and/or the second surface before the chip is mounted on the mounting region, and the reinforcing sheet covers patterned circuit layer and exposing the mounting region.
  • the reinforcing sheet is laminated onto the second surface after the chip is mounted on the mounting region.
  • the reinforcing sheet is laminated onto the first surface and/or the second surface by a laminating roller configured to roll over the first surface and/or the second surface.
  • the step of laminating the reinforcing sheet onto the first surface and/or the second surface further includes a heating process.
  • a heating temperature of the heating process ranges from 80° C. to 170° C.
  • a heating period of the heating process ranges from 1 minute to 60 minutes.
  • the manufacturing method of the chip on film package further includes the following steps.
  • An adhesive layer is formed on the first surface and/or the second surface before the reinforcing sheet is laminated onto the first surface and/or the second surface.
  • the reinforcing sheet is disposed on the first surface and/or the second surface of the base film and exposes the chip on the base film.
  • the flexibility of the reinforcing sheet is substantially equal to or greater than the flexibility of the base film to provide flexibility and protection to the patterned circuit layer on the base film, so as to avoid fracture of fine circuit lines of the patterned circuit layer. Therefore, yield rate of the chip on film package is significantly improved.
  • FIG. 1 illustrates a cross-sectional view of a chip on film package according to an embodiment of the disclosure.
  • FIG. 2 illustrates a top view of a chip on film package according to an embodiment of the disclosure.
  • FIG. 2 A illustrates a top view of a part of components of a chip on film package according to an embodiment of the disclosure.
  • FIG. 3 illustrates a cross-sectional view of a chip on film package according to an embodiment of the disclosure.
  • FIG. 4 illustrates a cross-sectional view of a chip on film package according to an embodiment of the disclosure.
  • FIG. 5 and FIG. 6 illustrate a part of a manufacturing process of a chip on film packages according to embodiments of the disclosure.
  • FIG. 7 and FIG. 8 illustrate a part of a manufacturing process of a chip on film packages according to embodiments of the disclosure.
  • FIG. 1 illustrates a cross-sectional view of a chip on film package according to an embodiment of the disclosure.
  • FIG. 2 illustrates a top view of a chip on film package according to an embodiment of the disclosure.
  • the chip on film package 100 may include a base film 110 , a patterned circuit layer 120 , a chip 130 and a reinforcing sheet 140 .
  • the base film 110 includes a first surface 112 , a second surface 114 opposite to the first surface and a mounting region R 1 located on the first surface 112 .
  • the base film 110 may include an insulating material such as, but not limited to, polyimide (PI).
  • the patterned circuit layer 120 is disposed on the first surface 112 .
  • the patterned circuit layer 120 is formed on the first surface 112 of the base film 110 by, for example, electroplating and etching processes, etc.
  • the chip 130 may be mounted on the mounting region R 1 by surface mount technology (SMT) and electrically connected to the patterned circuit layer 120 .
  • the patterned circuit layer 120 may include a plurality of pads on which the chip 130 is mounted.
  • the reinforcing sheet 140 is disposed on the first surface 112 and/or the second surface 114 and exposes the chip 130 .
  • the reinforcing sheet 140 may be a flexible sheet and the flexibility of the reinforcing sheet 140 is substantially equal to or greater than the flexibility of the base film 110 .
  • the material of the reinforcing sheet 140 may include PI, which includes a condensation product of an acid anhydride, a diamine compound, etc.
  • the reinforcing sheet 140 may be laminated onto the first surface 112 and/or the second surface 114 of the base film by a laminating roller (e.g. the laminating roller 200 shown in FIG. 5 and FIG. 8 ).
  • the thickness of the reinforcing sheet 140 may range from 3 ⁇ m to 40 ⁇ m. With such arrangement, the reinforcing sheet 140 is configured to provide flexibility and protection to the patterned circuit layer 120 , so as to avoid fracture of fine circuit lines of the patterned circuit layer 120 .
  • the reinforcing sheet 140 is disposed on the first surface 112 as shown in FIG. 1 .
  • the reinforcing sheet 140 may include a first opening 142 exposing the mounting region R 1 and the chip 130 disposed on the mounting region R 1 .
  • the chip on film package 100 may further include a solder resist layer 150 , which is disposed on the patterned circuit layer 120 .
  • the solder resist layer 150 may include a second opening 152 exposing a part of the patterned circuit layer 120 where the chip 130 is mounted.
  • the reinforcing sheet 140 is disposed on the solder resist layer 150 and the first opening 142 exposes the second opening 152 and a part of the solder resist layer 150 surround the second opening 152 as shown in FIG. 1 .
  • the size of the reinforcing sheet 140 is substantially smaller than the size of the solder resist layer 150 , and a gap G 1 maintains between an outer edge of the reinforcing sheet 140 and an outer edge of the solder resist layer 150 .
  • the chip on film package 100 may be formed by Reel to Reel production, so a plurality of chip on film packages 100 in a roll are singularized by punch process.
  • the reinforcing sheet 140 may be disposed within a punch lines of the chip on film package 100 . Accordingly, when the chip on film package 100 is punched to be singularized, a gap may exist between the outer edge of the reinforcing sheet 140 and the outer edge (i.e.
  • the reinforcing sheet 140 may further include a plurality of chamfered corners 144 as shown in FIG. 2 to further improve peeling issues of the reinforcing sheet 140 .
  • the chip on film package 100 further includes an underfill 160 , which is disposed between the chip 130 and the base film 110 and covers the patterned circuit layer 120 exposed by the first opening 142 .
  • the underfill 160 may be further filled between a side surface of the chip 130 and a side surface of the solder resist layer 150 exposed by the first opening 142 of the reinforcing sheet 140 as shown in FIG. 1 .
  • a gap exist between the side surface of the first opening 142 and the side surface of the chip 130 .
  • the gap G 2 may exist between the side surface of the first opening 142 and a short side surface of the chip 130
  • the gap G 3 may exist between another side surface of the first opening 142 and a long side surface of the chip 130 as shown in FIG. 2 .
  • the width of the gap G 2 may be substantially the same as the width of the gap G 3 .
  • the width of the gap G 2 may be different from the width of the gap G 3 .
  • the chip on film package 100 may further include an adhesive layer 170 , which is disposed between the reinforcing sheet 140 and the base film 110 , such that the reinforcing sheet 140 is laminated and attached to the base film 110 via the adhesive layer 170 .
  • the adhesive layer 170 may be omitted, and the reinforcing sheet 140 is laminated onto the base film 110 merely by applying pressure thereon.
  • the reinforcing sheet 140 is laminated onto the base film 110 by applying both heat and pressure thereon.
  • the method of laminating the reinforcing sheet 140 onto the first surface 112 and/or the second surface 114 may further include a heating process.
  • the heating temperature of the heating process may range from 80° C. to 170° C.
  • the heating period of the heating process may range from 1 minute to 60 minutes.
  • the present embodiment is merely for illustration, and the disclosure is not limited thereto.
  • FIG. 2 A illustrates a top view of a part of components of a chip on film package according to an embodiment of the disclosure. It is noted that, for the sake of clarity and simplicity, the reinforcing sheet 140 and the solder resist layer 150 are omitted in FIG. 2 A to better illustrate the layout of the patterned circuit layer 120 .
  • the patterned circuit layer 120 may include a plurality of circuit lines 122 and a fine-pitch region R 2 .
  • the fine-pitch region R 2 has a first portion and a second portion, and the first portion is disposed closer to the chip 130 than the second portion.
  • the density of the circuit lines 122 is high, so that a pitch P 1 between adjacent two of the circuit lines 122 may be extremely fine. Accordingly, the width and the thickness of each circuit line 122 is also limited.
  • a pitch P 1 between adjacent two of the circuit lines 122 in the first portion may be substantially smaller than 20 ⁇ m
  • a thickness of each of the circuit lines 122 may be less than 8 ⁇ m
  • a width of each of the circuit lines 122 may range from 5 ⁇ m to 11 ⁇ m
  • the pitch in the second portion may be substantially greater than the pitch in the first portion. Therefore, the circuit lines 122 in the fine-pitch region R 2 would be easily fractured due to lacking of mechanical strength.
  • the reinforcing sheet 140 at least covers the circuit lines 122 in the fine-pitch region R 2 so as to protect the circuit lines 122 underneath and also provide flexibility to the circuit lines 122 and the base film 110 . Accordingly, when the chip on film package 100 suffers impact or bending, the fracture of the circuit lines 122 in the fine-pitch region R 2 can be significantly improved, so as to increase the yield rate of the chip on film package 100 .
  • the reinforcing sheet 140 may also covers the part of the base film 110 where circuit lines 122 turns in direction (e.g. the circled region in FIG. 2 A ).
  • FIG. 3 illustrates a cross-sectional view of a chip on film package according to an embodiment of the disclosure.
  • the chip on film package 100 a shown in FIG. 3 contains many features same as or similar to the chip on film package 100 disclosed earlier with FIG. 1 to FIG. 2 A .
  • detail description of same or similar features may be omitted, and the same or similar reference numbers denote the same or like components.
  • the main differences between the chip on film package 100 a shown in FIG. 3 and the chip on film package 100 shown in FIG. 1 are described as follows.
  • the reinforcing sheet 140 is disposed on the second surface 114 of the base film 110 .
  • the reinforcing sheet 140 is laminated and attached to the base film 110 via the adhesive layer 170 .
  • the adhesive layer 170 may be omitted, and the reinforcing sheet 140 is laminated onto the base film 110 merely by applying pressure thereon.
  • the method of laminating the reinforcing sheet 140 onto the second surface 114 may further include a heating process.
  • the heating temperature of the heating process may range from 80° C. to 170° C., and the heating period of the heating process may range from 1 minute to 60 minutes.
  • the reinforcing sheet 140 may be disposed on the entire second surface 114 of the base film 110 .
  • a gap may exist between the outer edge of the reinforcing sheet 140 and the outer edge (i.e. the punch line) of the chip on film package 100 , so as to reduce the issue of the reinforcing sheet 140 peeling from the base film 110 .
  • the reinforcing sheet 140 may further include a plurality of chamfered corners (similar to the chamfered corners 144 shown in FIG. 2 ) to further improve peeling issues of the reinforcing sheet 140 .
  • the reinforcing sheet 140 may be disposed on the region of the second surface 114 corresponding to the fine-pitch region R 2 of the first surface 112 , so as to provide flexibility to the circuit lines 122 and the base film 110 .
  • the reinforcing sheet 140 may be disposed on the region of the second surface 114 right beneath the fine-pitch region R 2 of the first surface 112 .
  • the reinforcing sheet 140 may also be disposed on the region of the second surface 114 right beneath the circled region in FIG. 2 A .
  • FIG. 4 illustrates a cross-sectional view of a chip on film package according to an embodiment of the disclosure.
  • the chip on film package 100 b shown in FIG. 4 contains many features same as or similar to the chip on film packages 100 , 100 a disclosed earlier with FIG. 1 to FIG. 3 .
  • detail description of same or similar features may be omitted, and the same or similar reference numbers denote the same or like components.
  • the main differences between the chip on film package 100 b shown in FIG. 4 and the chip on film packages 100 , 100 a shown in FIG. 1 to FIG. 3 are described as follows.
  • the reinforcing sheet 140 may include a first reinforcing sheet 140 a disposed on the first surface 112 and a second reinforcing sheet 140 b disposed on the second surface 114 .
  • the first reinforcing sheet 140 a is directly disposed on the patterned circuit layer 120 and the first opening 142 exposes a part of the patterned circuit layer 120 where the chip 130 is mounted.
  • the solder resist layer 150 is omitted and is replaced by the reinforcing sheet 140 .
  • the adhesive layer 170 is also omitted herein.
  • the second reinforcing sheet 140 b is directly disposed on the second surface 114 without the help of the adhesive layer 170 .
  • the reinforcing sheets 140 a , 140 b are laminated onto the base film 110 merely by applying pressure thereon.
  • the step of laminating the reinforcing sheets 140 a , 140 b onto the first surface 112 and the second surface 114 may further include a heating process.
  • the heating temperature of the heating process may range from, but not limited to, 80° C. to 170° C.
  • the heating period of the heating process may range from, but not limited to, 1 minute to 60 minutes.
  • FIG. 5 and FIG. 6 illustrate a part of a manufacturing process of a chip on film packages according to embodiments of the disclosure.
  • the reinforcing sheet 140 may be laminated onto the first surface 112 and/or the second surface 114 before the chip is mounted on the mounting region R 1 . It is noted that the reinforcing sheet 140 being laminated onto the first surface 112 is depicted in FIG. 5 for illustration purpose, but the disclosure is not limited thereto. In other embodiments, the reinforcing sheet 140 may also be laminated onto the second surface 114 .
  • the base film 110 is firstly provided, and the patterned circuit layer 120 is then formed on the first surface 112 of the base film 110 .
  • the solder resist layer 150 can be optionally formed on the patterned circuit layer 120 .
  • the reinforcing sheet 140 is laminated onto the first surface 112 and/or the second surface 114 of the base film 110 , and the chip 130 is then mounted on the mounting region R 1 of the base film 110 to be electrically connected to the patterned circuit layer 120 .
  • the reinforcing sheet 140 may include one or more first openings 142 (multiple first openings 142 are illustrated herein) corresponding to the mounting regions R 1 of the base film 110 . Then, the reinforcing sheet 140 including the first openings 142 is laminated onto the first surface 112 (and/or the second surface 114 ) by a laminating roller 200 , which is configured to roll over the reinforcing sheet 140 on the first surface 112 and/or the second surface 114 to apply pressure evenly on the reinforcing sheet 140 .
  • two laminating rollers 200 may be applied to both sides of the base film respectively to laminate the reinforcing sheets 140 a , 140 b onto the first surface 112 and the second surface 114 at the same time.
  • an adhesive layer e.g. the adhesive layer 170 as shown in FIG. 1 and FIG. 3
  • the disclosure is not limited thereto.
  • one or more chips 130 are disposed in the first openings 142 respectively to be mounted on the mounting regions R 1 of the base film 110 , and the chips 130 are electrically connected to the patterned circuit layer 120 . Then, the resulting structure is punched to be singularized and form a plurality of chip on film packages 100 / 100 a / 100 b as shown in FIG. 1 , FIG. 3 or FIG. 4 .
  • FIG. 7 and FIG. 8 illustrate a part of a manufacturing process of a chip on film packages according to embodiments of the disclosure.
  • the reinforcing sheet 140 may be laminated onto the second surface 114 after the chip is mounted on the mounting region R 1 .
  • the base film 110 is firstly provided, and the patterned circuit layer 120 is then formed on the first surface 112 of the base film 110 .
  • the solder resist layer 150 can be optionally formed on the patterned circuit layer 120 .
  • the chip 130 is mounted on the mounting region R 1 of the base film 110 to be electrically connected to the patterned circuit layer 120 , and the reinforcing sheet 140 is then laminated onto the second surface 114 of the base film 110 .
  • one or more chips 130 are mounted on the mounting regions R 1 of the base film 110 are electrically connected to the patterned circuit layer 120 .
  • the reinforcing sheet 140 is laminated onto the second surface 114 by the laminating roller 200 , which is configured to roll over the reinforcing sheet 140 on the second surface 114 to apply pressure evenly on the reinforcing sheet 140 .
  • an adhesive layer e.g. the adhesive layer 170 as shown in FIG. 1 and FIG. 3
  • the resulting structure is punched to be singularized and form a plurality of chip on film packages 100 a as shown in FIG. 3 .
  • the reinforcing sheet is disposed on the first surface and/or the second surface of the base film and exposes the chip on the base film.
  • the flexibility of the reinforcing sheet is substantially equal to or greater than the flexibility of the base film to provide flexibility and protection to the patterned circuit layer on the base film, so as to avoid fracture of fine circuit lines of the patterned circuit layer.
  • the reinforcing sheet may be disposed at least on the region of the base film corresponding to the fine-pitch region of the patterned circuit layer to provide flexibility to the patterned circuit layer and the base film. Accordingly, when the chip on film package suffers impact or bending, the fracture of the patterned circuit layer in the fine-pitch region can be avoided. Therefore, yield rate of the chip on film package is significantly improved.

Abstract

A chip on film package includes a base film, a patterned circuit layer, a chip and a reinforcing sheet. The base film includes a first surface, a second surface opposite to the first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The chip is mounted on the mounting region and electrically connected to the patterned circuit layer. The reinforcing sheet is disposed on the first surface and/or the second surface and exposes the chip, wherein a flexibility of the reinforcing sheet is substantially equal to or greater than a flexibility of the base film.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This is a continuation application of patent application Ser. No. 15/821,846, filed on Nov. 24, 2017, which claims the priority benefit of U.S. provisional application Ser. No. 62/551,755, filed on Aug. 29, 2017 and is now allowed. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
BACKGROUND 1. Technical Field
The present disclosure generally relates to a chip package and a manufacturing method of the chip package, in particular, to a chip on film package and a manufacturing method of the chip on film package.
2. Description of Related Art
To expand the market area of display devices such as liquid crystal displays (LCDs), with promotion of low cost, large scale, and high performance, more pixels have to be integrated in a small area. Thus, as a lead pitch of a driver integrated circuit (IC) which controls each pixel becomes finer within the display device, various packaging methods have been developed.
Packaging methods mainly used in a display device field include a tape carrier packaging (TCP) method, a chip on glass (COG) packaging method, a chip on film (COF) packaging method, and the like. These methods are referred to as wireless methods. To promote reduction in fabrication cost and improvement in yield due to a fine pitch, the share of COF technology in the packaging market has gradually increased since the late 1990s.
Since COF technology uses a base film on which fine wiring patterns are formed, the distance and pitch between neighboring leads can be minimized, thus maximizing lead density. Further, this COF technology can employ semiconductor chips with a large number of chip pads and fine pitch or large-sized semiconductor chips. Therefore, the COF technology using the base film achieves high-integrated and multi-functional semiconductor device.
The COF package has an excellent bending force and a good flexibility, compared to the conventional chip package, is of high quality. However, as the demand for the IC packages of higher performances increases, the external terminals of such IC package are required not only to be increased in number but also to be more fine pitch. As the level of the fine pitch of the external contacts of the IC package rises, naturally it becomes necessary for the circuits on the base film of COF package to have fine pitch contacts in order to electrically connect the external terminals of the IC package. The thickness of the fine-pitch circuit is also reduces accordingly, which makes the fine-pitch circuit more vulnerable and easier to break.
SUMMARY
Accordingly, the present disclosure is directed to a chip on film package and a manufacturing method of the chip on film package with favourable yield rate.
The present disclosure provides a chip on film package includes a base film, a patterned circuit layer, a chip and a reinforcing sheet. The base film includes a first surface, a second surface opposite to the first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The chip is mounted on the mounting region and electrically connected to the patterned circuit layer. The reinforcing sheet is disposed on the first surface and/or the second surface and exposes the chip, wherein a flexibility of the reinforcing sheet is substantially equal to or greater than a flexibility of the base film.
According to an embodiment of the present disclosure, the reinforcing sheet is disposed on the first surface and includes a first opening exposing the chip.
According to an embodiment of the present disclosure, the reinforcing sheet directly disposed on the patterned circuit layer and the first opening exposes a part of the patterned circuit layer where the chip is mounted.
According to an embodiment of the present disclosure, the chip on film package further includes a solder resist layer disposed on the patterned circuit layer and including a second opening exposing a part of the patterned circuit layer where the chip is mounted, the reinforcing sheet is disposed on the solder resist layer and exposes the second opening.
According to an embodiment of the present disclosure, a size of the reinforcing sheet is substantially smaller than a size of the solder resist layer, and a gap maintains between an outer edge of the reinforcing sheet and an outer edge of the solder resist layer.
According to an embodiment of the present disclosure, the chip on film package further includes an underfill disposed between the chip and the base film and covering the patterned circuit layer exposed by the first opening.
According to an embodiment of the present disclosure, the reinforcing sheet is disposed on the second surface.
According to an embodiment of the present disclosure, the reinforcing sheet includes a plurality of chamfered corners.
According to an embodiment of the present disclosure, the chip on film package further includes an adhesive layer disposed between the reinforcing sheet and the base film.
According to an embodiment of the present disclosure, the patterned circuit layer includes a plurality of circuit lines and a fine-pitch region, and the reinforcing sheet covers the circuit lines in the fine-pitch region.
According to an embodiment of the present disclosure, a pitch between adjacent two of the circuit lines in the fine-pitch region is substantially smaller than 20 μm, and a width of each of the circuit lines ranges from 5 μm to 11 μm.
According to an embodiment of the present disclosure, a material of the reinforcing sheet includes polyimide (PI).
According to an embodiment of the present disclosure, a thickness of the reinforcing sheet ranges from 3 μm to 40 μm.
The present disclosure provides a manufacturing method of a chip on film package. The method includes the following steps. A base film is provided, wherein the base film includes a first surface, a second surface opposite to the first surface and a mounting region located on the first surface. A patterned circuit layer is formed on the first surface. A chip is mounted on the mounting region, wherein the chip is electrically connected to the patterned circuit layer. A reinforcing sheet is laminated onto the first surface and/or the second surface, wherein a flexibility of the reinforcing sheet is substantially equal to or greater than a flexibility of the base film.
According to an embodiment of the present disclosure, the reinforcing sheet is laminated onto the first surface and/or the second surface before the chip is mounted on the mounting region, and the reinforcing sheet covers patterned circuit layer and exposing the mounting region.
According to an embodiment of the present disclosure, the reinforcing sheet is laminated onto the second surface after the chip is mounted on the mounting region.
According to an embodiment of the present disclosure, the reinforcing sheet is laminated onto the first surface and/or the second surface by a laminating roller configured to roll over the first surface and/or the second surface.
According to an embodiment of the present disclosure, the step of laminating the reinforcing sheet onto the first surface and/or the second surface further includes a heating process.
According to an embodiment of the present disclosure, a heating temperature of the heating process ranges from 80° C. to 170° C., and a heating period of the heating process ranges from 1 minute to 60 minutes.
According to an embodiment of the present disclosure, the manufacturing method of the chip on film package further includes the following steps. An adhesive layer is formed on the first surface and/or the second surface before the reinforcing sheet is laminated onto the first surface and/or the second surface.
In light of the foregoing, in the chip on film package of the disclosure, the reinforcing sheet is disposed on the first surface and/or the second surface of the base film and exposes the chip on the base film. Moreover, the flexibility of the reinforcing sheet is substantially equal to or greater than the flexibility of the base film to provide flexibility and protection to the patterned circuit layer on the base film, so as to avoid fracture of fine circuit lines of the patterned circuit layer. Therefore, yield rate of the chip on film package is significantly improved.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.
FIG. 1 illustrates a cross-sectional view of a chip on film package according to an embodiment of the disclosure.
FIG. 2 illustrates a top view of a chip on film package according to an embodiment of the disclosure.
FIG. 2A illustrates a top view of a part of components of a chip on film package according to an embodiment of the disclosure.
FIG. 3 illustrates a cross-sectional view of a chip on film package according to an embodiment of the disclosure.
FIG. 4 illustrates a cross-sectional view of a chip on film package according to an embodiment of the disclosure.
FIG. 5 and FIG. 6 illustrate a part of a manufacturing process of a chip on film packages according to embodiments of the disclosure.
FIG. 7 and FIG. 8 illustrate a part of a manufacturing process of a chip on film packages according to embodiments of the disclosure.
 DESCRIPTION OF THE EMBODIMENTS
Reference will now be made in detail to the present preferred embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
FIG. 1 illustrates a cross-sectional view of a chip on film package according to an embodiment of the disclosure. FIG. 2 illustrates a top view of a chip on film package according to an embodiment of the disclosure. Referring to FIG. 1 and FIG. 2 , in some embodiments, the chip on film package 100 may include a base film 110, a patterned circuit layer 120, a chip 130 and a reinforcing sheet 140. The base film 110 includes a first surface 112, a second surface 114 opposite to the first surface and a mounting region R1 located on the first surface 112. In some embodiments, the base film 110 may include an insulating material such as, but not limited to, polyimide (PI). The patterned circuit layer 120 is disposed on the first surface 112. In some embodiments, the patterned circuit layer 120 is formed on the first surface 112 of the base film 110 by, for example, electroplating and etching processes, etc. The chip 130 may be mounted on the mounting region R1 by surface mount technology (SMT) and electrically connected to the patterned circuit layer 120. In some embodiments, the patterned circuit layer 120 may include a plurality of pads on which the chip 130 is mounted.
In some embodiments, the reinforcing sheet 140 is disposed on the first surface 112 and/or the second surface 114 and exposes the chip 130. In some embodiments, the reinforcing sheet 140 may be a flexible sheet and the flexibility of the reinforcing sheet 140 is substantially equal to or greater than the flexibility of the base film 110. In some embodiments, the material of the reinforcing sheet 140 may include PI, which includes a condensation product of an acid anhydride, a diamine compound, etc. The reinforcing sheet 140 may be laminated onto the first surface 112 and/or the second surface 114 of the base film by a laminating roller (e.g. the laminating roller 200 shown in FIG. 5 and FIG. 8 ). The thickness of the reinforcing sheet 140 may range from 3 μm to 40 μm. With such arrangement, the reinforcing sheet 140 is configured to provide flexibility and protection to the patterned circuit layer 120, so as to avoid fracture of fine circuit lines of the patterned circuit layer 120.
In one of the implementations, the reinforcing sheet 140 is disposed on the first surface 112 as shown in FIG. 1 . The reinforcing sheet 140 may include a first opening 142 exposing the mounting region R1 and the chip 130 disposed on the mounting region R1. In some embodiments, the chip on film package 100 may further include a solder resist layer 150, which is disposed on the patterned circuit layer 120. The solder resist layer 150 may include a second opening 152 exposing a part of the patterned circuit layer 120 where the chip 130 is mounted. In such embodiments, the reinforcing sheet 140 is disposed on the solder resist layer 150 and the first opening 142 exposes the second opening 152 and a part of the solder resist layer 150 surround the second opening 152 as shown in FIG. 1 .
In addition, the size of the reinforcing sheet 140 is substantially smaller than the size of the solder resist layer 150, and a gap G1 maintains between an outer edge of the reinforcing sheet 140 and an outer edge of the solder resist layer 150. In some embodiments, the chip on film package 100 may be formed by Reel to Reel production, so a plurality of chip on film packages 100 in a roll are singularized by punch process. In some embodiments, the reinforcing sheet 140 may be disposed within a punch lines of the chip on film package 100. Accordingly, when the chip on film package 100 is punched to be singularized, a gap may exist between the outer edge of the reinforcing sheet 140 and the outer edge (i.e. the punch line) of the chip on film package 100. As such, the issue of the reinforcing sheet 140 peeling from the base film 110 can be reduced. Moreover, the reinforcing sheet 140 may further include a plurality of chamfered corners 144 as shown in FIG. 2 to further improve peeling issues of the reinforcing sheet 140.
In some embodiments, the chip on film package 100 further includes an underfill 160, which is disposed between the chip 130 and the base film 110 and covers the patterned circuit layer 120 exposed by the first opening 142. In some embodiments, the underfill 160 may be further filled between a side surface of the chip 130 and a side surface of the solder resist layer 150 exposed by the first opening 142 of the reinforcing sheet 140 as shown in FIG. 1 . In the present embodiment, a gap exist between the side surface of the first opening 142 and the side surface of the chip 130. For example, the gap G2 may exist between the side surface of the first opening 142 and a short side surface of the chip 130, and the gap G3 may exist between another side surface of the first opening 142 and a long side surface of the chip 130 as shown in FIG. 2 . Preferably but not limitedly, the width of the gap G2 may be substantially the same as the width of the gap G3. Alternatively, the width of the gap G2 may be different from the width of the gap G3.
In some embodiments, the chip on film package 100 may further include an adhesive layer 170, which is disposed between the reinforcing sheet 140 and the base film 110, such that the reinforcing sheet 140 is laminated and attached to the base film 110 via the adhesive layer 170. In some embodiments, the adhesive layer 170 may be omitted, and the reinforcing sheet 140 is laminated onto the base film 110 merely by applying pressure thereon. In some embodiments, the reinforcing sheet 140 is laminated onto the base film 110 by applying both heat and pressure thereon. Namely, the method of laminating the reinforcing sheet 140 onto the first surface 112 and/or the second surface 114 may further include a heating process. For example, the heating temperature of the heating process may range from 80° C. to 170° C., and the heating period of the heating process may range from 1 minute to 60 minutes. The present embodiment is merely for illustration, and the disclosure is not limited thereto.
FIG. 2A illustrates a top view of a part of components of a chip on film package according to an embodiment of the disclosure. It is noted that, for the sake of clarity and simplicity, the reinforcing sheet 140 and the solder resist layer 150 are omitted in FIG. 2A to better illustrate the layout of the patterned circuit layer 120. Referring to FIG. 1 and FIG. 2A, in some embodiments, the patterned circuit layer 120 may include a plurality of circuit lines 122 and a fine-pitch region R2. The fine-pitch region R2 has a first portion and a second portion, and the first portion is disposed closer to the chip 130 than the second portion. In the fine-pitch region R2, the density of the circuit lines 122 is high, so that a pitch P1 between adjacent two of the circuit lines 122 may be extremely fine. Accordingly, the width and the thickness of each circuit line 122 is also limited. For example, a pitch P1 between adjacent two of the circuit lines 122 in the first portion may be substantially smaller than 20 μm, a thickness of each of the circuit lines 122 may be less than 8 μm, a width of each of the circuit lines 122 may range from 5 μm to 11 μm, and the pitch in the second portion may be substantially greater than the pitch in the first portion. Therefore, the circuit lines 122 in the fine-pitch region R2 would be easily fractured due to lacking of mechanical strength. In such embodiments, the reinforcing sheet 140 at least covers the circuit lines 122 in the fine-pitch region R2 so as to protect the circuit lines 122 underneath and also provide flexibility to the circuit lines 122 and the base film 110. Accordingly, when the chip on film package 100 suffers impact or bending, the fracture of the circuit lines 122 in the fine-pitch region R2 can be significantly improved, so as to increase the yield rate of the chip on film package 100. In other embodiments, for similar purposes, the reinforcing sheet 140 may also covers the part of the base film 110 where circuit lines 122 turns in direction (e.g. the circled region in FIG. 2A).
FIG. 3 illustrates a cross-sectional view of a chip on film package according to an embodiment of the disclosure. It is noted that the chip on film package 100 a shown in FIG. 3 contains many features same as or similar to the chip on film package 100 disclosed earlier with FIG. 1 to FIG. 2A. For purpose of clarity and simplicity, detail description of same or similar features may be omitted, and the same or similar reference numbers denote the same or like components. The main differences between the chip on film package 100 a shown in FIG. 3 and the chip on film package 100 shown in FIG. 1 are described as follows.
Referring to FIG. 3 , in some embodiments, the reinforcing sheet 140 is disposed on the second surface 114 of the base film 110. In the present embodiments, the reinforcing sheet 140 is laminated and attached to the base film 110 via the adhesive layer 170. In some embodiments, the adhesive layer 170 may be omitted, and the reinforcing sheet 140 is laminated onto the base film 110 merely by applying pressure thereon. In some embodiments, the method of laminating the reinforcing sheet 140 onto the second surface 114 may further include a heating process. For example, the heating temperature of the heating process may range from 80° C. to 170° C., and the heating period of the heating process may range from 1 minute to 60 minutes.
In some embodiments, the reinforcing sheet 140 may be disposed on the entire second surface 114 of the base film 110. In other embodiments, a gap may exist between the outer edge of the reinforcing sheet 140 and the outer edge (i.e. the punch line) of the chip on film package 100, so as to reduce the issue of the reinforcing sheet 140 peeling from the base film 110. Moreover, the reinforcing sheet 140 may further include a plurality of chamfered corners (similar to the chamfered corners 144 shown in FIG. 2 ) to further improve peeling issues of the reinforcing sheet 140. Alternatively, the reinforcing sheet 140 may be disposed on the region of the second surface 114 corresponding to the fine-pitch region R2 of the first surface 112, so as to provide flexibility to the circuit lines 122 and the base film 110. For example, the reinforcing sheet 140 may be disposed on the region of the second surface 114 right beneath the fine-pitch region R2 of the first surface 112. In other embodiments, the reinforcing sheet 140 may also be disposed on the region of the second surface 114 right beneath the circled region in FIG. 2A.
FIG. 4 illustrates a cross-sectional view of a chip on film package according to an embodiment of the disclosure. It is noted that the chip on film package 100 b shown in FIG. 4 contains many features same as or similar to the chip on film packages 100, 100 a disclosed earlier with FIG. 1 to FIG. 3 . For purpose of clarity and simplicity, detail description of same or similar features may be omitted, and the same or similar reference numbers denote the same or like components. The main differences between the chip on film package 100 b shown in FIG. 4 and the chip on film packages 100, 100 a shown in FIG. 1 to FIG. 3 are described as follows.
Referring to FIG. 4 , in some embodiments, the reinforcing sheet 140 may include a first reinforcing sheet 140 a disposed on the first surface 112 and a second reinforcing sheet 140 b disposed on the second surface 114. The first reinforcing sheet 140 a is directly disposed on the patterned circuit layer 120 and the first opening 142 exposes a part of the patterned circuit layer 120 where the chip 130 is mounted. Namely, in the present embodiments, the solder resist layer 150 is omitted and is replaced by the reinforcing sheet 140. The adhesive layer 170 is also omitted herein. Similarly, the second reinforcing sheet 140 b is directly disposed on the second surface 114 without the help of the adhesive layer 170. In the present embodiment, the reinforcing sheets 140 a, 140 b are laminated onto the base film 110 merely by applying pressure thereon. In addition, the step of laminating the reinforcing sheets 140 a, 140 b onto the first surface 112 and the second surface 114 may further include a heating process. For example, the heating temperature of the heating process may range from, but not limited to, 80° C. to 170° C., and the heating period of the heating process may range from, but not limited to, 1 minute to 60 minutes.
FIG. 5 and FIG. 6 illustrate a part of a manufacturing process of a chip on film packages according to embodiments of the disclosure. Referring to FIG. 1 , FIG. 5 and FIG. 6 , in some embodiments, the reinforcing sheet 140 may be laminated onto the first surface 112 and/or the second surface 114 before the chip is mounted on the mounting region R1. It is noted that the reinforcing sheet 140 being laminated onto the first surface 112 is depicted in FIG. 5 for illustration purpose, but the disclosure is not limited thereto. In other embodiments, the reinforcing sheet 140 may also be laminated onto the second surface 114. Accordingly, in the manufacturing process of the chip on film package 100/100 a/100 b, the base film 110 is firstly provided, and the patterned circuit layer 120 is then formed on the first surface 112 of the base film 110. In some embodiments, the solder resist layer 150 can be optionally formed on the patterned circuit layer 120. Next, the reinforcing sheet 140 is laminated onto the first surface 112 and/or the second surface 114 of the base film 110, and the chip 130 is then mounted on the mounting region R1 of the base film 110 to be electrically connected to the patterned circuit layer 120.
Referring to FIG. 5 , in some embodiments, the reinforcing sheet 140 may include one or more first openings 142 (multiple first openings 142 are illustrated herein) corresponding to the mounting regions R1 of the base film 110. Then, the reinforcing sheet 140 including the first openings 142 is laminated onto the first surface 112 (and/or the second surface 114) by a laminating roller 200, which is configured to roll over the reinforcing sheet 140 on the first surface 112 and/or the second surface 114 to apply pressure evenly on the reinforcing sheet 140. For the embodiments of the reinforcing sheets 140 a, 140 b being laminated onto both the first surface 112 and the second surface 114, two laminating rollers 200 may be applied to both sides of the base film respectively to laminate the reinforcing sheets 140 a, 140 b onto the first surface 112 and the second surface 114 at the same time. In some embodiments, an adhesive layer (e.g. the adhesive layer 170 as shown in FIG. 1 and FIG. 3 ) may be formed on the first surface 112 and/or the second surface 114 before the reinforcing sheet 140 is laminated, but the disclosure is not limited thereto.
Then, referring to FIG. 6 , one or more chips 130 (multiple chips 130 are illustrated herein) are disposed in the first openings 142 respectively to be mounted on the mounting regions R1 of the base film 110, and the chips 130 are electrically connected to the patterned circuit layer 120. Then, the resulting structure is punched to be singularized and form a plurality of chip on film packages 100/100 a/100 b as shown in FIG. 1 , FIG. 3 or FIG. 4 .
FIG. 7 and FIG. 8 illustrate a part of a manufacturing process of a chip on film packages according to embodiments of the disclosure. Referring to FIG. 3 , FIG. 7 and FIG. 8 , in the embodiments of the reinforcing sheet 140 being laminated onto the second surface 114, the reinforcing sheet 140 may be laminated onto the second surface 114 after the chip is mounted on the mounting region R1. Accordingly, in the manufacturing process of the chip on film package 100 a, the base film 110 is firstly provided, and the patterned circuit layer 120 is then formed on the first surface 112 of the base film 110. In some embodiments, the solder resist layer 150 can be optionally formed on the patterned circuit layer 120. Next, the chip 130 is mounted on the mounting region R1 of the base film 110 to be electrically connected to the patterned circuit layer 120, and the reinforcing sheet 140 is then laminated onto the second surface 114 of the base film 110.
Referring to FIG. 7 , in some embodiments, one or more chips 130 (multiple chips 130 are illustrated herein) are mounted on the mounting regions R1 of the base film 110 are electrically connected to the patterned circuit layer 120. Then, the reinforcing sheet 140 is laminated onto the second surface 114 by the laminating roller 200, which is configured to roll over the reinforcing sheet 140 on the second surface 114 to apply pressure evenly on the reinforcing sheet 140. In some embodiments, an adhesive layer (e.g. the adhesive layer 170 as shown in FIG. 1 and FIG. 3 ) may be formed on the second surface 114 before the reinforcing sheet 140 is laminated, but the disclosure is not limited thereto. Then, the resulting structure is punched to be singularized and form a plurality of chip on film packages 100 a as shown in FIG. 3 .
In sum, in the chip on film package of the disclosure, the reinforcing sheet is disposed on the first surface and/or the second surface of the base film and exposes the chip on the base film. The flexibility of the reinforcing sheet is substantially equal to or greater than the flexibility of the base film to provide flexibility and protection to the patterned circuit layer on the base film, so as to avoid fracture of fine circuit lines of the patterned circuit layer. In addition, the reinforcing sheet may be disposed at least on the region of the base film corresponding to the fine-pitch region of the patterned circuit layer to provide flexibility to the patterned circuit layer and the base film. Accordingly, when the chip on film package suffers impact or bending, the fracture of the patterned circuit layer in the fine-pitch region can be avoided. Therefore, yield rate of the chip on film package is significantly improved.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.

Claims (28)

What is claimed is:
1. A chip on film package, comprising:
a base film comprising a first surface, a second surface opposite to the first surface and a mounting region located on the first surface;
a patterned circuit layer disposed on the first surface;
a chip mounted on the mounting region and electrically connected to the patterned circuit layer; and
a reinforcing sheet disposed on the first surface and/or the second surface and exposing the chip, wherein a flexibility of the reinforcing sheet is substantially greater than a flexibility of the base film,
wherein the patterned circuit layer comprises a plurality of circuit lines and a fine-pitch region, and the reinforcing sheet at least covers the circuit lines in the fine-pitch region, and a pitch between adjacent two of the circuit lines in the fine-pitch region is substantially smaller than a pitch between adjacent two of the circuit lines in the rest of the patterned circuit layer and is substantially smaller than 20 μm, and a width of each of the circuit lines ranges from 5 μm to 11 μm.
2. The chip on film package according to claim 1, wherein the reinforcing sheet is disposed on the first surface and comprises a first opening exposing the chip.
3. The chip on film package according to claim 2, wherein the reinforcing sheet is directly disposed on the patterned circuit layer and the first opening exposes a part of the patterned circuit layer where the chip is mounted.
4. The chip on film package according to claim 2, further comprising a solder resist layer disposed on the patterned circuit layer and comprising a second opening exposing a part of the patterned circuit layer where the chip is mounted, the reinforcing sheet is disposed on the solder resist layer and exposes the second opening.
5. The chip on film package according to claim 4, wherein a size of the reinforcing sheet is substantially smaller than a size of the solder resist layer, and a gap maintains between an outer edge of the reinforcing sheet and an outer edge of the solder resist layer.
6. The chip on film package according to claim 2, further comprising an underfill disposed between the chip and the base film and covering the patterned circuit layer exposed by the first opening.
7. The chip on film package according to claim 1, wherein the reinforcing sheet is disposed on the second surface.
8. The chip on film package according to claim 1, wherein the reinforcing sheet comprises a plurality of chamfered corners.
9. The chip on film package according to claim 1, further comprising an adhesive layer disposed between the reinforcing sheet and the base film.
10. The chip on film package according to claim 1, wherein a material of the reinforcing sheet comprises polyimide (PI).
11. The chip on film package according to claim 1, wherein a thickness of the reinforcing sheet ranges from 3 μm to 40 μm.
12. A manufacturing method of a chip on film package, comprising:
providing a base film, wherein the base film comprises a first surface, a second surface opposite to the first surface and a mounting region located on the first surface;
forming a patterned circuit layer on the first surface, wherein the patterned circuit layer comprises a plurality of circuit lines and a fine-pitch region, and a pitch between adjacent two of the circuit lines in the fine-pitch region is substantially smaller than a pitch between adjacent two of the circuit lines in the rest of the patterned circuit layer and is substantially smaller than 20 μm, and a width of each of the circuit lines ranges from 5 μm to 11 μm;
mounting a chip on the mounting region, wherein the chip is electrically connected to the patterned circuit layer; and
laminating a reinforcing sheet onto the first surface and/or the second surface, wherein a flexibility of the reinforcing sheet is substantially greater than a flexibility of the base film, wherein the reinforcing sheet at least covers the circuit lines in the fine-pitch region.
13. The manufacturing method of the chip on film package according to claim 12, wherein the reinforcing sheet is laminated onto the first surface and/or the second surface before the chip is mounted on the mounting region, and the reinforcing sheet covers patterned circuit layer and exposing the mounting region.
14. The manufacturing method of the chip on film package according to claim 12, wherein the reinforcing sheet is laminated onto the second surface after the chip is mounted on the mounting region.
15. The manufacturing method of the chip on film package according to claim 12, wherein the reinforcing sheet is laminated onto the first surface and/or the second surface by a laminating roller configured to roll over the reinforcing sheet on the first surface and/or the second surface.
16. The manufacturing method of the chip on film package according to claim 12, the step of laminating the reinforcing sheet onto the first surface and/or the second surface further comprises a heating process.
17. The manufacturing method of the chip on film package according to claim 16, wherein a heating temperature of the heating process ranges from 80° C. to 170° C., and a heating period of the heating process ranges from 1 minute to 60 minutes.
18. The manufacturing method of the chip on film package according to claim 12, further comprising:
forming an adhesive layer on the first surface and/or the second surface before the reinforcing sheet is laminated onto the first surface and/or the second surface.
19. A chip on film package, comprising:
a base film comprising a first surface, a second surface opposite to the first surface and a mounting region located on the first surface;
a patterned circuit layer disposed on the first surface;
a chip mounted on the mounting region and electrically connected to the patterned circuit layer; and
a reinforcing sheet disposed on the first surface and/or the second surface and exposing the chip, wherein a flexibility of the reinforcing sheet is substantially greater than a flexibility of the base film,
wherein the patterned circuit layer comprises a plurality of circuit lines and a fine-pitch region, which has a first portion and a second portion, the pitch in the second portion is substantially greater than the pitch in the first portion, and the reinforcing sheet at least covers the circuit lines in the first portion, wherein the pitch between adjacent two of the circuit lines in the fine-pitch region is substantially smaller than 20 μm, and a width of each of the circuit lines ranges from 5 μm to 11 μm.
20. The chip on film package according to claim 19, wherein the first portion is disposed closer to the chip than the second portion.
21. The chip on film package according to claim 19, wherein the reinforcing sheet is disposed on the first surface and comprises a first opening exposing the chip.
22. The chip on film package according to claim 21, wherein the reinforcing sheet is directly disposed on the patterned circuit layer and the first opening exposes a part of the patterned circuit layer where the chip is mounted.
23. The chip on film package according to claim 21, further comprising a solder resist layer disposed on the patterned circuit layer and comprising a second opening exposing a part of the patterned circuit layer where the chip is mounted, the reinforcing sheet is disposed on the solder resist layer and exposes the second opening.
24. The chip on film package according to claim 23, wherein a size of the reinforcing sheet is substantially smaller than a size of the solder resist layer, and a gap maintains between an outer edge of the reinforcing sheet and an outer edge of the solder resist layer.
25. The chip on film package according to claim 19, wherein the reinforcing sheet is disposed on the second surface.
26. The chip on film package according to claim 19, wherein the reinforcing sheet comprises a plurality of chamfered corners.
27. The chip on film package according to claim 19, wherein a material of the reinforcing sheet comprises polyimide (PI).
28. The chip on film package according to claim 19, wherein a thickness of the reinforcing sheet ranges from 3 μm to 40 μm.
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Publication number Priority date Publication date Assignee Title
TWI727912B (en) * 2019-06-19 2021-05-11 萬潤科技股份有限公司 Method and equipment for attaching heat-dissipating rubber pad

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030109669A1 (en) * 2000-04-20 2003-06-12 Jiro Sadanobu Polyimide film and process for producing the same
US20050110049A1 (en) * 2003-10-27 2005-05-26 Tatsuhiro Urushido Semiconductor device and its manufacturing method, electronic module, and electronic unit
US20060068164A1 (en) * 2004-09-29 2006-03-30 Mitsui Mining & Smelting Co., Ltd. Film carrier tape for mounting electronic devices thereon and flexible substrate
US20060289939A1 (en) * 2005-06-23 2006-12-28 Samsung Electronics Co., Ltd. Array substrate and display device having the same
US20070007649A1 (en) * 2005-07-07 2007-01-11 Taiwan Semiconductor Manufacturing Company, Ltd. Low cte substrates for use with low-k flip-chip package devices
US20080078491A1 (en) * 2006-09-19 2008-04-03 Seiko Epson Corporation Method for manufacturing wiring substrate having sheet
US20080116561A1 (en) * 2006-11-16 2008-05-22 Chipmos Technologies Inc. Chip carrier film having leads with improved strength and semiconductor package utilizing the film
US20110050657A1 (en) * 2009-08-25 2011-03-03 Seiko Epson Corporation Electro-optical device and electronic apparatus
US20130148312A1 (en) * 2011-12-12 2013-06-13 Sang-uk Han Tape wiring substrate and chip-on-film package including the same
US20140306348A1 (en) * 2013-04-15 2014-10-16 Samsung Display Co., Ltd. Chip on film and display device having the same
US20180102312A1 (en) * 2016-10-06 2018-04-12 Compass Technology Company Limited Fabrication Process and Structure of Fine Pitch Traces for a Solid State Diffusion Bond on Flip Chip Interconnect

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2814966B2 (en) * 1995-09-29 1998-10-27 日本電気株式会社 Semiconductor device
JP3998878B2 (en) * 1999-11-25 2007-10-31 シャープ株式会社 Semiconductor device, semiconductor device manufacturing method, and package manufacturing method
JP5214753B2 (en) 2011-02-23 2013-06-19 シャープ株式会社 Semiconductor device and manufacturing method thereof
TWI567886B (en) 2014-05-28 2017-01-21 南茂科技股份有限公司 Chip package structure and method for manufacutring chip package structure

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030109669A1 (en) * 2000-04-20 2003-06-12 Jiro Sadanobu Polyimide film and process for producing the same
US20050110049A1 (en) * 2003-10-27 2005-05-26 Tatsuhiro Urushido Semiconductor device and its manufacturing method, electronic module, and electronic unit
US20060068164A1 (en) * 2004-09-29 2006-03-30 Mitsui Mining & Smelting Co., Ltd. Film carrier tape for mounting electronic devices thereon and flexible substrate
US20060289939A1 (en) * 2005-06-23 2006-12-28 Samsung Electronics Co., Ltd. Array substrate and display device having the same
US20070007649A1 (en) * 2005-07-07 2007-01-11 Taiwan Semiconductor Manufacturing Company, Ltd. Low cte substrates for use with low-k flip-chip package devices
US20080078491A1 (en) * 2006-09-19 2008-04-03 Seiko Epson Corporation Method for manufacturing wiring substrate having sheet
US20080116561A1 (en) * 2006-11-16 2008-05-22 Chipmos Technologies Inc. Chip carrier film having leads with improved strength and semiconductor package utilizing the film
US20110050657A1 (en) * 2009-08-25 2011-03-03 Seiko Epson Corporation Electro-optical device and electronic apparatus
US20130148312A1 (en) * 2011-12-12 2013-06-13 Sang-uk Han Tape wiring substrate and chip-on-film package including the same
US20140306348A1 (en) * 2013-04-15 2014-10-16 Samsung Display Co., Ltd. Chip on film and display device having the same
US20180102312A1 (en) * 2016-10-06 2018-04-12 Compass Technology Company Limited Fabrication Process and Structure of Fine Pitch Traces for a Solid State Diffusion Bond on Flip Chip Interconnect

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US10777498B2 (en) 2020-09-15
US20190067168A1 (en) 2019-02-28
US20210098345A1 (en) 2021-04-01
CN109427599A (en) 2019-03-05

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