CN109661723A - 具有双面散热结构的半导体封装 - Google Patents

具有双面散热结构的半导体封装 Download PDF

Info

Publication number
CN109661723A
CN109661723A CN201880003374.5A CN201880003374A CN109661723A CN 109661723 A CN109661723 A CN 109661723A CN 201880003374 A CN201880003374 A CN 201880003374A CN 109661723 A CN109661723 A CN 109661723A
Authority
CN
China
Prior art keywords
substrate portion
main body
radiation structure
metal
semiconductor packages
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201880003374.5A
Other languages
English (en)
Other versions
CN109661723B (zh
Inventor
崔伦华
崔淳性
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JMJ Korea Co Ltd
Original Assignee
JMJ Korea Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by JMJ Korea Co Ltd filed Critical JMJ Korea Co Ltd
Publication of CN109661723A publication Critical patent/CN109661723A/zh
Application granted granted Critical
Publication of CN109661723B publication Critical patent/CN109661723B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/3701—Shape
    • H01L2224/37012—Cross-sectional shape
    • H01L2224/37013—Cross-sectional shape being non uniform along the connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/40227—Connecting the strap to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48229—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73263—Layer and strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明提供一种具有双面散热结构的半导体封装，设置金属部，以使将从半导体芯片产生的高温快速地向分别露出至封装上部面、下部面的基板进行热传导。金属部通过超声波焊接及通过粘合剂与基板接合。

Description

具有双面散热结构的半导体封装
技术领域
本发明涉及具有双面散热结构的半导体封装，更具体地涉及一种具有双面散热结构的半导体封装，使得在半导体芯片中产生的高温快速地向分别在封装上、下部面露出的基板进行热传导，而散热效果优秀。
背景技术
一般而言，半导体封装为在基板贴装半导体芯片，在用卡箍或焊线而连接半导体芯片与引线框架的结构的单一模块通过环氧树脂模塑料(EMC：Epoxy molding compound)等热固性材料制模而形成封装主体。
该半导体封装将在贴装于主体内部的半导体芯片中产生的热与另外的散热片(heat slug)结合而排出热，但实情是，对于高集成半导体封装，因发热量大，而无法期望通过散热片而顺畅地排出热。
尤其，在与电动汽车的电池连接的变频器或逆变器内部设置半导体封装，此时，半导体封装的散热功能与电池的效率密切关联。
下面观察提高散热效果的现有技术。
注册专利第10-0648509号(带子式引线框架条带与利用其的引线裸露式半导体芯片封装及制造方法)中公开包括如下结构的技术，包括：半导体芯片，具有结合片；图案引线，通过电线与所述结合片连接；封装主体，封装所述半导体芯片与电线及图案引线，并将所述半导体芯片的下部与所述图案引线的下部露出至外部而形成。
所述现有技术为从半导体芯片产生的热仅向下部排出的结构，由此，散热效果低下，因露出的图案引线为通过电线连接，而构成为不易于释放热的结构。即，所述电线通过焊接附着，并仅传输电信号，并非通过电线而向图案传输热的结构，因而，难以期待高的热释放。
②注册专利第10-1461197号(散热结构的COF型半导体芯片封装)中公开由如下结构构成的技术，其包括：第一散热树脂层，涂覆于半导体芯片与薄膜之间；及第二散热树脂层，涂覆于薄膜上，以与所述半导体芯片的侧面相接的方式涂覆，且以所述半导体芯片的上面露出至外部的方式涂覆。
所述现有技术为半导体芯片被放置于薄膜上，而通过凸点与电极图案相连的结构，是一种在半导体芯片产生的热仅向露出的上部排出，难以向附着有薄膜的下部方向释放热，未存在保护半导体芯片与各个结构的封装主体，因而，难以通过引线框架或电线而进行连接，容易通过震动或冲击而发生损伤的结构。
③注册专利第10-0475313号(利用粘合带的双重芯片半导体封装组装方法)中公开通过如下步骤进行的技术，其步骤包括：第一步骤，在使用于半导体封装组装工艺的框架材料的芯片焊盘(paddle)形成用于粘合芯片的粘合层；第二步骤，在所述粘合层附着第一半导体芯片；及第三步骤，在所述第一半导体芯片上附着供在底面附着用于粘合芯片的粘合带的第二半导体芯片。
所述现有技术为通过液状胶黏剂及粘合带附着第一半导体芯片与第二半导体芯片的技术，因该技术也构成为层叠结构，由此，存在半导体封装的散热效果低下，且在结构上无法有效配置半导体芯片的问题。
发明的内容
发明要解决的技术问题
本发明是为了解决所述问题而研发，其目的为提供一种具有双面散热结构的半导体封装，在封装主体的上部、下部分别将基板的一面露出至外部，通过上部的基板而相互连接在被放置于下部的基板上贴装的半导体芯片的上面与底面，由此，从半导体芯片产生的热向下部的基板排出，并且，也向上部的基板排出，从而，提高散热效果。
用于解决的技术方案
本发明的具有双面散热结构的半导体封装包括：封装主体，通过制模形成；第一基板部，配置于所述封装主体的内侧下部，下部面露出至封装主体的外部；半导体芯片，在所述第一基板部的上面贴装；第二基板部，配置于所述封装主体的内侧上部，上面露出至封装主体的外部；引线框架，附着于所述第一基板部及第二基板部中至少一个，并延伸至封装主体的外部；第一金属部，一侧与所述半导体芯片的上面接合；另一侧与第二基板部的底面接合；第二金属部，一侧与所述第一基板部的上面接合，另一侧与第二基板部的底面接合。
并且，本发明的特征在于，与第二基板部接合的第一金属部与第二金属部的上部通过超声波焊接接合，半导体芯片与接合于第一基板部的第一金属部和第二金属部的下部通过粘合剂接合。
而且，本发明的特征在于，第一金属部的下部通过粘合剂与半导体芯片接合的部分还形成有“V”字或“U”字状的凹槽，并坚固接合而提高散热效果，所述凹槽并非为利用数控刀具或模具而形成凹痕或通过冲压过程而借助另外的工艺形成，伴随所述第一金属部与第二金属部的超声波焊接工艺而形成。
并且，本发明的特征在于，封装主体的制模部的最上面及最下面线具有比第一基板部及第二基板部的露出面的线高或低的阶梯差。
发明的效果
本发明具有如下效果，是一种第一基板部与第二基板部的一面分别在封装主体的上部、下部露出，而容易排出热的结构，通过金属部将贴装于第一基板部的半导体芯片与第二基板部连接，而从半导体芯片产生的热并非仅向第一基板部排出，也随着金属部向上部的第二基板部排出，因而，具有优秀的散热效果。
附图说明
图1为显示具有本发明的双面散热结构的半导体封装的第一实施例的截面图；
图2为显示本发明的具有双面散热结构的半导体封装的第二实施例的截面图；
图3为显示本发明的具有双面散热结构的半导体封装的第三实施例的截面图；
图4为显示本发明的具有双面散热结构的半导体封装的第四实施例的截面图；
图5为概念性显示通过超声波焊接而进行的附着与粘合而产生的附着的附着层的不同点的截面图；
图6为显示根据本发明的实施例，对于在将金属部通过超声波而焊接至基板的情况，在金属部的对侧形成浮雕的接合层的附图；
图7为放大图6的接合层的附图；
图8为显示根据本发明的实施例，具有封装主体的制模部的最上面及最下面的线比第一基板部及第二基板部的露出面的线高(图8a)或低的(图8b)阶梯差的截面图。
具体实施方式
下面，参照附图对本发明的优选的实施例作如下具体说明。
并且，在说明本发明时，对于判断相关的公知功能或结构的具体说明为不必要地且混淆本发明的要旨的情况，省略其具体说明。
本发明的具有双面散热结构的半导体封装包括：封装主体100，通过制模形成；第一基板部200，配置于所述封装主体100的内侧下部，下部面露出至封装主体100的外部；半导体芯片300，在所述第一基板部200的上面贴装；第二基板部500，配置在所述封装主体100的内侧上部，上面露出至封装主体100的外部；引线框架400，附着在所述第一基板部200及第二基板部500中至少一个，并延伸至封装主体100的外部；第一金属部600，一侧与所述半导体芯片300的上面接合，另一侧与第二基板部500的底面接合；第二金属部700，一侧与所述第一基板部200的上面接合，另一侧与第二基板部500的底面接合。
本发明中的基板部200、500为金属材质的单一层芯片及包括将单一层设于之间，而在上部及下部附加绝缘层的三层结构的芯片。
本发明中的引线框架400，附着在第一基板部200及第二基板部500中至少一个，下面，以引线框架400附着于第一基板部200为例进行说明，但并非限定于此，如上所述，能够附着在在第一基板部200及第二基板部500中至少一个。
本发明具有如下结构，为在上部、下部第一基板部200与第二基板部500的一面分别露出至封装主体100外侧的结构，通过露出的面容易排出热，半导体芯片300贴装在第一基板部200的上面，在半导体芯片300产生的热排出至位于下部的第一基板部200，第一金属部600连接半导体芯片300的上面与第二基板部500的底面，在半导体芯片300产生的热直接传输至第二基板部500，由此，将热排出至位于上部的第二基板部500。并且，第二金属部700连接第一基板部200的上面与第二基板部500的底面，而将第一基板部200的热输送至第二基板部500而具有双面排出热的结构。
本发明的第一基板部200与第二基板部500使用由陶瓷(Al2O3)或氮化铝基体(AIN：Aluminum Nitride Substrate)材质等构成，分别在内侧形成金属图案210、510。所述金属图案210、510由金属材质印刷，该金属图案210、510包括贴装数据线、电源供应线与半导体芯片300的垫片。并且，露出至封装主体的第一基板部200与第二基板部500的外侧形成热传导性高的金属层220、520，且一面露出至外部。而且，所述第一基板部200与第二基板部500的结构由此也构成为三层，但根据半导体封装的种类，也适用由一个金属层构成的基板形式。
图1为显示本发明的第一实施例的附图，第一金属部600与第二金属部700分别由垂直的柱状的金属杆形成。由此，对于形成柱状的金属杆的情况，在结构上为稳定的形状，金属杆未在封装主体100内占据大量空间，并能够有效进行热传导。
本发明的第一金属部600与第二金属部700根据接合部位而通过不同的方法接合。即，与第二基板部500接合的第一金属部600与第二金属部700的上部通过超声波焊接接合，与半导体芯片300和第一基板部200接合的第一金属部600与第二金属部700的下部通过粘合剂接合。
所述超声波焊接(ULTRASONIC WELDING)方式为通过另外的超声波焊接接合装置(未图示)而进行接合，在要接合的材料面施加静荷重，并通过超声波震动而发生震动摩擦热而进行压接的方式。由此，根据通过超声波焊接方式接合，具有提高接合品质，防止发生环境污染，并通过自动控制而提高生产力的效果。并且，粘合剂为通过一般使用的导电性焊锡或胶黏剂焊锡的接合方式。
由此，对于第一金属部600与第二金属部700通过超声波焊接而接合于处于上部的第二基板部500，通过焊锡等粘合剂与处于下部的半导体芯片300与第一基板部200接合的情况，具有在作业工艺中提高生产力，并提高半导体封装的完成度的效果。
而且，第一金属部600的下部，即通过粘合剂与半导体芯片300接合的部分还形成“V”字或“U”字形的凹槽，使得更坚固接合，并且，因凹槽而增加表面，更易于提高散热效果。
所述凹槽并非为利用数控刀具或模具而形成凹痕或通过冲压过程而借助另外的工艺形成，优选地，通过第一金属部600与第二金属部700的超声波焊接工艺中的振动而自然形成。此时的作业条件为超声波频率15～45khz，焊接作业0.05～2秒，对于用于超声波焊接的压力，通过气压按压的情况为0.05～0.7Mpa，通过电机驱动按压的情况为1Kgf～150Kgf的范围。
在本发明的实施例中，以第一金属部600为代表，参照图5至图7对超声波焊接工艺的优点作如下具体说明。
图5显示所示，通过超声波焊接与粘合剂而形成的接合在“一体化”或“附着”的方面相同，将第一金属部600通过粘合剂附着于下部基板即第一基板部200的情况的接合层20，与通过超声波焊接而熔接至上部基板即第二基板部500的情况的接合层(50)对比，而变厚最小数倍，对于超声波焊接的情况，显示形成有细微界线的程度的厚度。
在散热面进行观察时，散热的必要性大的部分，尤其在贴装有大量发散热的半导体芯片的下部基板存在厚的粘合层，合理的为将通过粘合剂附着金属部，以帮助散热。但对于金属部附着于与主热源存在距离的金属即上部基板的部分，散热效果也很重要，但在通过严密且稳定的金属之间的组织结合的辅助材料的一体化与通过自动化的超声波焊接工艺的生产效率方面超声波焊接更有利。
而且，发明人如图6显示所示，确认了在将第一金属部600通过超声波焊接至第二基板部500的情况下，通过高频率振动，而在其对面，即，第一金属部600与第一基板部200相对的层形成有圆形或V、U字形的浮雕20a。图6显示，为了方便，去除了第一基板部200。因此，在将金属部的下部通过半导体芯片与粘合剂接合时，向浮雕部分，即“V”字或“U”字形的凹槽填充粘合剂，由此，稳固结合金属部与半导体芯片，通过增加接合层20的厚度与表面积而得到优秀的散热效果。
由图7所示，能够确认到对于在第一金属部600与半导体芯片之间填充粘合剂的情况，粘合剂被熔融于浮雕20a而流入，从而，得到坚固的结合与散热效果的改善。
再次，图2为显示本发明的第二实施例的附图，第一金属部600由弯曲的金属回形针形成，第二金属部700由柱状的金属杆构成，第一金属部与第二金属部形成为相互不同的形状。由此，对于第一金属部600由弯曲的形状的金属回形针构成的情况，与第一实施例相比，具有接触面积高，而快速进行热传导，且散热效果更优秀的特征。
本发明的半导体芯片300被贴装于第一基板部200的金属图案(210)上部。此时，半导体芯片300通过焊锡等粘合剂接合，如图1至2所示，也能够由一个半导体芯片300构成，如图3显示的第三实施例所示，多个半导体芯片300位于第一基板部200，第一金属部600也与半导体芯片300的数量对应，各个半导体芯片300也构成为分别接合第一金属部600的形状。
图4为显示本发明的第四实施例的附图。包括：封装主体100，通过制模形成；第一基板部200，配置于所述封装主体100的内侧下部，下部面露出至封装主体100的外部；下部半导体芯片310，在所述第一基板部200的上面贴装；第二基板部500，配置于所述封装主体100的内侧上部，上面露出至封装主体100的外部；引线框架400，附着于所述第一基板部200及第二基板部500中至少一个，并延伸至封装主体100的外部；所述上部半导体芯片320，在所述第二基板部500的底面贴装；第一金属部600，一侧分别与所述下部半导体芯片310的上面和上部半导体芯片320的底面接合，另一侧分别与处于背面的第一基板部、第二基板部200、500接合；第二金属部700，一侧与所述第一基板部200的上面接合，另一侧与第二基板部500的底面接合。
本发明的第四实施例为下部半导体芯片310与上部半导体芯片320分别贴装于第一基板部200与第二基板部500的形状。作为所述第四实施例的接合结构，第一金属部600通过粘合剂分别与下部半导体芯片310和上部半导体芯片320接合，通过超声波焊接与处于相对面的第一基板部、第二基板部200、500接合，第二金属部700通过粘合剂与第一基板部200接合，通过超声波焊接与第二基板部500接合。该接合结构与第一、二、三实施例存在略微差异，但与半导体芯片接合的第一金属部600通过焊锡等粘合剂接合的技术思想为相同的。
如上所述，本发明的第四实施例的引线框架400也附着于所述第一基板部200及第二基板部500中至少一个，并以引线框架400附着于所述第一基板部200为例进行了记述，但并非限定于此，能够附着于第一基板部200及第二基板部500中至少一个。
再者，本发明的第五实施例如图8显示所示，封装主体100的制模部的线被设计为具有比第一基板部200及第二基板部500的露出面，即比各个金属层220、520高(图8a)或低的(图8d)阶梯差d。优选地，阶梯差d的大小为5～100um。
由此，在赋予阶梯差d的情况下，对于将半导体封装安装于在后续工艺中未显示的被安装辅助材料的情况，对于在位于被安装辅助材料的散热片(heat sink)涂覆热传导效率高的油膏(Greece)或热胶带(thermal tape)的情况，能够均匀地保持该涂覆层的厚度，并由半导体封装快速且有效地释放热。
综上，本发明参照所述实施例而进行了说明，但能够在本发明的技术思想范围内进行各种变形实施。
工业实用性
本发明的具有双面散热结构的半导体封装适用于电子设备，并能够大量生产，由此，具有工业实用性。

Claims (16)

1.一种具有双面散热结构的半导体封装，其特征在于，
包括：
封装主体(100)，通过制模形成；
第一基板部(200)，配置于所述封装主体(100)的内侧下部，且下部面露出至封装主体(100)的外部；
半导体芯片(300)，在所述第一基板部(200)的上面贴装；
第二基板部(500)，配置于所述封装主体(100)的内侧上部，上面露出至封装主体(100)的外部；
引线框架(400)，附着于所述第一基板部(200)及第二基板部(500)中至少一个，并延伸至封装主体(100)的外部；
第一金属部(600)，一侧与所述半导体芯片(300)的上面接合，另一侧与第二基板部(500)的底面接合；
第二金属部(700)，一侧与所述第一基板部(200)的上面接合，另一侧与第二基板部(500)的底面接合。
2.根据权利要求1所述的具有双面散热结构的半导体封装，其特征在于，
与所述第二基板部(500)接合的第一金属部(600)与第二金属部(700)的上部通过超声波焊接接合，与半导体芯片(300)和第一基板部(200)接合的第一金属部(600)和第二金属部(700)的下部通过粘合剂接合。
3.根据权利要求1所述的具有双面散热结构的半导体封装，其特征在于，
所述第一金属部(600)与第二金属部(700)分别由柱状的金属杆形成。
4.根据权利要求1所述的具有双面散热结构的半导体封装，其特征在于，
所述第一金属部(600)由弯曲的金属回形针形成，第二金属部(700)由柱状的金属杆形成。
5.根据权利要求1所述的具有双面散热结构的半导体封装，其特征在于，
所述半导体芯片(300)在第一基板部(200)具有多个，各个半导体芯片(300)分别接合有第一金属部(600)。
6.根据权利要求2所述的具有双面散热结构的半导体封装，其特征在于，
第一金属部(600)的下部通过粘合剂与半导体芯片(300)接合的部分还形成有“V”字或“U”字形状的凹槽，坚固地接合并提高散热效果。
7.根据权利要求6所述的具有双面散热结构的半导体封装，其特征在于，
所述凹槽并非为利用数控刀具或模具而形成凹痕或通过冲压过程而借助另外的工艺形成，伴随所述第一金属部(600)和第二金属部(700)的超声波焊接工艺而形成。
8.根据权利要求7所述的具有双面散热结构的半导体封装，其特征在于，
对于所述超声波焊接工艺，超声波频率为15～45khz、焊接作业为0.05～2秒，对于用于超声波焊接的压力，通过气压按压的情况为0.05～0.7Mpa，通过电机驱动按压的情况为1Kgf～150Kgf的范围。
9.根据权利要求7所述的具有双面散热结构的半导体封装，其特征在于，
所述封装主体(100)的制模部的最上面及最下面线具有比第一基板部(200)及第二基板部(500)的露出面的线高或低的阶梯差。
10.根据权利要求9所述的具有双面散热结构的半导体封装，其特征在于，
所述阶梯差(d)的大小为5～100um。
11.一种具有双面散热结构的半导体封装，其特征在于，
包括：
封装主体(100)，通过制模形成；
第一基板部(200)，配置于所述封装主体(100)的内侧下部，下部面露出至封装主体(100)的外部；
下部半导体芯片(310)，在所述第一基板部(200)的上面贴装；
第二基板部(500)，配置于所述封装主体(100)的内侧上部，且上面露出至封装主体(100)的外部；
引线框架(400)，附着于所述第一基板部(200)及第二基板部(500)中至少一个，并向封装主体的外部延伸；
上部半导体芯片(320)，在所述第二基板部(500)的底面贴装；
第一金属部(600)，一侧分别与所述下部半导体芯片(310)的上面和上部半导体芯片(320)的底面接合，另一侧分别与位于相对面的第一基板部、第二基板部(200)、(500)接合；
第二金属部(700)，一侧与所述第一基板部(200)的上面接合，另一侧与第二基板部(500)的底面接合。
12.根据权利要求11所述的具有双面散热结构的半导体封装，其特征在于，
所述第一金属部(600)通过粘合剂分别与下部半导体芯片(310)和上部半导体芯片(320)接合，并通过超声波焊接与处于相对面的第一基板部、第二基板部(200)、(500)接合，第二金属部(700)通过粘合剂与第一基板部(200)接合，通过超声波焊接与第二基板部(500)接合。
13.根据权利要求12所述的具有双面散热结构的半导体封装，其特征在于，
在所述第一金属部(600)的下部通过粘合剂与下部半导体芯片(310)接合的部分与所述第一金属部(600)的上部通过粘合剂与上部半导体芯片(320)接合的部分还形成“V”字或“U”字形状的凹槽，坚固接合并提高散热效果。
14.根据权利要求13所述的具有双面散热结构的半导体封装，其特征在于，
所述凹槽并非为利用数控刀具或模具而形成凹痕或通过冲压过程而借助另外的工艺形成，伴随所述超声波焊接工艺形成。
15.根据权利要求14所述的具有双面散热结构的半导体封装，其特征在于，
所述超声波焊接工艺为超声波频率15～45khz、焊接作业0.05～2秒，用于超声波焊接的压力通过气压按压的情况为0.05～0.7Mpa，通过电机驱动按压的情况为1Kgf～150Kgf的范围。
16.根据权利要求14所述的具有双面散热结构的半导体封装，其特征在于，
所述封装主体(100)的制模部的最上面及最下面线具有比第一基板部(200)及第二基板部(500)的露出面的线高或低的阶梯差。
CN201880003374.5A 2017-02-22 2018-02-22 具有双面散热结构的半导体封装 Active CN109661723B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR10-2017-0023416 2017-02-22
KR20170023416 2017-02-22
PCT/KR2018/002184 WO2018155927A1 (ko) 2017-02-22 2018-02-22 양면 방열구조를 갖는 반도체 패키지

Publications (2)

Publication Number Publication Date
CN109661723A true CN109661723A (zh) 2019-04-19
CN109661723B CN109661723B (zh) 2023-03-03

Family

ID=63167387

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201880003374.5A Active CN109661723B (zh) 2017-02-22 2018-02-22 具有双面散热结构的半导体封装

Country Status (6)

Country Link
US (1) US10249552B2 (zh)
JP (1) JP6655221B2 (zh)
KR (1) KR101899788B1 (zh)
CN (1) CN109661723B (zh)
DE (1) DE112018000108B4 (zh)
WO (1) WO2018155927A1 (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110335821A (zh) * 2019-06-03 2019-10-15 通富微电子股份有限公司 一种具有双面散热的半导体器件及其封装方法
CN110993511A (zh) * 2019-11-26 2020-04-10 通富微电子股份有限公司技术研发分公司 具有双面散热结构的半导体器件及封装器具、封装方法
CN111403357A (zh) * 2020-03-31 2020-07-10 深圳市依思普林科技有限公司 双面散热功率模块
CN113675168A (zh) * 2020-05-13 2021-11-19 Jmj韩国株式会社 金属柱、包含其的半导体封装及半导体封装制造方法
TWI767543B (zh) * 2020-10-05 2022-06-11 欣興電子股份有限公司 封裝結構
US11631626B2 (en) 2020-10-05 2023-04-18 Unimicron Technology Corp. Package structure
CN117334664A (zh) * 2023-09-28 2024-01-02 海信家电集团股份有限公司 智能功率模块和电子设备

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102552077B1 (ko) * 2018-04-23 2023-07-06 현대자동차주식회사 적층형 파워 모듈 및 이의 제조 방법
US11088046B2 (en) * 2018-06-25 2021-08-10 Semiconductor Components Industries, Llc Semiconductor device package with clip interconnect and dual side cooling
US20200168533A1 (en) * 2018-11-26 2020-05-28 Texas Instruments Incorporated Multi-die package with multiple heat channels
KR102244279B1 (ko) 2019-06-14 2021-04-26 제엠제코(주) 반도체 패키지
KR102264132B1 (ko) 2019-06-14 2021-06-11 제엠제코(주) 반도체 패키지
CN112086413B (zh) 2019-06-14 2024-04-23 Jmj韩国株式会社 半导体封装
KR102355687B1 (ko) 2020-03-19 2022-01-27 제엠제코(주) 반도체 패키지 및 반도체 패키지 제조방법
US11894347B2 (en) * 2019-08-02 2024-02-06 Semiconductor Components Industries, Llc Low stress asymmetric dual side module
US11469163B2 (en) * 2019-08-02 2022-10-11 Semiconductor Components Industries, Llc Low stress asymmetric dual side module
KR102231769B1 (ko) * 2019-08-20 2021-04-01 제엠제코(주) 고열전도를 위한 히트싱크 노출형 반도체 패키지 및 그 제조방법
KR102325114B1 (ko) * 2019-12-06 2021-11-11 제엠제코(주) 반도체 패키지의 제조 방법
DE112020005302T5 (de) * 2020-01-21 2022-11-03 Rohm Co., Ltd. Halbleiterbauteil
KR102371636B1 (ko) * 2020-04-23 2022-03-07 제엠제코(주) 양면 기판 반도체 제조 방법
CN112259513B (zh) * 2020-10-22 2023-09-26 湖南国芯半导体科技有限公司 一种双面散热功率模块及其封装方法
US11908766B2 (en) 2021-04-05 2024-02-20 Jmj Korea Co., Ltd. Cooling system where semiconductor component comprising semiconductor chip and cooling apparatus are joined
KR102405276B1 (ko) 2022-01-26 2022-06-07 제엠제코(주) 반도체 패키지 및 이의 제조방법
KR102603439B1 (ko) 2022-03-07 2023-11-20 제엠제코(주) 음각기판을 구비한 반도체 패키지 및 이의 제조방법
KR102536643B1 (ko) 2022-11-28 2023-05-30 제엠제코(주) 반도체 패키지

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004221516A (ja) * 2002-11-22 2004-08-05 Toyota Industries Corp 半導体モジュールおよび半導体モジュール用リード
JP2008227131A (ja) * 2007-03-13 2008-09-25 Renesas Technology Corp 半導体装置及びその製造方法
JP2009170802A (ja) * 2008-01-18 2009-07-30 Oki Semiconductor Co Ltd 半導体装置
JP2013157361A (ja) * 2012-01-26 2013-08-15 Mitsubishi Materials Corp ヒートシンク付パワーモジュール用基板の製造方法
JP2014060410A (ja) * 2008-04-09 2014-04-03 Fuji Electric Co Ltd 半導体装置
JP2014127538A (ja) * 2012-12-26 2014-07-07 Meidensha Corp 半導体モジュール
KR20150129269A (ko) * 2014-05-09 2015-11-19 제엠제코(주) 반도체 패키지를 위한 클립 구조체 및 이를 이용한 반도체 패키지, 제조 방법

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2334814A (en) * 1998-02-25 1999-09-01 Motorola Inc Moulded electronic device package with a heat sink
KR100648509B1 (ko) 2000-12-06 2006-11-24 삼성전자주식회사 테이프형 리드 프레임 스트립과 이를 이용한 리드 노출형반도체 칩 패키지 및 제조 방법
KR100475313B1 (ko) 2002-07-04 2005-03-10 에스티에스반도체통신 주식회사 접착테이프를 이용한 이중칩 반도체 패키지 조립방법
US7999369B2 (en) * 2006-08-29 2011-08-16 Denso Corporation Power electronic package having two substrates with multiple semiconductor chips and electronic components
DE102007034491A1 (de) * 2007-07-24 2009-02-05 Siemens Ag Modul mit elektronischem Bauelement zwischen zwei Substraten, insbesondere DCB-Keramiksubstraten, dessen Herstellung und Kontaktierung
TW201011869A (en) * 2008-09-10 2010-03-16 Cyntec Co Ltd Chip package structure
JP2011114176A (ja) * 2009-11-27 2011-06-09 Mitsubishi Electric Corp パワー半導体装置
KR20120031697A (ko) * 2010-09-27 2012-04-04 삼성전자주식회사 패키지 적층 구조 및 그 제조 방법
JP5947537B2 (ja) * 2011-04-19 2016-07-06 トヨタ自動車株式会社 半導体装置及びその製造方法
JP5869285B2 (ja) * 2011-10-07 2016-02-24 トヨタ自動車株式会社 半導体装置
JP6033011B2 (ja) * 2012-09-12 2016-11-30 三菱電機株式会社 電力用半導体装置および電力用半導体装置の製造方法
JP5840102B2 (ja) * 2012-10-11 2016-01-06 三菱電機株式会社 電力用半導体装置
US9275926B2 (en) * 2013-05-03 2016-03-01 Infineon Technologies Ag Power module with cooling structure on bonding substrate for cooling an attached semiconductor chip
KR101461197B1 (ko) 2013-08-01 2014-11-21 주식회사 루셈 방열 구조의 cof 형 반도체칩 패키지
US9555962B1 (en) * 2013-09-23 2017-01-31 David M Stravitz Waste containers with bag trapping structure
US10971476B2 (en) * 2014-02-18 2021-04-06 Qualcomm Incorporated Bottom package with metal post interconnections
KR101755769B1 (ko) * 2014-10-29 2017-07-07 현대자동차주식회사 양면 냉각 파워 모듈 및 이의 제조 방법

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004221516A (ja) * 2002-11-22 2004-08-05 Toyota Industries Corp 半導体モジュールおよび半導体モジュール用リード
JP2008227131A (ja) * 2007-03-13 2008-09-25 Renesas Technology Corp 半導体装置及びその製造方法
JP2009170802A (ja) * 2008-01-18 2009-07-30 Oki Semiconductor Co Ltd 半導体装置
JP2014060410A (ja) * 2008-04-09 2014-04-03 Fuji Electric Co Ltd 半導体装置
JP2013157361A (ja) * 2012-01-26 2013-08-15 Mitsubishi Materials Corp ヒートシンク付パワーモジュール用基板の製造方法
JP2014127538A (ja) * 2012-12-26 2014-07-07 Meidensha Corp 半導体モジュール
KR20150129269A (ko) * 2014-05-09 2015-11-19 제엠제코(주) 반도체 패키지를 위한 클립 구조체 및 이를 이용한 반도체 패키지, 제조 방법

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110335821A (zh) * 2019-06-03 2019-10-15 通富微电子股份有限公司 一种具有双面散热的半导体器件及其封装方法
CN110335821B (zh) * 2019-06-03 2021-07-09 通富微电子股份有限公司 一种具有双面散热的半导体器件及其封装方法
CN110993511A (zh) * 2019-11-26 2020-04-10 通富微电子股份有限公司技术研发分公司 具有双面散热结构的半导体器件及封装器具、封装方法
CN111403357A (zh) * 2020-03-31 2020-07-10 深圳市依思普林科技有限公司 双面散热功率模块
CN113675168A (zh) * 2020-05-13 2021-11-19 Jmj韩国株式会社 金属柱、包含其的半导体封装及半导体封装制造方法
CN113675168B (zh) * 2020-05-13 2024-06-07 Jmj韩国株式会社 金属柱、包含其的半导体封装及半导体封装制造方法
TWI767543B (zh) * 2020-10-05 2022-06-11 欣興電子股份有限公司 封裝結構
US11631626B2 (en) 2020-10-05 2023-04-18 Unimicron Technology Corp. Package structure
CN117334664A (zh) * 2023-09-28 2024-01-02 海信家电集团股份有限公司 智能功率模块和电子设备

Also Published As

Publication number Publication date
US10249552B2 (en) 2019-04-02
DE112018000108T5 (de) 2019-05-29
JP2020503697A (ja) 2020-01-30
US20180240731A1 (en) 2018-08-23
WO2018155927A1 (ko) 2018-08-30
DE112018000108B4 (de) 2020-10-22
JP6655221B2 (ja) 2020-02-26
KR101899788B1 (ko) 2018-11-05
CN109661723B (zh) 2023-03-03

Similar Documents

Publication Publication Date Title
CN109661723A (zh) 具有双面散热结构的半导体封装
JP3392590B2 (ja) チップ・キャリア・モジュール及びその生成方法
CN105990265B (zh) 功率转换电路的封装模块及其制造方法
US7947999B2 (en) Luminescent device and method for manufacturing the same
US5686758A (en) Semiconductor device having integral structure of case and external connection terminals
US8421088B2 (en) Surface mounting type light emitting diode
US20050116335A1 (en) Semiconductor package with heat spreader
KR102172689B1 (ko) 반도체 패키지 및 그 제조방법
CN218730911U (zh) 一种内绝缘的双面散热封装结构
EP4280270A1 (en) Power semiconductor module and manufacturing method therefor
CN104051397A (zh) 包括非整数引线间距的封装器件及其制造方法
KR101363392B1 (ko) 고출력 증폭기용 GaN 반도체 패키지 및 그 제조방법
CN108493163A (zh) 一种基于片条式刚性框架的芯片封装结构及其工艺
CN117293101A (zh) 一种功率模组及其制作方法、功率设备
CN112201632A (zh) 一种半导体器件封装结构及半导体器件封装方法
US20220208661A1 (en) Qfn/qfp package with insulated top-side thermal pad
CN203085515U (zh) 半导体封装体
CN211238244U (zh) 板上芯片型光电器件
CN107154359A (zh) 半导体封装结构及其制造方法
US20200357753A1 (en) Method of manufacturing semiconductor device
CN221327698U (zh) 一种厚膜塑封芯片封装结构
CN204834605U (zh) 带有热管系统的功率模块
CN204632803U (zh) 一种csp led及基板
CN220796734U (zh) 一种半桥功率模块封装结构
CN113725099B (zh) 半导体封装方法及半导体封装结构

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant