CN112086413B - 半导体封装 - Google Patents

半导体封装 Download PDF

Info

Publication number
CN112086413B
CN112086413B CN202010381690.5A CN202010381690A CN112086413B CN 112086413 B CN112086413 B CN 112086413B CN 202010381690 A CN202010381690 A CN 202010381690A CN 112086413 B CN112086413 B CN 112086413B
Authority
CN
China
Prior art keywords
substrate
module
main module
pattern
semiconductor package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010381690.5A
Other languages
English (en)
Other versions
CN112086413A (zh
Inventor
崔伦华
赵廷焄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jmj Korea Co ltd
Original Assignee
Jmj Korea Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020190070583A external-priority patent/KR102244279B1/ko
Priority claimed from KR1020200033834A external-priority patent/KR102355687B1/ko
Application filed by Jmj Korea Co ltd filed Critical Jmj Korea Co ltd
Publication of CN112086413A publication Critical patent/CN112086413A/zh
Application granted granted Critical
Publication of CN112086413B publication Critical patent/CN112086413B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29347—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/3701—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/3701—Shape
    • H01L2224/37012—Cross-sectional shape
    • H01L2224/37013—Cross-sectional shape being non uniform along the connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40101—Connecting bonding areas at the same height, e.g. horizontal bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/404—Connecting portions
    • H01L2224/4046—Connecting portions with multiple bonds on the same bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/115—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

本发明提供一种半导体封装，通过如下步骤模块化制造：准备安置半导体芯片的主模块、绝缘剂、一个以上的子模块的步骤；准备所述半导体芯片的步骤；准备用于粘接所述半导体芯片的粘接剂的步骤；将所述半导体芯片附着在所述主模块的上面或上下面的步骤；进行所述半导体芯片的电性连接的步骤；准备形成有可电性连接的图案的基板的步骤；及将所述主模块的一侧面垂直地附着在所述基板的图案而电性连接的步骤，由此，通过半导体芯片(111)的垂直排列结构提高在基板(140)上的聚集率，并且，扩大散热面积而提高散热效果。

Description

半导体封装
技术领域
本发明涉及半导体封装，更详细地，涉及一种通过半导体芯片的垂直排列结构提高在基板上的聚集率，并且，扩大散热面积而提高散热效果的半导体封装。
并且，本发明涉及一种借助于在基板上的主模块的半导体芯片的垂直附着结构而提高半导体芯片的聚集率的半导体封装。
背景技术
一般而言，如图1的a所示，半导体封装是在半导体封装主体60内侧的基板10上安装半导体芯片20，并通过金属夹片31或导电配线32将半导体芯片20与基板10相互连接而形成。
或者，如图1的b所示，半导体封装是在半导体封装主体内侧的顺次地层积图案金属层B和绝缘层C和图案金属层D的采用直接绑定铜Direct Bonded Copper结构的下部基板10B上安装半导体芯片20，并通过导电配线32将半导体芯片20和下部基板10B的图案金属层D相互连接，并且，通过金属桩40与顺次地层积有图案金属层B和绝缘层C和图案金属层D的DBC结构的上部基板10A粘合，而相互连接形成。
并且，半导体芯片20在基板10,10A,10B上由水平方向安装，从而，金属夹片31或导电配线32的水平结构使得散热不顺畅，因此，为了降低半导体芯片20的发热，需要附加另外的散热板(heat slug)散热。
因此，需要一种从根本上改善半导体芯片的水平安装结构，而将半导体封装的大小最小化，并且，无需附加另外的散热结构，也能够有效地降低半导体芯片的发热而提高收益率的封装技术。
【先行技术文献】
【专利文献】
韩国注册专利公报第1920915号(具有散热结构的半导体封装,2018.11.21)
韩国注册专利公报第1899788号(具有两面散热结构的半导体封装及其制造方法,2018.11.05)
韩国注册专利公报第1694657号(具有散热结构的半导体封装,2017.01.09)
发明内容
发明要解决的技术问题
本发明的思想要解决的技术问题是提供一种通过半导体芯片的垂直排列结构提高在基板上的聚集率，并且，扩大散热面积而提高散热效果的半导体封装。
并且，提供一种形成有贯通模块的冷却管，通过半导体芯片的垂直排列结构提高基板上的聚集率，并且，扩大散热面积而提高散热效果，并且，循环冷却剂而降低半导体的发热的半导体封装。
并且，在上下部基板之间垂直地排列半导体芯片，而更加扩大散热面积，更加提高冷却效率的半导体封装。
并且，将在主模块上附着的半导体芯片与外部端子直接地电性连接而形成小型结构的半导体封装。
解决问题的技术方案
为了实现上述目的，本发明的半导体封装，通过如下步骤模块化制造：准备安置半导体芯片的主模块、绝缘剂、一个以上的子模块的步骤；准备所述半导体芯片的步骤；准备用于粘接所述半导体芯片的粘接剂的步骤；将所述半导体芯片附着在所述主模块的上面或上下面的步骤；进行所述半导体芯片的电性连接的步骤；准备形成有可电性连接的图案的基板的步骤；及将所述主模块的一侧面垂直地附着在所述基板的图案而电性连接的步骤。
在此，所述主模块和所述子模块包括导电金属。
并且，所述粘接剂含有焊料系列或含有Ag或Cu烧结材料。
并且，在所述主模块的上面或上下面附着安装至少一个以上的所述半导体芯片。
并且，所述半导体芯片为多个，通过金属夹片相互电性连接，或所述半导体芯片与所述子模块通过导电配线相互电性连接。
并且，所述基板由绝缘物质和在所述绝缘物质上形成的金属图案构成。
并且，通过超音波焊接、焊接或烧结方式，将所述主模块的一侧面垂直地附着在所述基板的图案而电性连接。
并且，所述半导体芯片由功率二极管和功率DVC构成，所述功率二极管与所述功率DVC通过金属夹片电性连接，所述功率DVC与所述子模块通过导电配线或导电金属电性连接而构成单位的功率模块，将由第1功率模块、第2功率模块、隔片模块构成的组模块垂直地附着在所述基板的图案而相互电性连接。
并且，所述组模块的子模块与所述基板通过导电配线或导电金属电性连接。
并且，还包括在半导体封装主体上形成所述组模块和所述基板的步骤，形成连接于在所述基板上连接的所述导电配线的接线销,所述接线销在所述基板上垂直地形成，或在所述半导体封装主体插入形成而通过导电配线或导电金属与所述基板电性连接。
并且，在所述主模块的另一侧面还包括相互电性连接的另一个基板。
并且，所述基板及所述另一个基板由一个以上的金属层、绝缘层、一个以上的金属层顺次地层积而形成，或由一个以上的金属层和绝缘层顺次地层积而形成。
并且，所述基板及所述另一个基板由单一的金属层形成，所述金属层的厚度为0.1mm至10mm。
并且，还包括冷却管：其从所述半导体封装主体外部向所述主模块的孔延伸形成，以使冷却剂循环。
并且，还包括冷却管：其从所述半导体封装主体外部向所述隔片模块的孔延伸形成，以使冷却剂循环。
并且，根据本发明的又另一实施例的半导体封装，包括：主模块；附着在所述主模块的一面的一个以上的半导体芯片；形成有可电性连接的图案的第1图案基板；及包裹所述主模块和所述半导体芯片的封装主体，并且，将所述主模块的另一面垂直地附着在所述第1图案基板而电性连接。
并且，所述一个以上的半导体芯片附着在所述主模块的上面，将所述主模块的下面或侧面垂直地附着在所述第1图案基板而电性连接。
并且，所述半导体芯片与所述第1图案基板通过电性连接部件直接地连接，或介入形成导电介质而电性连接。
并且，还包括形成有可电性连接的图案的第2图案基板，所述一个以上的半导体芯片附着在所述主模块的上面，所述主模块的上端侧面及下端侧面分别垂直地附着在所述第1图案基板与所述第2图案基板之间，而电性连接。
并且，所述主模块由在所述第1图案基板附着下端侧面的第1主模块和在所述第2图案基板附着上端侧面的第2主模块构成，所述第1主模块和所述第2主模块具有不同的垂直高度，在所述第1图案基板与所述第2图案基板之间介入形成隔片而将所述第1主模块和所述第2主模块连续地排列。
发明效果
本发明具有如下效果：通过半导体芯片的垂直排列结构提高在基板上的聚集率，并且，扩大散热面积而提高散热效果。
并且，具有如下效果：形成有贯通模块的冷却管，通过半导体芯片的垂直排列结构提高基板上的聚集率，并且，扩大散热面积而提高散热效果，并且，循环冷却剂而降低半导体的发热。
并且，具有如下效果：在上下部基板之间垂直地排列半导体芯片，而更加扩大散热面积，更加提高冷却效率。
并且，具有如下效果：借助于通过基板上的主模块的半导体芯片的垂直附着结构而提高半导体芯片的聚集率,并且，扩大散热面积而提高半导体芯片的散热效果。
并且，具有如下效果：将在主模块上附着的半导体芯片与外部端子直接地电性连接而形成小型结构。
附图说明
图1示例根据以往技术的电线连接模块封装；
图2表示根据本发明的一实施例的半导体封装的立体图；
图3示例图2的半导体封装的内部结构；
图4示例图2的半导体封装的截面结构；
图5分离表示图2的半导体封装的组模块；
图6及图7分别截断表示图2的半导体封装的内部结构；
图8表示根据本发明的又另一实施例的半导体封装的立体图；
图9示例图8的半导体封装的内部结构；
图10至图12分别截断表示图8的半导体封装的内部结构；
图13表示图8的半导体封装的组模块的侧面结构；
图14表示图8的半导体封装的接线销；
图15及图16表示根据本发明的又另一实施例的半导体封装的截面结构；
图17表示根据本发明的又另一实施例的半导体封装的立体图；
图18表示图17的半导体封装的截面结构；
图19至图21分别表示图17的半导体封装的分解立体图；
图22分离表示图17的半导体封装的半导体芯片的附着构成；
图23及图24分别表示图17的半导体封装的配线结构。
附图标记说明
10：基板 10A：上部基板
10B：下部基板 20：半导体芯片
31：金属夹片 32：导电配线
40：金属桩 60：半导体封装主体
110：主模块 111：半导体芯片
112：金属夹片 113：导电配线
114：孔 120：绝缘剂
130：子模块 140：基板
140A：上部基板 140B：下部基板
141,141a,141b：图案 142,143：导电配线
144：接线销 150：隔片模块
160：半导体封装主体 170：基板
180：冷却管
510：主模块 511：第1主模块
512：第2主模块 513：隔片
520：半导体芯片 521：导电性粘接剂
522：金属夹片 523：导电配线
524：接线销 530：第1图案基板
531：第1图案 532：第2图案
533：第3图案 534：接线销
535：接线销 540：封装主体
541：底座基板 542：第1夹片端子
543：第2夹片端子 550：第2图案基板
具体实施方式
以下，参照附图详细说明本发明的实施例，以便本发明的技术领域的普通技术人员地实施。本发明可以各种不同的形态实施，并非限定于在此说明的实施例。
参照图2至图7，根据本发明的一实施例的半导体封装，整体上通过如下步骤模块化制造：准备安置半导体芯片111的主模块(main block)110和绝缘剂120和子模块(subblock)130的步骤；准备半导体芯片111的步骤；准备用于粘接半导体芯片111的粘接剂(未图示)的步骤；将半导体芯片111附着在主模块110的上面或上下面的步骤；进行半导体芯片111的电性连接的步骤；准备形成有可电性连接的图案141的基板140的步骤；将主模块110的一侧面垂直地附着在基板140的图案141而电性连接的步骤，其要点为通过半导体芯片111的垂直排列结构提高在基板140上的聚集率，并扩大散热面积而提高散热效果。
如图5的a所示，主模块110和子模块130包括导电金属，在主模块110与子模块130之间介入绝缘粘接剂或绝缘环氧的绝缘剂120，而将主模块110和子模块130相互绝缘的同时相互附着结合。
如图4、图5的a及图13所示，将半导体芯片111通过含有焊料系列或含有Ag或Cu烧结材料的粘接剂粘接附着在主模块110的上面或上下面。
在此，参照图13，在主模块110的上面或上下面附着至少一个以上的功率半导体芯片111，而根据需要调整半导体芯片111的聚集率。
并且，半导体芯片111通过金属夹片112相互电性连接，或根据需要，半导体芯片111与一个以上的第1子模块或第2子模块的子模块130通过栅极信号线即导电配线113或导电金属(未图示)相互电性连接。
例如，半导体芯片111由功率二极管(power diode)111a和功率DVC(绝缘栅双极型晶体管(IGBT)或场效应晶体管(MOSFET)或氮化镓(GaN))111b构成，功率二极管111a与功率DVC111b通过金属夹片112电性连接，并且，功率DVC111b与子模块130通过导电配线113或导电金属(未图示)电性连接而构成单位的功率模块，并且，将由第1功率模块和第2功率模块和隔片模块150构成的组模块A以侧面竖立，垂直地附着在基板140的图案141而相互电性连接。
在此，可通过超音波焊接、焊接或烧结(sintering)方式将主模块110的一侧面垂直地附着在基板140的图案141而电性连接。
并且，如图3、图4及图6所示，基板140由绝缘物质和在绝缘物质上形成的金属图案141形成，并且，可在导热性优秀并具有绝缘性的基板形成电路图案或在基板上附着形成有电路图案的绝缘基板而形成。
并且，如图3及图6所示，将组模块的子模块130和基板140通过栅极信号线即导电配线(142)或导电金属(未图示)电性连接，而将子模块130与基板140的线路相互连接。
并且，还包括在半导体封装主体160形成组模块A和基板140的步骤，并且，形成有连接于在基板140上连接的导电配线143的接线销144，作为参考，如图14所示，接线销144可在基板140上垂直地形成，或如图2及图3所示，在半导体封装主体160插入形成，而通过导电配线(143)或导电金属(未图示)与基板140电性连接。
并且，如图4、图6及图7所示，在组模块A的主模块110的另一侧面还可包括相互电性连接的另一个基板170。
或者,参照图5和图8至图12，根据本发明的又另一实施例的半导体封装，整体上通过如下步骤以模块化制造：准备安置半导体芯片111并形成有使冷却剂循环的孔114的主模块110和绝缘剂120和子模块130的步骤；准备半导体芯片111的步骤；准备用于粘接半导体芯片111的粘接剂的步骤；将半导体芯片111附着在主模块110的上面或上下面的步骤；进行半导体芯片111的电性连接的步骤；准备具有可电性连接的图案141的基板140的步骤；及将主模块110的一侧面垂直地附着在基板140的图案141而电性连接的步骤，由此，其要旨是通过半导体芯片111的垂直排列结构提高在基板140上的聚集率，并扩大散热面积而提高散热效果，并且，循环冷却剂以降低半导体的发热。
如图5的a所示，主模块110和子模块130包括导电金属，在主模块110与子模块130之间介入形成绝缘粘接剂或绝缘环氧基的绝缘剂120，而将主模块110与子模块130相互绝缘的同时相互附着结合。
如图5的a、图12及图13所示，可将半导体芯片111通过含有焊料系列或包括Ag或Cu烧结材料的粘接剂粘接附着在主模块110的上面或上下面。
在此，参照图13，可在主模块110的上面或上下面附着至少一个以上的功率半导体芯片111，并根据需要调整半导体芯片111的聚集率。
并且，半导体芯片111可通过金属夹片112相互电性连接，或根据需要半导体芯片111与一个以上的第1子模块或第2子模块的子模块130通过栅极信号线即导电配线113或导电金属(未图示)而相互电性连接。
例如，半导体芯片111由功率二极管111a和功率DVC(IGBT或MOSFET或GaN)111b构成，功率二极管111a和功率DVC111b通过金属夹片112电性连接，功率DVC111b与子模块130通过导电配线113或导电金属(未图示)电性连接而构成单位的功率模块，并且，将由第1功率模块和第2功率模块和隔片模块150构成的组模块A以侧面竖立，垂直地附着在基板140的图案141而相互电性连接。
在此，可通过超音波焊接、焊接或烧结(sintering)方式将主模块110的一侧面垂直地附着在基板140的图案141而电性连接。
并且，如图9及图11所示，基板140由绝缘物质和在绝缘物质上形成的金属图案141构成，并且，在导热性优秀并具有绝缘性的基板上形成电路图案，或在基板上附着形成有电路图案的绝缘基板而形成。
并且，如图9及图10所示，将组模块的子模块130和基板140通过栅极信号线即导电配线(142)或导电金属(未图示)电性连接而将子模块130与基板140的线路相互连接。
并且，还包括在半导体封装主体160上形成组模块A和基板140的步骤，形成有连接于在基板140上连接的导电配线143的接线销144,作为参考，如图14所示，接线销144在基板140上垂直地形成，或如图2及图3所示，在半导体封装主体160插入形成而通过导电配线(143)或导电金属(未图示)与基板140电性连接。
并且，如图10及图12所示，在组模块A的主模块110的另一侧面还可包括相互电性连接的另一个基板170。
并且，冷却剂从半导体封装主体160的外部引入(inlet)，通过向主模块110的孔114延伸形成的冷却管180向外部引出(outlet)而循环。
在此，冷却剂可使用空气、氢气、冷却水。
或者,如图10及图11所示，冷却剂通过从半导体封装主体160外部向隔片模块150的孔114延伸形成的冷却管180循环。
并且，图15及图16表示根据本发明的又另一实施例的半导体封装的截面结构。以下，以图15及图16为中心详细说明本发明的又另一实施例，但，对于与根据图2至图7的一实施例的构成相同的构成参照图2至图7。
参照图15及图16，根据本发明的又另一实施例的半导体封装，整体上通过如下步骤模块化制造：准备用于安置半导体芯片111的主模块110和绝缘剂120和子模块130的步骤；准备半导体芯片111的步骤；准备用于粘接半导体芯片111的粘接剂(未图示)的步骤；将半导体芯片111附着在主模块110的上面或上下面的步骤；进行半导体芯片111的电性连接的步骤；分别准备形成有可电性连接的图案141a,b的上部基板140A和下部基板140B的步骤；将主模块110的一侧面分别在上部基板140A的图案141a和下部基板140B的图案141b垂直地附着，而电性连接的步骤，由此，其要旨为通过半导体芯片111的垂直排列结构提高在上下部基板140A,B上的聚集率，并扩大散热面积而提高散热效果，并且，通过上下部基板更加扩大散热面积。
并且，如图15所示，上部基板140A和下部基板140B由一个以上的金属层B、绝缘层C、一个以上的金属层D顺次地层积而形成，或由一个以上的金属层B、绝缘层C顺次地层积而形成。在此，绝缘层C可由Al2O3(陶瓷)、氮化铝(Aluminium Nitride)或氮化硅(Si3N4)的绝缘材质形成。
或者，如图16所示，上部基板140A和下部基板140B由单一的金属层形成，金属层的厚度可为0.1㎜至10㎜。
如图5的a所示，主模块110和子模块130包括导电金属，在主模块110与子模块130之间介入形成绝缘粘接剂或绝缘环氧基的绝缘剂120，而将主模块110与子模块130相互绝缘的同时相互附着结合。
如图4、图5的a及图13所示，将半导体芯片111通过包含焊料系列或包含Ag或Cu烧结材料的粘接剂粘接附着在主模块110的上面或上下面。
在此，参照图13，可在主模块110的上面或上下面附着至少一个以上的功率半导体芯片111，而根据需要调整半导体芯片111的聚集率。
并且，半导体芯片111可通过金属夹片112相互电性连接，或根据需要，半导体芯片111与一个以上的第1子模块或第2子模块的子模块130通过栅极信号线即导电配线113或导电金属(未图示)相互电性连接。
例如，半导体芯片111由功率二极管(power diode)(111a)和功率DVC(IGBT或MOSFET或GaN)111b构成，功率二极管111a与功率DVC111b通过金属夹片112电性连接，功率DVC111b与子模块130通过导电配线113或导电金属(未图示)电性连接而构成单位的功率模块，并且，将由第1功率模块和第2功率模块和隔片模块150构成的组模块A以侧面竖立垂直地附着在上下部基板140A,B的图案141a,b之间，而相互电性连接。
在此，通过超音波焊接、焊接或烧结方式，将主模块110的两侧面垂直地附着在上下部基板140A,B的图案141a,b而电性连接。
并且，如图3、图4及图6所示，基板140由绝缘物质和在绝缘物质上形成的金属图案141构成，可在导热性优秀并具有绝缘性的基板上形成电路图案，或在基板上附着形成有电路图案的绝缘基板而形成。
并且，如图3及图6所示，将组模块的子模块130与基板140通过栅极信号线即导电配线(142)或导电金属(未图示)电性连接，而将子模块130与基板140的线路相互连接。
并且，还包括在半导体封装主体160形成组模块A和基板140的步骤，形成有连接于在基板140上连接的导电配线143的接线销144,作为参照，如图14所示，接线销144基板可在140上垂直地形成，或如图2及图3所示，在半导体封装主体160插入形成而与基板140通过导电配线(143)或导电金属(未图示)电性连接。
或者，虽未图示，如下详细说明根据本发明的又另一实施例的半导体封装。以下，对于与本发明的又另一实施例的构成相同的构成参照图8至图12及图15和图16。
本发明的又另一实施例的半导体封装，整体上通过如下步骤模块化制造：安置半导体芯片111并形成有循环冷却剂的孔114的主模块110、绝缘剂120、子模块130的步骤；准备半导体芯片111的步骤；准备用于粘接半导体芯片111的粘接剂的步骤；将半导体芯片111附着在主模块110的上面或上下面的步骤；进行半导体芯片111的电性连接的步骤；分别准备形成有可电性连接的图案141a,b的上部基板140A和下部基板140B的步骤；将主模块110的一侧面分别垂直地附着在上部基板140A的图案141a和下部基板140B的图案141b而电性连接的步骤，由此，其要旨是通过半导体芯片111的垂直排列结构提高在上下部基板140A,B上的聚集率，并扩大散热面积而提高散热效果，并且，通过上下部基板140A,B更加扩大散热面积，并且，循环冷却剂以降低半导体的发热。
并且，如图15所示，上部基板140A和下部基板140B由一个以上的金属层B、绝缘层C、一个以上的金属层D顺次地层积形成，或由一个以上的金属层B、绝缘层C顺次地层积形成。在此，绝缘层C可由Al2O3(陶瓷)、AlN或Si3N4的绝缘材质形成。
或者，如图16所示，上部基板140A和下部基板140B由单一的金属层，金属层的厚度为0.1㎜至10㎜。
如图5的a所示，主模块110和子模块130包括导电金属，在主模块110与子模块130之间介入形成绝缘粘接剂或绝缘环氧基的绝缘剂120，而将主模块110与子模块130相互绝缘的同时相互附着结合。
如图5的a、图12及图13所示，将半导体芯片111通过包括焊料系列或包括Ag或Cu烧结材料的粘接剂粘接附着在主模块110的上面或上下面。
在此，参照图13，在主模块110的上面或上下面附着至少一个以上的功率半导体芯片111，而根据需要调整半导体芯片111的聚集率。
并且，半导体芯片111可通过金属夹片112相互电性连接，或根据需要，半导体芯片111与一个以上的第1子模块或第2子模块的子模块130通过栅极信号线即导电配线113或导电金属(未图示)而相互电性连接。
例如，半导体芯片111由功率二极管111a和功率DVC(IGBT或MOSFET或GaN)111b构成，功率二极管111a与功率DVC111b通过金属夹片112电性连接，功率DVC111b与子模块130通过导电配线113或导电金属(未图示)电性连接而构成单位的功率模块，并且，将由第1功率模块、第2功率模块、隔片模块150构成的组模块A以侧面竖立而在上下部基板140A,B的图案141a,b之间垂直地附着，相互电性连接。
在此，可通过超音波焊接、焊接或烧结方式将主模块110的两侧面垂直地附着在上下部基板140A,B的图案141a,b而电性连接。
并且，如图9及图11所示，基板140由绝缘物质和在绝缘物质上形成的金属图案141构成，并且，在热导性优秀、具有绝缘性的基板上形成电路图案，或在基板上附着形成有电路图案的绝缘基板而形成。
并且，如图9及图10所示，将组模块的子模块130与基板140通过栅极信号线即导电配线(142)或导电金属(未图示)电性连接，而将子模块130与基板140的线路相互连接。
并且，还包括在半导体封装主体160形成组模块A和基板140的步骤，形成有连接于在基板140上连接的导电配线143的接线销144,作为参照，如图14所示，接线销144在基板140上垂直地形成，或如图2及图3所示，在半导体封装主体160插入形成，而与基板140通过导电配线(143)或导电金属(未图示)电性连接。
并且，冷却剂通过从半导体封装主体160外部引入(inlet)并向主模块110的孔114延伸形成的冷却管180向外部引出(outlet)而循环。
在此，作为冷却剂可使用空气、氮气或冷却水。
或者，如图10及图11所示，冷却剂通过从半导体封装主体160外部向隔片模块150的孔114延伸形成的冷却管180而循环。
并且，在根据本发明的又另一实施例的半导体封装的上下部基板140A,B将功率模块和组模块与引脚框架一起粘接后，通过环氧塑封料(EMC；Epoxy Molding Compound)包裹而最终制造模块。
由此，通过如上述的半导体封装的构成，借助于半导体芯片的垂直排列结构提高在基板上的聚集率，并且，扩大散热面积而提高散热效果，并且，形成有贯通模块的冷却管，而借助于半导体芯片的垂直排列结构提高在基板上的聚集率，扩大散热面积而提高散热效果，并循环冷却剂而降低半导体的发热，并且，在上下部基板之间垂直地排列半导体芯片，而更加扩大散热面积，更加提高冷却效率。
并且，根据本发明的又另一实施例的半导体封装包括：主模块510；附着在主模块510的一面的一个以上的半导体芯片520；形成有可电性连接的图案的第1图案基板530；包裹主模块510和半导体芯片520的封装主体540，并且，将主模块510的另一面垂直地附着在第1图案基板530而电性连接，从而，其要旨为通过半导体芯片的垂直附着结构提高聚集率，并且，扩大散热面积而提高散热效果，并直接地电性连接半导体芯片与外部端子而形成小型化。
参照图17至图24，如下详细说明上面说明的本发明的又另一实施例的半导体封装。
首先，如图21所示，主模块(main block)510提供附着半导体芯片520的安装控件，并且，在形成于第1图案基板530的图案531,532上通过超音波焊接、焊接或烧结方式附着而电性连接。
在此，主模块由导电性材料形成，或在非导电性材料表面镀敷导电金属而形成。
作为本发明的又另一实施例，主模块可由包含铜(Cu)或铝(Al)等的导电性材料形成，在必要时可在主模块的表面附加地镀覆导电金属。或者，主模块可在陶瓷或绿碳化硅(AlSiC)等非导电性材料表面镀覆导电金属而形成。
并且，如图18、图20及图21所示，主模块510由在第1图案基板530的第1图案531上附着下端侧面的第1主模块511和在第1图案基板530的第2图案532上附着下端侧面的第2主模块512构成。此时，第1主模块511和第2主模块512具有相同的垂直高度，或具有不同的垂直高度，而在第1图案基板530上以不同的垂直高度附着。
然后，在主模块510的一面附着至少一个以上的半导体芯片520。
即，如图22所示，一个以上的半导体芯片520附着在主模块510的上面，并且，将未附着有半导体芯片520的主模块510的下面或侧面垂直地附着在第1图案基板530而电性连接。
在此，半导体芯片520由功率二极管(power diode)和功率DVC(IGBT或MOSFET或GaN)构成，并且，介入形成包括焊料系列或包括Ag或Cu烧结材料的导电性粘接剂521附着在主模块510的上面，并通过金属夹片522或导电配线相互电性连接。
并且，附着在主模块510的一面的半导体芯片520通过电性连接部件与第1图案基板530直接连接。
即，如图23所示，电性连接部件可为与第1图案基板530的第3图案533连接的导电配线523或金属夹片，并且，通过与第3图案533电性连接的接线销524电性连接。
并且，虽未图示，半导体芯片520与第1图案基板530也可介入形成包括另外的独立性的导电金属的导电介质或子模块而电性连接。
换而言之，根据封装结构，半导体芯片520通过电性连接部件与第1图案基板530的第3图案533直接接合而电性连接，或通过导电介质或子模块与第1图案基板530的第3图案533间接接合而电性连接。此时，导电介质或子模块可介入形成主模块和绝缘剂而接合。
然后，在第1图案基板530上形成可电性连接的图案,如图20及图21所示，在第1图案基板530的第1图案531上附着第1主模块511而电性连接，第1图案531通过导电配线和接线销535与外部端子电性连接。
在第1图案基板530的第2图案532上附着第2主模块512而电性连接。
并且，第1图案基板530包括一个以上的金属层和一个以上的绝缘层顺次地层积的结构，并且，可包括顺次地层积第1金属层、绝缘层及第2金属层的结构。
在此，绝缘层可包括选自陶瓷(Al2O3)、氮化铝(AlN)及氮化硅(Si3N4)中的至少一个。
并且，如图21及图23所示，第2图案532可通过导电配线和接线销534与外部端子电性连接。
然后，封装主体540包裹保护主模块510和半导体芯片520，并且，如图20及图21所示，在封装主体540的两侧面贯通封装主体540而形成有第1夹片端子542和第2夹片端子543，所述第1夹片端子542弹性地加压第1图案基板530而固定在底座基板541上，并且，通过第1图案531向第1主模块511供应电性信号，所述第2夹片端子543通过第2图案532向第2主模块512供应电性信号。
在此，第1图案基板530可在下部介入形成有导电性或非导电性的粘接剂(未图示)，而在底座基板541上粘接形成。
并且，底座基板541由导电性材质或非导电性材质构成。
并且，第2图案基板550形成于主模块510的上端，在第2图案基板550上形成有可电性连接的图案，在上面附着有一个以上的半导体芯片520的主模块510的上端侧面及下端侧面分别垂直地附着在第1图案基板530及第2图案基板550之间而电性连接。
根据本发明的又另一实施例，如图18及图19所示，第1主模块511和第2主模块512的未附着半导体芯片520的侧面由垂直方向竖立，而在第1图案基板530及第2图案基板550之间附着形成，并且，第1主模块511和第2主模块512以不同的垂直高度形成，从而，第1主模块511附着在第1图案基板530的第1图案531上而与第1夹片端子542电性连接，第2主模块512附着在第1图案基板530的第2图案532上而与第2图案基板550紧贴，并通过第2夹片端子543电性连接。
在此，第1主模块511和第2主模块512介入形成有隔片513，在第1图案基板530与第2图案基板550之间垂直地竖立而连续地排列，并且，第2图案基板550可在第2主模块512上端以单一结构形成而电性连接，或在第2主模块512上端以多个分段的构成相互交叉而电性连接。
即，如图24所示,第1主模块511和第2主模块512和隔片513形成一个模块组，至少一个以上的模块组在第1图案基板530与第2图案基板550之间电性连接而连续地排列，由此，通过基板530,550之间的主模块的垂直附着结构提高半导体芯片的聚集率，扩大散热面积而提高散热效果。
并且，虽未图示，也可借助于贯通第1主模块511、第2主模块512或隔片513的侧面而与外部循环装置连通的冷却管使得空气、氮气或冷却水的冷却剂循环，由此，降低半导体芯片520的发热。
根据本发明的又另一实施例的半导体封装制造方法，包括如下步骤：准备用于附着一个以上的半导体芯片520的主模块510的步骤；将半导体芯片520附着在主模块510的一面的步骤；准备形成有可电性连接的图案的第1图案基板530的步骤；将主模块510的另一面垂直地附着在第1图案基板530而电性连接的步骤；及形成包裹主模块510及半导体芯片520的封装主体540的步骤，由此，其要旨为借助于半导体芯片的垂直附着结构提高聚集率，扩大散热面积而提高散热效果，并且，将半导体芯片与外部端子直接电性连接而形成小型化。
下面详细说明上面说明的本发明的又另一实施例的半导体封装制造方法。
首先，准备为附着一个以上的半导体芯片520的主模块510，并将半导体芯片520附着在主模块510的一面。
例如，在半导体芯片520介入形成导电性粘接剂521而附着在主模块510的上面。作为本发明的又另一实施例，半导体芯片520由功率二极管(power diode)和功率DVC(IGBT或MOSFET或GaN)构成，通过金属夹片522或导电配线相互电性连接。
在此，主模块510提供附着半导体芯片520的安装空间，并且，通过超音波焊接、焊接或烧结方式附着在形成于第1图案基板530的图案531,532上而电性连接。
此时，主模块可由导电性材料形成，或在非导电性材料表面镀覆导电金属而形成。
作为本发明的又另一实施例，主模块由包括铜(Cu)或铝(Al)等的导电性材料形成，必要时可在主模块的表面附加地镀覆导电金属。或者，主模块可在陶瓷或绿碳化硅(AlSiC)等非导电性材料表面镀覆导电金属而形成。
并且，参照图18、图20及图21，主模块510由在第1图案基板530的第1图案531上附着下端侧面的第1主模块511和在第1图案基板530的第2图案532上附着下端侧面的第2主模块512构成，第1主模块511和第2主模块512具有相同的垂直高度，或具有不同的垂直高度，而在第1图案基板530上以不同的垂直高度附着。
并且，半导体芯片520在主模块510的一面附着至少一个以上，参照图22，将一个以上的半导体芯片520附着在主模块510的上面，将未附着有半导体芯片520的主模块510的下面或侧面垂直地附着在第1图案基板530而电性连接。
在此，半导体芯片520可由功率二极管和功率DVC(IGBT或MOSFET或GaN)构成，包括焊料系列或Ag或Cu烧结材料。
并且，附着在主模块510的一面的半导体芯片520通过电性连接部件与第1图案基板530直接连接。
即，参照图23，电性连接部件可为与第1图案基板530的第3图案533连接的导电配线523或金属夹片，并且，通过与第3图案533电性连接的接线销524电性连接。
并且，虽未图示，半导体芯片520与第1图案基板530也可介入形成另外的独立性的包括导电金属的导电介质或子模块而电性连接。
即，根据封装结构，半导体芯片520通过电性连接部件与第1图案基板530的第3图案533直接接合而电性连接，或也可通过导电介质或子模块与第1图案基板530的第3图案533间接接合而电性连接。此时，导电介质或子模块可介入形成主模块和绝缘剂而接合。
然后，准备形成有可电性连接的图案的第1图案基板530，并将主模块510的另一面垂直地附着在第1图案基板530而电性连接。
在第1图案基板530上形成有可电性连接的图案，参照图20及图21，在第1图案基板530的第1图案531上附着第1主模块511而电性连接，在第1图案基板530的第2图案532上附着第2主模块512而电性连接。
并且，第1图案基板530包括顺次地层积一个以上的金属层和一个以上的绝缘层的结构，并且，可包括顺次地层积第1金属层、绝缘层及第2金属层的结构。
在此，绝缘层可包括选自陶瓷(Al2O3)、氮化铝(AlN)及氮化硅(Si3N4)中的至少某一个。
然后，形成包裹主模块510及半导体芯片520的封装主体540。
封装主体540包裹保护主模块510和半导体芯片520，参照图20及图21，在封装主体540的两侧面贯通封装主体540而形成有第1夹片端子542和第2夹片端子543，所述第1夹片端子542弹性地加压第1图案基板530而固定在底座基板541上，并且，通过第1图案531向第1主模块511供应电性信号，所述第2夹片端子543通过第2图案532向第2主模块512供应电性信号。
在此，第1图案基板530在下部介入形成导电性或非导电性的粘接剂(未图示)而在底座基板541上粘接形成。
并且，底座基板541由导电性材质或非导电性材质形成。
并且，第2图案基板550形成于主模块510上端，在第2图案基板550上形成有可电性连接的图案，并且，在上面附着有一个以上的半导体芯片520的主模块510的上端侧面及下端侧面分别垂直地附着在第1图案基板530与第2图案基板550之间而电性连接。
根据本发明的又另一实施例，参照图18及图19，第1主模块511和第2主模块512是将未附着有半导体芯片520的侧面由垂直方向竖立，而附着在第1图案基板530与第2图案基板550之间形成，第1主模块511和第2主模块512以不同的垂直高度形成，第1主模块511附着在第1图案基板530的第1图案531上而与第1夹片端子542电性连接，第2主模块512附着在第1图案基板530的第2图案532上，而与第2图案基板550紧贴，通过第2夹片端子543电性连接。
在此，第1主模块511和第2主模块512介入形成有隔片513，在第1图案基板530与第2图案基板550之间垂直地竖立而连续地排列，并且，第2图案基板550在第2主模块512上端以单一结构形成而电性连接，或在第2主模块512上端以多个分段的构成相互交叉而电性连接。
即，参照图24，第1主模块511和第2主模块512和隔片513形成一个模块组，至少一个以上的模块组在第1图案基板530与第2图案基板550之间电性连接而连续地排列，由此，借助于基板530,550之间的主模块的垂直附着结构，提高半导体芯片的聚集率，并且，扩大散热面积而提高散热效果。
并且，虽未图示，也可包括形成贯通第1主模块511、第2主模块512或隔片513的侧面而与外部循环装置连通的冷却管的步骤，从而，通过冷却管使得空气、氮气或冷却水的冷却剂循环，而降低半导体芯片520的发热。
由此，通过如上述的半导体封装的构成，借助于通过基板上的主模块的半导体芯片的垂直附着结构，提高半导体芯片的聚集率，并且，扩大散热面积而提高半导体芯片的散热效果，并且，将附着在主模块的半导体芯片与外部端子直接电性连接而形成小型化。
并且，在由上下形成的第1图案基板与第2图案基板之间垂直地排列半导体芯片，从而，更加扩大散热面积，更加提高冷却效率。
并且，借助于贯通附着有半导体芯片的主模块或隔片的侧面而与外部循环装置连通的冷却管，使得冷却剂循环，更加降低半导体芯片的发热。
以上参照附图中表示的实施例说明了本发明。但，本发明并非限定于此，本发明的技术领域的普通技术人员可实施属于与本发明均等的范围的各种变形例或其他实施例。从而，本发明的真正的保护范围应当根据权利要求范围而定义。

Claims (11)

1.一种半导体封装件，其特征在于，包括：
主模块；
至少一个子模块，通过介入绝缘剂与所述主模块接合；
至少一个半导体芯片，通过介入粘接剂附着在所述主模块的上表面或者上下表面两侧；
基板，具有可电性连接的图案；以及
包裹所述主模块、所述子模块、所述半导体芯片和所述基板的半导体封装主体，
所述主模块的一侧面垂直地附着在所述基板的图案并电性连接，
所述主模块和所述子模块包括导电金属，
在所述主模块的上表面或者上下表面两侧附着安装有至少一个所述半导体芯片，
所述半导体芯片由功率二极管和功率DVC构成，
所述功率二极管与所述功率DVC通过金属夹片电性连接，所述功率DVC和所述子模块通过第一导电配线电性连接，构成单位的功率模块，
由第1功率模块、第2功率模块和隔片模块组成的组模块以侧面竖立而垂直地附着在所述基板的图案而相互电性连接，
所述组模块的子模块和所述基板通过第二导电配线电性连接，
在所述基板上形成有连接到第三导电配线的接线销，所述接线销垂直形成在所述基板上或插入形成于所述半导体封装主体而通过所述第三导电配线与所述基板电性连接。
2.根据权利要求1所述的半导体封装件，其特征在于，还包括：
孔，形成于所述主模块或所述隔片模块而使冷却剂循环。
3.根据权利要求1或2所述的半导体封装件，其特征在于，
所述粘接剂含有焊料系列。
4.根据权利要求1或2所述的半导体封装件，其特征在于，
所述粘接剂含有Ag或Cu烧结材料。
5.根据权利要求1或2所述的半导体封装件，其特征在于，
所述基板由绝缘物质和在所述绝缘物质上形成的金属图案构成。
6.根据权利要求1或2所述的半导体封装件，其特征在于，
在所述主模块的另一侧面还包括相互电性连接的另一个基板。
7.根据权利要求6所述的半导体封装件，其特征在于，
所述基板及所述另一个基板由一个以上的金属层、绝缘层、一个以上的金属层顺次地层积而形成，或由一个以上的金属层和绝缘层顺次地层积而形成。
8.根据权利要求7所述的半导体封装件，其特征在于，
所述基板及所述另一个基板由单一的金属层形成，所述金属层的厚度为0.1mm至10mm。
9.根据权利要求2所述的半导体封装件，其特征在于，
所述孔形成在所述主模块上，
还包括冷却管：其从所述半导体封装主体外部向所述主模块的孔延伸形成，以使冷却剂循环。
10.根据权利要求2所述的半导体封装件，其特征在于，
所述孔形成在所述隔片模块上，
还包括冷却管：其从所述半导体封装主体外部向所述隔片模块的孔延伸形成，以使冷却剂循环。
11.根据权利要求2所述的半导体封装件，其特征在于，
所述冷却剂使用空气、氮气或冷却水。
CN202010381690.5A 2019-06-14 2020-05-08 半导体封装 Active CN112086413B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2019-0070583 2019-06-14
KR1020190070583A KR102244279B1 (ko) 2019-06-14 2019-06-14 반도체 패키지
KR1020200033834A KR102355687B1 (ko) 2020-03-19 2020-03-19 반도체 패키지 및 반도체 패키지 제조방법
KR10-2020-0033834 2020-03-19

Publications (2)

Publication Number Publication Date
CN112086413A CN112086413A (zh) 2020-12-15
CN112086413B true CN112086413B (zh) 2024-04-23

Family

ID=73735948

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010381690.5A Active CN112086413B (zh) 2019-06-14 2020-05-08 半导体封装

Country Status (2)

Country Link
US (1) US11482463B2 (zh)
CN (1) CN112086413B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6717266B2 (ja) * 2017-06-28 2020-07-01 株式会社オートネットワーク技術研究所 回路装置
KR102499825B1 (ko) * 2021-02-05 2023-02-14 파워마스터반도체 주식회사 패키지형 전력 반도체 장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012004543A (ja) * 2010-05-17 2012-01-05 Fuji Electric Co Ltd 半導体ユニットおよびそれを用いた半導体装置
CN103681545A (zh) * 2012-09-26 2014-03-26 三星电机株式会社 功率模块封装
KR20160109573A (ko) * 2015-03-12 2016-09-21 제엠제코(주) 클립을 이용한 반도체 칩 패키지 및 그를 위한 제조방법
CN108257940A (zh) * 2016-12-28 2018-07-06 三菱电机株式会社 半导体装置及其制造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960003212B1 (ko) 1993-08-04 1996-03-07 이장무 엔시(Numerical Control) 절삭시스템 이상진단을 위한 진동 모니터링 방법과 장치
JPH07202120A (ja) 1993-12-28 1995-08-04 Hitachi Ltd 高放熱型メモリおよび高放熱型メモリモジュール
US6191474B1 (en) * 1997-12-31 2001-02-20 Micron Technology, Inc. Vertically mountable interposer assembly and method
JP2002093988A (ja) 2000-09-20 2002-03-29 Nippon Avionics Co Ltd 半導体集積回路パッケージ
US6483705B2 (en) 2001-03-19 2002-11-19 Harris Corporation Electronic module including a cooling substrate and related methods
US9029898B2 (en) * 2009-08-26 2015-05-12 Formosa Epitaxy Incorporation Light emitting diode and illumination device using same
US9614129B2 (en) * 2010-08-14 2017-04-04 Seoul Semiconductor Co., Ltd. Light emitting device having surface-modified luminophores
US8390109B2 (en) * 2011-02-17 2013-03-05 Oracle America, Inc. Chip package with plank stack of semiconductor dies
CN203277498U (zh) * 2012-05-29 2013-11-06 璨圆光电股份有限公司 发光组件及其发光装置的装置基座
JP5831401B2 (ja) * 2012-08-24 2015-12-09 三菱電機株式会社 半導体装置
KR101694657B1 (ko) 2016-08-04 2017-01-09 제엠제코(주) 방열 구조를 갖는 반도체 패키지
US10249552B2 (en) 2017-02-22 2019-04-02 Jmj Korea Co., Ltd. Semiconductor package having double-sided heat dissipation structure
KR101920915B1 (ko) 2017-04-26 2018-11-21 제엠제코(주) 방열구조를 갖는 반도체 패키지

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012004543A (ja) * 2010-05-17 2012-01-05 Fuji Electric Co Ltd 半導体ユニットおよびそれを用いた半導体装置
CN103681545A (zh) * 2012-09-26 2014-03-26 三星电机株式会社 功率模块封装
KR20160109573A (ko) * 2015-03-12 2016-09-21 제엠제코(주) 클립을 이용한 반도체 칩 패키지 및 그를 위한 제조방법
CN108257940A (zh) * 2016-12-28 2018-07-06 三菱电机株式会社 半导体装置及其制造方法

Also Published As

Publication number Publication date
US11482463B2 (en) 2022-10-25
CN112086413A (zh) 2020-12-15
US20200395264A1 (en) 2020-12-17

Similar Documents

Publication Publication Date Title
US10297522B2 (en) Semiconductor package structure and manufacturing method thereof
US10636732B2 (en) Power module based on multi-layer circuit board
US8513059B2 (en) Pre-molded clip structure
CN106997871B (zh) 一种功率模块的封装结构
US8309399B2 (en) Power semiconductor module and method of manufacturing the same
US7466020B2 (en) Power module
US8916958B2 (en) Semiconductor package with multiple chips and substrate in metal cap
US10079195B2 (en) Semiconductor chip package comprising laterally extending connectors
US20120235293A1 (en) Semiconductor device including a base plate
WO2008027708A2 (en) Semiconductor die package including stacked dice and heat sink structures
CN112086413B (zh) 半导体封装
CN114765151A (zh) 在层合物和导热载体之间具有包封的电子部件的封装体
US20180247924A1 (en) Electronics package having a multi-thickness conductor layer and method of manufacturing thereof
US20070145576A1 (en) Power Semiconductor Circuit And Method Of Manufacturing A Power Semiconductor Circuit
KR102244279B1 (ko) 반도체 패키지
US11955407B2 (en) Electronic module including a semiconductor package connected to a fluid heatsink
JP2010225952A (ja) 半導体モジュール
EP4016618A1 (en) Power device packaging
KR102264132B1 (ko) 반도체 패키지
CN114600238A (zh) 高功率密度3d半导体模块封装
CN112786567A (zh) 一种半导体功率模组及半导体功率模组的封装方法
KR102355687B1 (ko) 반도체 패키지 및 반도체 패키지 제조방법
CN111244061A (zh) 氮化镓设备的封装结构
US20230369160A1 (en) Semiconductor Device Package Thermally Coupled to Passive Element
US11450623B2 (en) Semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant