CN111244061A - 氮化镓设备的封装结构 - Google Patents

氮化镓设备的封装结构 Download PDF

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Publication number
CN111244061A
CN111244061A CN201911057318.2A CN201911057318A CN111244061A CN 111244061 A CN111244061 A CN 111244061A CN 201911057318 A CN201911057318 A CN 201911057318A CN 111244061 A CN111244061 A CN 111244061A
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China
Prior art keywords
substrate
traces
die
package
electrically insulating
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CN201911057318.2A
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Inventor
S·圣日尔曼
R·阿巴斯诺特
D·比林斯
A·塞拉亚
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Semiconductor Components Industries LLC
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Semiconductor Components Industries LLC
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Publication of CN111244061A publication Critical patent/CN111244061A/zh
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Abstract

本发明题为“氮化镓设备的封装结构”。本发明提供了一种半导体封装件的实施方式。该半导体封装件的实施方式可包括：衬底，该衬底具有第一侧上的一条或多条迹线以及第二侧上的一条或多条迹线。衬底可以是刚性的。封装件，该封装件可包括以机械的方式和电的方式耦接到衬底的第一侧的至少一个管芯。管芯可以是高压管芯。封装件可包括沿衬底的一个或多个边缘的一条或多条迹线。沿衬底的一个或多个边缘的一条或多条迹线提供衬底第一侧上的一条或多条迹线与衬底第二侧上的一条或多条迹线之间的电连接。封装件还可包括模塑料，模塑料包封至少第一侧和该陶瓷衬底的一个或多个边缘。

Description

氮化镓设备的封装结构
背景技术
1.技术领域
本文件的各方面整体涉及半导体封装件，诸如电子设备的功率模块。更具体的实施方式涉及单管芯模块和多管芯模块，诸如开关。
2.背景技术
具有高压管芯的功率模块包括引线框架或印刷电路板衬底。已知高压管芯由于较大的电压和快速的切换速度而产生大量的热量。管芯可通过夹具和焊线电耦接到功率和信号。
发明内容
半导体封装件的实施方式可包括：衬底，该衬底具有第一侧上的一条或多条迹线以及衬底的第二侧上的一条或多条迹线。衬底可以是刚性的。封装件可包括以机械的方式和电的方式耦接到衬底的第一侧的至少一个管芯。管芯可以是高压管芯。封装件可包括沿衬底的一个或多个边缘的一条或多条迹线。沿衬底的一个或多个边缘的一条或多条迹线在衬底的第一侧上的一条或多条迹线与在衬底的第二侧上的一条或多条迹线之间提供电连接。封装件还可包括模塑料，模塑料包封至少所述第一侧和衬底的一个或多个边缘。
半导体封装件的实施方式可包括以下各项中的一项、全部或任一项：
衬底可以是陶瓷的，并且陶瓷可以是氮化铝、氧化铝或它们的任何组合。
衬底可为直接接合铜衬底。
管芯可包括氮化镓。
封装件还可包括将所述一个或多个管芯电耦接到所述衬底的夹具或两个或更多个焊线中的一者。
夹具可包括3密耳至20密耳的厚度。
封装件还可包括耦接到衬底的所述第一侧或第二侧的一个或多个铜柱。
半导体封装件的实施方式可包括：陶瓷衬底，该陶瓷衬底包括第一侧上的一条或多条迹线以及陶瓷衬底的第二侧上的一条或多条迹线。陶瓷衬底可以是电绝缘的。封装件还可包括以机械的方式和电的方式耦接到陶瓷衬底的第一侧的至少一个管芯。至少一个管芯可为高压管芯。封装件还可包括一条或多条迹线，一条或多条迹线从陶瓷衬底的第一侧延伸到第二侧。封装件还可包括模塑料，模塑料包封至少第一侧和陶瓷衬底的一个或多个边缘。封装件中的一条或多条迹线在陶瓷衬底的第一侧上的一条或多条迹线与在陶瓷衬底的第二侧上的一条或多条迹线之间提供电连接。
半导体封装件的实施方式可包括以下各项中的一项、全部或任一项：
衬底可以是陶瓷的，并且可包括氮化铝、氧化铝或它们的任何组合。
管芯可包括氮化镓。
封装件还可包括将所述一个或多个管芯电耦接到衬底的夹具或两个或更多个焊线中的一者。
夹具可包括3密耳至20密耳的厚度。
封装件还可包括耦接到陶瓷衬底的所述第一侧或所述第二侧的一个或多个铜柱。
形成半导体封装件的方法的实施方式可包括：提供两个或更多个电绝缘衬底，衬底各自具有第一侧和第二侧以及穿过第一侧和第二侧的多个开口。从两个或更多个电绝缘衬底的第一侧到两个或更多个电绝缘衬底的第二侧，通过多个开口形成一条或多条迹线。形成半导体封装件的方法中还可包括在两个或更多个电绝缘衬底的第一侧和第二侧中的每一个上形成一条或多条迹线。该方法还可包括在多个开口处切割两个或更多个电绝缘衬底。该方法还包括将一个或多个管芯耦接到两个或更多个电绝缘衬底中的每一个的第一侧并且包封一个或多个管芯以及两个或更多个电绝缘衬底中的每一个。
形成半导体封装的方法的实施方式可包括以下各项中的一项、全部或任一项：
电绝缘衬底的第二侧上的所述一条或多条迹线可为暴露的。
一条或多条迹线可沿两个或更多个电绝缘衬底中的每一个的一个或多个边缘形成。
该方法还可包括在电绝缘衬底的平坦表面中形成一个或多个通孔。
该方法还可包括将一个或多个夹具或两个或更多个焊线中的一者耦接到一个或多个管芯和一条或多条迹线。
一个或多个夹具可具有3密耳至20密耳的厚度。
电绝缘衬底可以是陶瓷或直接粘结的铜衬底。
对于本领域的普通技术人员而言，通过说明书和附图并且通过权利要求书，上述以及其他方面、特征和优点将会显而易见。
附图说明
将在下文中结合附图来描述实施方式，在附图中类似标号表示类似元件，并且：
图1是半导体封装件的实施方式的剖视图；
图2是半导体封装件的另一个实施方式的剖视图；
图3是半导体封装件的实施方式的剖视图；
图4是具有两个管芯的半导体封装件的实施方式的顶部透视图；
图5是半导体封装件的实施方式的顶视图；
图6是具有一个管芯的半导体封装件的实施方式的透视图；
图7是半导体封装件的实施方式的透视图；
图8是衬底的实施方式的透视图，所述衬底具有从衬底的第一侧延伸到衬底的第二侧的通孔；
图9是具有迹线的衬底的平面的实施方式的透视图；
图10是在迹线上具有管芯附接材料的衬底的实施方式的透视图；
图11是耦接到衬底的管芯的实施方式的透视图；
图12是管芯上的粘合剂的实施方式的透视图；
图13是耦接到管芯和衬底的夹具的实施方式的透视图；
图14是通过焊线耦接的衬底上的部件的实施方式的透视图；
图15是切割后的两个衬底的实施方式的透视图；
图16是耦接到安装带的衬底的侧视图；
图17是包封后的第一侧半导体的实施方式的透视图；
图18是包封的半导体封装件的第二侧的实施方式的透视图；
图19是半导体封装件的第一侧的实施方式的顶视图；
图20是半导体封装件的第二侧的实施方式的顶视图；
图21是功率模块的实施方式的侧视图；和
图22是半导体模块的实施方式的透视图。
具体实施方式
本公开、其各方面以及实施方式并不限于本文所公开的具体部件、组装工序或方法元素。本领域已知的符合预期半导体封装的许多另外的部件、组装工序和/或方法元素将显而易见地能与本公开的特定实施方式一起使用。因此，例如，尽管本发明公开了特定实施方式，但是此类实施方式和实施部件可包括符合预期操作和方法的本领域已知用于此类半导体封装件以及实施部件和方法的任何形状、尺寸、样式、类型、模型、版本、量度、浓度、材料、数量、方法元素、步骤，和/或类似的。
参见图1，示出了半导体封装2的实施方式。半导体封装件2是单个高压管芯封装件的示例。封装件包括具有第一侧6和第二侧8的刚性衬底4。衬底4可以是/包括电绝缘材料。电绝缘材料也可为热绝缘的。因为电绝缘材料是热绝缘的，所以主热路径可在封装件的第二侧8之外。在各种实施方式中，衬底可为直接接合铜(DBC)衬底。在其他实施方式中，衬底可包括陶瓷衬底上的厚膜图案。通过非限制性示例，陶瓷衬底可包括氮化铝(AlN)、氧化铝(Al2O3)、或它们的任何组合。氮化铝陶瓷可提供附加的热绝缘性能。迹线10和12位于衬底4的第一侧6和第二侧8上。在各种实施方式中，迹线可以是铜。在其他实施方式中，迹线可以是金、镍、锡、铅、它们的任何组合或合金(包括铜的合金)或其他导电材料。衬底4的第一侧6和第二侧8上的迹线10和12通过衬底4的边缘16上的迹线14连接。在各种实施方式中，衬底的一个或多个边缘上/横跨衬底的一个或多个边缘可存在一条或多条迹线。在各种实施方式中，衬底的单个边缘上/横跨衬底的单个边缘可存在多条迹线，并且衬底的若干边缘可包括迹线。迹线可在衬底的第一侧和第二侧上的迹线之间提供电/热连接。
管芯18耦接到衬底4的第一侧6。管芯可通过导电材料诸如环氧树脂、管芯附接膜、焊料、银烧结或能够将管芯粘结到衬底上的任何其他材料来耦接。在一些实施方式中，管芯18可使用倒装芯片技术使用球或柱耦接到导电迹线10。在各种实施方式中，管芯为高压管芯，这意味着管芯旨在处理大于200V的输入电势。管芯可由衬底材料形成，所述衬底材料可为(作为非限制性示例)氮化镓、二氧化硅、玻璃、绝缘体上的硅、砷化镓、蓝宝石、红宝石、碳化硅、任何前述物质的多晶或无定形形式，以及用于半导体设备的任何其它类型的衬底类型。高压管芯18的所有区域可通过迹线10直接耦接到衬底4。管芯18也通过柱20电耦接到衬底。在各种实施方式中，柱可以是铜。在其他实施方式中，封装件可不包括柱。管芯也电耦接到夹具22。在各种实施方式中，夹具可以是铜。在各种实施方式中，夹具可具有在约3密耳至约20密耳范围内的厚度。在一些实施方式中，夹具可具有5密耳的厚度。在其他实施方式中，夹具可具有10密耳的厚度。通过非限制性示例，夹具可被半蚀刻、形成或可为形成和半蚀刻的组合。在其他实施方式中，焊线可用于代替夹具。
如图1所示，封装件2还包括模塑料24，该模塑料包封衬底4的第一侧6和衬底的边缘16。在各种实施方式中，衬底的一个或多个边缘可被包封。在其他实施方式中，设备/封装件的边缘上不暴露任何部件。如图所示，夹具22未被模塑料24包封，这可在结合到较大设备中时为封装件提供电/热连接。暴露的夹具22还可允许更好的热分散。在各种实施方式中，衬底4上的迹线10和12也可暴露以实现连通性和热性能。在实施方式中，衬底的第二侧上的迹线12被暴露。在一些实施方式中，模塑料可包括环氧树脂、树脂、热塑性塑料以及适用于高压封装的其它模塑料。可选择模塑料类型以便提高封装件的可靠性。
参见图2，示出了半导体封装26的另一种实施方式。半导体封装件包括通过迹线34耦接到刚性衬底32的两个管芯28和30。迹线34和36分别耦接到衬底的第一侧和衬底的第二侧。衬底32可以是直接粘结的铜衬底(DBC)、陶瓷衬底上的厚膜图案或其它刚性的、热的和电绝缘的材料。在衬底32为DBC衬底的实施方式中，DBC衬底可包括夹置在两个铜层之间的陶瓷板，层中的一层与衬底的第一侧上的迹线与位于衬底的第二侧内部并延伸到衬底的第二侧的迹线形成连接。在其他实施方式中，DBC衬底可包括陶瓷板和仅单个铜层，单个铜层与衬底的第二侧上的迹线形成连接。DBC上的铜层可通过衬底边缘上的迹线延伸到衬底的第二侧。
在各种实施方式中，衬底32和相关封装保持封装内部和外部的电隔离。第一侧34和第二侧36上的迹线通过衬底32的边缘40上的迹线38电连接。在各种实施方式中，从衬底的第一侧延伸到衬底的第二侧的迹线可直接穿过衬底，如图8所示。从衬底的第一侧延伸到衬底的第二侧的迹线可通过钻孔、模制或激光钻孔形成。在各种实施方式中，迹线34，36，38包括铜。在其他实施方式中，迹线可由金、银、铝、锡、镍、它们的任何合金以及其他导电材料形成。使用具有从衬底的第一侧延伸到衬底的第二侧的迹线的刚性衬底可减小封装尺寸，同时允许热传递并保持封装内的电隔离。二氧化硅可在各种实施方式中用作焊料阻挡/支座。
图2中的半导体封装件26用模塑料42包封。模塑料42包封封装件的边缘40，而没有侧特征部被暴露。在衬底32的第一侧上，模塑料42包封管芯28，30和夹具44，46的一部分，如图所示。夹具44，46将管芯28，30与衬底32上的迹线34，36电耦接。夹具44，46的一些部分通过模塑料42暴露，从而允许与较大半导体设备中的其他部件电连接。通过非限制性示例，通过使用焊料、导电粘合剂等将封装件的第二侧上的暴露的迹线附接到这些元件的接触件，可以将半导体封装件耦接到母板、印刷电路板(PCB)、散热器、散热片、或一个或多个热管、一个或多个电源、一个或多个电气接地件、和/或任何其它电子部件。在一些实施方式中，单独的半导体封装件的进一步封装可在进行此类连接之前进行。在其他实施方式中，封装件可被堆叠，并且多个封装件可通过暴露的夹具和暴露的迹线两者电连接。
在如本文所述的半导体封装件的各种实施方式中，封装件内的管芯可为功率半导体管芯，诸如作为非限制性示例，功率金属氧化物半导体场效应晶体管(功率MOSFET)、绝缘栅双极晶体管(IGBT)和/或其他功率半导体管芯类型。在其他实施方式中，封装件可不包括功率半导体管芯，但可包括能够处理高电压的各种无源部件。在其他实施方式中，除了一个或多个非功率半导体管芯之外，封装件还可包括一个或多个功率半导体管芯。
参见图3，示出了半导体封装48的另一种实施方式。封装件48包括单个管芯50，该管芯通过倒装芯片连接54耦接至衬底52。在各种实施方式中，管芯50为高压管芯。在操作期间，高压管芯可达到比硅管芯更高的温度。较高的温度是由于高电压管芯所特有的大电压和更快的切换速度。在各种实施方式中，衬底52包括衬底52的第一侧58上的迹线56和衬底52的第二侧60上的迹线62。在各种实施方式中，迹线可以是铜迹线。在其他实施方式中，迹线可为金、锡/铅、银、铝、它们的任何合金、以及其它高可靠性导电材料。
如图3所示，封装件48包括耦接到衬底52上的并延伸到封装件的模塑料66外部的迹线56的柱64。模塑料66包封衬底的边缘。在封装件48的第一侧68上，柱的第二端部70被暴露以允许与电气设备中的部件电连接。相似地，衬底52的第二侧62上的迹线60不用模塑料66包封以允许热耗散以及电连接。
参见图4，示出了不包括模塑料的半导体封装件72的实施方式的透视图。在图5中，其中示出了半导体封装件72的第一侧的顶视图。封装件72包括耦接到衬底80上的迹线78的两个管芯74和76。在各种实施方式中，衬底80可为刚性的并且可包括陶瓷。在一些实施方式中，陶瓷可包括氮化铝(AlN)、氧化铝(Al2O3)、或它们的任何组合。陶瓷衬底80包括从衬底80的第一侧82延伸至衬底80的第二侧84的迹线78。在各种实施方式中，迹线可通过厚膜图案形成在衬底上形成的线上。从衬底的第一侧延伸到衬底的第二侧的迹线可通过钻孔、冲压、蚀刻、模制以及在刚性材料中制造孔的其它方法形成。
管芯74和76通过夹具86和焊线88电耦接到封装件中的其他部件。在各种实施方式中，其他部件可包括电容器、晶体管和其他无源部件。在一些实施方式中，封装件可仅包括部件并且不包括半导体管芯。穿过衬底和围绕衬底形成迹线可有助于减小封装件尺寸。通过非限制性示例，一个或多个衬底可被堆叠并通过夹具和迹线电耦接。在各种实施方式中，衬底可在用模塑料包封之前或之后堆叠。在一些实施方式中，由于使用横跨封装件的边缘连接的迹线，因此在半导体封装件内的电耦接部件中不可使用焊线。
参见图6，示出了具有一个管芯的半导体封装件89，其被模塑料90包封。在该图示中，模塑料90是可见的，以允许包括夹具92、管芯94、焊线96、迹线98和衬底100在内的封装件内的部件的可见性。模塑料90被示出为包封封装件89的边缘102，使得不暴露导电部件。在该视图中，夹具被暴露以允许连接和散热。衬底的第二侧上的迹线也不用模塑料包封以用于电连接。在各种实施方式中，半导体封装件可在封装之后堆叠。
参见图7和图8，示出了半导体封装件102的实施方式。在图7中，示出了用模塑料104包封的封装件102。为了进行示意性的说明，模塑料是可见的。示出了将管芯108耦接到衬底110上的迹线的夹具106。参见图8，示出了从衬底110的第一侧114延伸至衬底110的第二侧116的迹线/通孔112。这些迹线112允许通过电绝缘衬底110的电连接。在各种实施方式中，衬底可通过迹线堆叠并电耦接在一起。如本文所示和所述的迹线可允许较小的封装。
现在参见图9至图18，示出了形成半导体封装件的方法中使用的各种元件。形成半导体封装件的方法包括提供衬底的面板。在图9中，示出了衬底120的面板118的实施方式的示例。在该具体的实施方式中，面板中示出了两个衬底120。在其他实施方式中，单个面板中可包括多于两个的衬底。衬底中的每一个包括从衬底120的第一侧124延伸至衬底120的第二侧126的迹线122。用于形成半导体封装件的方法可包括在衬底中形成迹线。在各种实施方式中，迹线可通过钻孔、蚀刻、图案化或本文所述的任何其他方法形成。迹线可包括铜、金、银、锡、镍、它们的任何合金、它们的任何组合或前述的任何导电材料。在形成迹线之后，然后将衬底切割。
参见图10，衬底120被示出为具有耦接到迹线122的管芯附接材料128。管芯附接材料128可包括银烧结、环氧树脂、焊料和其他导电材料。管芯附接材料128可用于将两个或更多个管芯耦接到衬底。其他部件也可耦接到衬底和在其上的迹线。形成半导体封装件的方法可包括将一个或多个管芯耦接到两个或更多个衬底120中的每一个的第一侧。参见图11，示出了通过管芯附接材料耦接到迹线的部件130。在各种实施方式中，部件可包括氮化镓(GaN)管芯132。在其他实施方式中，部件130可包括电容器、晶体管和其他无源部件。在一些实施方式中，部件可形成开关，诸如IGBT和MOSFET。部件可包括其他大功率半导体设备。管芯可通过倒装芯片方法耦接到迹线。将高压管芯翻转到导热且电绝缘的衬底上可允许大多数热量流过衬底。与铜引线框架设计相比，衬底的绝缘和隔离特性可允许在布线高电压管芯和其他部件之间的互连时采用不同的设计规则。这部分是因为路由氮化镓管芯所需的电连接布线不再需要经由引线接合来处理，而是通过衬底上的迹线进行处理，同时通过夹具处理与氮化镓管芯的相对侧的连接。另外，因为仅使用夹具来处理氮化镓管芯的一侧上的连接，并且在衬底自身上处理其他互连，所以衬底的其他部件(以及封装件周围的其他部件)不需要遵循传统的间距设计规则，这些规则要求保持一定的间距以确保不发生电弧。
参见图12，示出了耦接到管芯132的第二侧的粘合剂材料134。粘合剂材料136也被施加到迹线122。粘合剂材料可包括银烧结、管芯附接膜、环氧树脂、焊料和其他导电材料。参见图13，其示出了具有耦接到管芯132和迹线122的夹具138的半导体封装件。夹具138将管芯132与迹线122以电的方式和机械的方式耦接。夹具可被蚀刻或半蚀刻，其厚度在3密耳至20密耳的范围内。在其他实施方式中，可形成夹具。在其他实施方式中，制造夹具的方法可包括形成夹具和蚀刻夹具的组合。在将夹具耦接到封装件之后，进行粘合剂的回流和固化。在其他实施方式中，可使用焊线将管芯132与迹线122耦接。在图14中，在部件130已通过焊线140耦接之后，示出半导体封装件。形成半导体封装件的方法还包括将衬底面板切割成单独的衬底。参见图15，在切割之后示出了衬底120中的每一个。在各种实施方式中，可通过激光切割将衬底切割。该方法还可包括将一个或多个衬底安装到带材上以进一步加工。在图16中示出了安装到带材142的衬底120的示例。双带材方法可用于各种实施方式中。在该侧视图中，衬底120的边缘144被示出为具有从衬底的第一侧延伸到第二侧的迹线122。焊线140被示出为将管芯132耦接到迹线122。在其他实施方式中，该方法可仅包括倒装芯片接合并且不包括焊线。在其他方法中，与普通焊线长度相比，焊线可缩短，因为不需要施加普通的设计规则。
该方法还包括将半导体封装件包封在模塑料中。参见图17，在用模塑料148包封之后，示出了半导体封装件146的第一侧的顶视图。夹具132暴露在半导体封装件的第一侧上。暴露的夹具132可提供穿过封装件的附加热路径。在各种实施方式中，附加散热器可耦接到夹具或可添加其他冷却选项。在图18中，示出了包封之后封装件146的第二侧150的视图。从衬底的第一侧延伸到衬底的第二侧的迹线122被暴露以提供与其他半导体设备的连接。暴露的迹线也可提供穿过封装件的附加热路径。
参见图19至图20，示出了多芯片模块152的实施方式。在图19中，示出了模块152的第一侧153的顶视图，其中A为邻近边缘的侧视图，并且B为该邻近边缘的侧视图。在图19中，示出了耦接到衬底156的第一侧的部件154。示出了两个夹具158，每个夹具耦接到管芯。迹线160被示出为在衬底的周边内并且也在衬底的边缘上从衬底156的第一侧162延伸到衬底156的第二侧164。在各种实施方式中，两个或更多个焊线可将管芯耦接到迹线。在图20中，示出了模块152的第二侧157的顶视图。示出了衬底边缘上的迹线166，并且示出了具有正方形形状的用于附加迹线的接触件168。在各种实施方式中，接触件可包括其他几何形状。
在表1和表2中，示出了图19的陶瓷多芯片模块的模拟结果和具有类似部件的印刷电路板(PCB)设备。用两种不同类型的陶瓷AlN和Al3O2进行模拟。在单冷却路径模拟(表1)中，两个陶瓷设备的每瓦特的温度出乎意料地低于PCB设备。氮化铝衬底在总体温度上显示出21％的改善。在具有耦接到设备的第一侧的散热器的双冷却路径模拟(表2)中，示出了甚至更大的温度改善。与四层PCB衬底相比，氮化铝衬底导致总体温度改善50％。
表1
Figure BDA0002256831500000101
表2
Figure BDA0002256831500000102
将图19至图20中的多芯片模块152与图21(170)至图22(172)中所示的半导体封装件进行比较，多芯片模块152具有更紧凑的设计。与图21中的封装件170不同，不存在从多芯片模块152延伸的突出部。多芯片模块152具有单个连接层，而图21中的设备170具有增加封装件厚度的至少两个层。多芯片模块152也不具有暴露在模块边缘上的电连接器。模块的这一方面意味着，不需要将高电压设备的普通间隔规则应用于将模块放置在母板或电路板上，这进一步节省了电路板空间。与图22中的设备172不同，多芯片模块152不需要从衬底的主要部分延伸的引线。与图22的引线框设计174相比，多芯片模块152的包封可提高可靠性。在焊线用于连接部件的各种实施方式中，多芯片模块152中的那些焊线可短于具有引线框架设计的半导体封装件中的焊线，其示例示出于图22中。通过多芯片模块152中的迹线实现的内部布线减小了总体封装件尺寸。当多芯片模块被包括在电子设备中时，封装件尺寸的减小可减小空间限制。
半导体封装件的实施方式可包括衬底，该衬底可为陶瓷的并且包括氮化铝、氧化铝或它们的任何组合中的一种。
在半导体封装件的各种实施方式中，衬底可为直接接合铜衬底。
在半导体封装件的各种实施方式中，管芯可包括氮化镓。
半导体封装件的实施方式可包括厚度在3密耳至20密耳之间的一个或多个夹具。
半导体封装件的实施方式可包括将一个或多个管芯电耦接到衬底的夹具或两个或更多个焊线。
半导体封装件的实施方式可包括其中电绝缘衬底为陶瓷衬底或直接接合铜衬底的情况。
在以上描述中提到半导体封装件的具体实施方式以及实施部件、子部件、方法和子方法的地方，应当显而易见的是，可在不脱离其实质的情况下作出多种修改，并且这些实施方式、实施部件、子部件、方法和子方法可应用于其他半导体封装件。

Claims (10)

1.一种半导体封装件，包括：
衬底，所述衬底包括第一侧上的一条或多条迹线和所述衬底的第二侧上的一条或多条迹线，其中所述衬底为刚性的；
至少一个管芯，所述至少一个管芯以机械的方式和电的方式耦接到所述衬底的所述第一侧，其中所述管芯为高压管芯；
一条或多条迹线，所述一条或多条迹线沿所述衬底的一个或多个边缘；和
模塑料，所述模塑料包封所述衬底的至少所述第一侧和所述衬底的所述一个或多个边缘；
其中沿所述衬底的所述一个或多个边缘的所述一条或多条迹线在所述衬底的所述第一侧上的所述一条或多条迹线与在所述衬底的所述第二侧上的所述一条或多条迹线之间提供电连接。
2.根据权利要求1所述的设备，还包括将所述一个或多个管芯电耦接到所述衬底的夹具或两个或更多个焊线中的一者。
3.根据权利要求1所述的设备，还包括耦接到所述陶瓷衬底的所述第一侧或所述第二侧中的一者的一个或多个铜柱。
4.一种半导体封装件，包括：
陶瓷衬底，所述陶瓷衬底包括第一侧上的一条或多条迹线和所述刚性陶瓷衬底的第二侧上的一条或多条迹线，其中所述陶瓷衬底为电绝缘的；
至少一个高压管芯，所述至少一个高压管芯以机械的方式和电的方式耦接到所述陶瓷衬底的所述第一侧；
一条或多条迹线，所述一条或多条迹线从所述陶瓷衬底的所述第一侧延伸到所述第二侧；和
模塑料，所述模塑料包封至少所述第一侧和所述陶瓷衬底的所述一个或多个边缘；
其中所述一条或多条迹线在所述陶瓷衬底的所述第一侧上的所述一条或多条迹线与在所述陶瓷衬底的所述第二侧上的所述一条或多条迹线之间提供所述电连接。
5.根据权利要求4所述的设备，还包括耦接到所述衬底的所述第一侧或所述第二侧中的一者的一个或多个铜柱。
6.一种用于形成半导体设备的方法，所述方法包括：
提供两个或更多个电绝缘衬底，所述衬底各自具有第一侧和第二侧以及穿过所述第一侧和所述第二侧的多个开口；
从所述两个或更多个电绝缘衬底的第一侧到所述两个或更多个电绝缘衬底的所述第二侧，形成通过所述多个开口的一条或多条迹线；
在所述两个或更多个电绝缘衬底的所述第一侧和所述第二侧中的每一个上形成一条或多条迹线；
在所述多个开口处切割所述两个或更多个电绝缘衬底；
将一个或多个管芯耦接到所述两个或更多个电绝缘衬底中的每一个的所述第一侧；和
包封所述一个或多个管芯以及所述两个或更多个电绝缘衬底中的每一个；
其中所述衬底为刚性的；和
其中所述一个或多个管芯为高压管芯。
7.根据权利要求6所述的方法，其中所述电绝缘衬底的所述第二侧上的所述一条或多条迹线为暴露的。
8.根据权利要求6所述的方法，其中所述一条或多条迹线沿所述两个或更多个电绝缘衬底中的每一个的一个或多个边缘形成。
9.根据权利要求6所述的方法，还包括在所述电绝缘衬底的平坦表面中形成一个或多个通孔。
10.根据权利要求6所述的方法，还包括将一个或多个夹具或两个或更多个焊线中的一者耦接到所述一个或多个管芯和所述一条或多条迹线。
CN201911057318.2A 2018-11-28 2019-11-01 氮化镓设备的封装结构 Pending CN111244061A (zh)

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