CN1094850A - 制造半导体芯片凸块的方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 91
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- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 99
- 239000002184 metal Substances 0.000 claims abstract description 22
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- 238000005286 illumination Methods 0.000 claims description 4
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- 238000007747 plating Methods 0.000 description 6
- 239000004020 conductor Substances 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
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- 239000002253 acid Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
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- 238000012797 qualification Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
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Abstract
通过多次光刻工艺,为形成光致抗蚀剂图形,各
自的光致抗蚀剂溶液选用正性和/或者负性的溶液,
采用限定凸块形成区域的适当图形掩模,通过曝光形
成光致抗蚀剂图形,由此,在半导体芯片的金属阻挡
层上形成凸形。由于制造的凸块上部与其下部相等
或者小于下部,在TAB封装内引线焊接期间,各凸
块互相不会接触,即使由于产生的压力使凸块上部伸
延也不会互相接触。采用多次光刻工艺,形成限定凸
块区域的光致抗蚀剂图形,结果使凸块具有大的高宽
比率。
Description
本发明涉及一种制造密集安置半导体芯片凸块的方法。特别涉及一种制造下述半导体芯片凸块的方法,其中,在自动带焊(TAB)组装中的为焊接内部引线所需的半导体芯片凸块区域上,通过好几次光刻工艺,形成光致抗蚀剂层,以获得所需形状的半导体芯片凸块和以便在TAB工艺中在焊接导线框架内部引线期间改善可靠性。
在TAB封装中,作为导线框架和布线的金属图形,通常被配置在绝缘膜上。TAB与通过焊接导线进行封装的方法完全不同,它是一种表面组装技术,借助于由导电材料组成的凸块,把在绝缘膜上形成的金属图形焊接到半导体芯片的焊接区上,并且广泛地用在小尺寸的计算器,液晶显示器(LCDS)、计算机等方面。
把TAB封装研制成细长的TAB或者小型的TAB封装,以便实现小型化和减薄的目的。
图1是表示使用一般带状载体的一个TAB封装例子的平面图。
参考图1,如此形成用于TAB封装的带状载体10、以便附着在由聚酰亚胺,聚脂、聚脂砜、多对位(Polyparalic)酸等组成的底膜12上的金属层,经过光刻工艺处理后,形成内引线13和外引线14,而内引线13附带半导体芯片11。
通过打孔对底膜12的中心部位进行加工,形成器件开口15,以便露出内引线13的末端。形成狭缝16、以便露出外引线14的一个端面,用于电连接外部的脚针。
在内引线13的下端形成凸块(未表示),以便采用热压方法和半导体芯片11的电极针柱进行电连接。在TAB封装中,通过密封的树脂模制内引线13,半导体芯片11的凸块和上表面进行防护(未表示)。
与获得半导体器件高封装密度一道,趋势是在TAB封装中实现细间距,增加引线数量,使引线的间距和凸块的间距减小。
利用半导体芯片焊接区上面的光致抗蚀剂图形,通过电镀或者非电镀的方法,形成用于TAB封装的那样一种半导体芯片凸块,下面将详细叙述制造半导体芯片凸块的方法。
图2A和图2B是表示按照常规技术制造半导体芯片凸块方法的示意剖面图。
首先参考图2A,借助于布线图形制造工艺,在半导体基片21上面形成作为印刷导线的金属导线,用作焊接区域,而形成光致抗蚀剂图形22,厚度近似于20μm,以露出焊接区上面的金属阻挡层26。
为制作焊接区,在半导体基片21上面,连续地形成绝缘层23,金属导线24和钝化层25,露出焊接区中金属线24的预定部分,在金属导线24和钝化层25上面,形成金属阻挡层26。
另一方面,进行形成光致抗蚀剂图形的通用光刻工艺如下。由溶解在溶剂中的光敏材料,树脂等物质组成的光致抗蚀剂溶液,借助于旋转涂覆法,被均匀地涂在半导体基片上面,然后以低温进行适当的烘焙。然后,穿过图形掩模,选择地照射光,经过显影形成具有预定形状的光致抗蚀剂图形。此时,在显影工艺中,利用弱碱性显影剂,选择地除掉曝光的或者未曝光的图形掩模的部分,上述显影液是处于溶液状态,以四甲胺氢氧化物(TMAH)作为主要成分,由此形成光致抗蚀剂图形。
参考图2B,在半导体基片21上面形成的具有预定形状的光致抗蚀剂图形22,在由光致抗蚀剂图形22露出的金属阻挡层26上面形成具有预定高度的凸块27,然后除掉光致抗蚀剂图形22。
凸块27必须具有预定的高度,例如高于20μm,以便在TAB封装内引线的焊接期间,防止半导体基片21和内引线之间的相互接触。
然而,按照常规方法制造半导体芯片凸块的方法,利用借助于一次光刻工艺形成作为图形掩模的光致抗蚀剂图形,形成具有所需要求高度的凸块。由于,仅采用一次光刻工艺,抗蚀剂层的厚度不能大于20μm,该厚度才能透过光,从而防碍了超过某种程度的高宽比率(高度和直径的比率)的增大。
随着半导体芯片凸块增高,光致抗蚀剂的上部和下部直径之间的差别和光刻工艺的特性一起增大。凸块的下部直径比它的上部直径小,结果当把凸块焊接到内引线上时,使力集中到接触区上面,由此引起焊接区的破裂。
此外,为达到半导体器件的高密度封装要减小凸块之间的间距,凸块的上部直径在内引线的小间距情况下,受到很大限制,当内引线和凸块焊接时,会使凸块的上部伸延,以致造成凸块和相邻凸块相互接触。
因为除掉一次光刻抗蚀剂图形的过程,特别是凹进部分不能完全除去凸块下部上的抗蚀剂图形,所以,必须接着进行除去残留光致抗蚀剂图形的工艺。
此外,如果凸块上表面的周围高于它的中心部分,它和内引线的接触会失效。为防止上述情况发生,可以形成一种蘑菇型凸块,而且它具有一个高于抗蚀剂图形的凸块。因此,可以防止和内引线的接触失效,但是可能产生焊接区的破裂,或者使凸块之间相互接触。
因此,本发明的目的是提供一种半导体芯片凸块的制造方法,通过任意调整凸块的形状和高宽比率,在内引线的焊接过程中能够防止焊接区的破裂、相邻凸块之间的相互接触和光致抗蚀剂图形的不完全去除。
本发明的另一个目的是提供一种能实现小间距的半导体芯片凸块的制造方法。
为了实现本发明的上述目的,利用掩模,通过形成具有预定类型的光致抗蚀剂图形,露出半导体基片的焊接区上面的金属阻挡层,制造具有预定形状的半导体芯片凸块的方法,包括下述步骤:
为了在半导体基片焊接区上面限定凸块形成区,在半导体基片的整个表面,涂覆性第1和第2次光致抗蚀剂溶液(光刻胶);
至少用2倍预定的能量,对正性的第1和第2次光致蚀剂层进行曝光;
通过显影第1和第2光致抗蚀剂层、形成光致抗蚀剂层,暴露出金属阻挡层;
借助于电镀或非电镀的方法,在由光致抗蚀剂图形限定的凸块形成区上面,形成具有预定图形的半导体芯片凸块;
在形成半导体凸块后,去掉光致抗蚀剂图形。
为了达到本发明另一个目的,利用掩模通过形成具有预定类型的光致抗蚀剂图形,露出半导体基片的焊接区上面的金属阻挡层,制造具有预定形状的半导体芯片凸块的方法,包括下述步骤:
用旋涂法在半导体的整个表面上面涂覆正性第1层光致抗蚀剂溶液,用于限定半导体基片焊接区上面的凸块形成区,再把光照射到第1图形掩模上面,用预定的能量进行曝光;
用旋涂法,在曝过光的正性第一层光致抗蚀剂溶液(层)的上面,涂覆负性第2光致抗蚀剂溶液,通过把光照射到与第1图形掩模形状相反的第2图形掩模上面,用预定的能量对第2光致抗蚀剂溶液(层)进行曝光;
通过对曝过光的第1光致抗蚀剂溶液(层)显影,形成光致抗蚀剂图形,以露出金属阻挡层和负性第2光致抗蚀剂层;
借助于电镀或者非电镀方法,在由光致抗蚀剂图形限定的凸块形成区域上形成具有预定形状的半导体芯片凸块;
在形成半导体芯片凸块以后,除掉光致抗蚀剂图形。
为了达到本发明另一目的,借助于光刻工艺,利用掩模通过形成具有预定类型的光致抗蚀剂图形,露出半导体基片焊接区上面的金属阻挡层制造具有预定图形的半导体芯片凸块的方法,包括下述步骤:
采用旋涂法,在半导体基片的整个表面上面,涂覆正性第1和第2光致抗蚀剂溶液,用于限定半导体基片焊接区上面的凸块形成区;
把光照射到具有相同形状的第1和第2图形掩模上,用预定的能量使第1和第2光致抗蚀剂层曝光;
通过对曝过光的正性第1和第2光致抗蚀剂层显影,形成在其上部伸出的光致抗蚀剂图形,露出金属阻挡层;
借助于电镀或者非电镀的方法,在由光致抗蚀剂图形限定的凸块形成区上面,形成具有预定形状的半导体芯片凸块;
在形成半导体芯片凸块后,去掉光致抗蚀剂图形。
通过参考附图详细地叙述最佳实施例,本发明的上述目的和优点将变得更加明显。
图1是表示使用通用的带状载体的一个TAB封装例子的平面图;
图2A和2B是表示按照常规技术制造半导体芯片凸块的简略剖面图;
图3A到3D是详细地表示按照本发明制造半导体芯片凸块方法的一个实施例的剖面图;
图4A到4D是详细地表示按照本发明制造半导体芯片凸块方法另一个实施例的剖面图;
图5是表示按照本发明制造半导体芯片凸块的又一实施例的剖面图;
图6是表示按照图5的方法制造的半导体芯片凸块的剖面图。
按照图3A到3D所示的一个实施例,制造半导体芯片凸块方法的要旨是通过二次光刻工艺,形成抗蚀剂图形。
参看图3A,借助于旋涂法,在半导体基片31焊接区的整个表面上面涂覆第1正性抗蚀剂溶液,限定在其上形成的半导体芯片凸块的区域,由此,在它的整个结构上面对第1抗蚀剂层进行曝光。
在半导体基片31上面焊接区有一个连续叠加的绝缘层33、金属线34和钝化层35的结构,还包括形成由钝化层35露出的金属线上面的阻挡层36。
参看3B,用旋涂法,涂覆正性的第2抗蚀剂溶液,在第1抗蚀剂层32上面,形成具有预定厚度的第2抗蚀剂层37,然后利用图形掩模38,施加预定的能量,对于金属阻挡层上面露出的第1抗蚀剂层32和第2抗蚀剂层37进行曝光。
参看图3C,通过显影工艺,显影第1和第2光致抗蚀剂层32和37,形成抗蚀剂图形39,露出金属阻挡层36。
此时,光致抗蚀剂图形39的整个高度要与待形成的凸块高度,例如10μm以上,相同或者稍高。除了高度之外,因为第1层光致抗蚀剂层32被曝光2次,除掉该层比除掉只曝光一次的第2层光致抗蚀剂层37较快,所以在显影工艺过程中,光致抗蚀剂图形39的底部开口比它的上部开口大。
参看图3D,借助于电镀和非电镀的方法,具有上述结构的半导体基片31,经过电镀或者非电镀的处理,在金属阻挡层上面形成凸块40,然后去掉光致抗蚀剂图形39。因此,要注意到,按照第1实施例形成的凸块40具有壶状形状,底部较宽。
图4A到图4D是表示按照本发明制造半导体芯片凸块方法的另一个实施例的剖面图,其中,与图3A到3D表示的各部分相同的部分,用相同的标号表示。
参考图4A,通过旋涂正性胶,在半导体基片31焊接区的整个表面上面,涂覆第1抗蚀剂溶液,以便形成第1抗蚀剂层41,来限定在其上待形成半导体芯片凸块的区域,再用第1图形掩模42,照射100到2000mJ/cm2的预定能量的光,使金属阻挡层36上的第1抗蚀剂层41曝光。
参考图4B,用旋涂法,在第1抗蚀剂层41上面涂负性第2层抗蚀剂溶液,形成预定的厚度的第2抗蚀剂层43,然后,采用第2图形掩模44,以预定的能量,例如,100到2000mJ/cm2,进行第2次曝光,而第2图形掩模44是与第1图形掩模42相反。此时,第1层光致抗蚀剂层41的第1次已曝光部分被保护起来。而负性的第2光致抗蚀剂层43的较高感光性起作用。
参考图4C,把半导体基片31的焊接区上面形成的第1和第2光致抗蚀剂层41和43显影而除掉,结果形成光致抗蚀剂图形45。此时,光致抗蚀剂图形45的高度是大于10μm。
参考图4D,上述半导体基片31,用电镀或者非电镀的方法,在金属阻挡层36上面形成凸块46,然后,去掉光致抗蚀剂图形45。凸块46的高度等同于或小于光致抗蚀剂图形45,按照本发明第2实施例的半导体芯片凸块46为柱状。
图5是表示按照本发明制造半导体芯片凸块方法的又一实施例的略图,其中,由于制造工艺是与上述方法相同,省略相同部分以便简略地表示第3实施例。
参考图5,与已经叙述的方法不同,第1和第2光致抗蚀剂溶液47和48都是正性的溶液。而且具有用于第1次和第2次曝光工艺形成凸块部分的第1图形掩模49是这样开孔,它们的形状决定于第1和第2曝光的掩模,使第1光致抗蚀剂层的开孔高宽比小于第2光致抗蚀剂层的开孔的高宽比为10-90%。
形成对应于凸块区的掩蔽区,以便透光或遮光,这取决于第1和第2光致抗蚀剂层47和48是正性还是负性。
图6是表示按照有关图5所述方法制造的半导体芯片凸块的剖面图。
参考图6,在半导体基片31的金属阻挡层36上面形成的半导体芯片凸块,其形状象蘑菇形。形成的凸块51比由多次光刻工艺形成的光致抗蚀剂图形高,其中凸块51比常规的凸块高,而且凸块51的上部是凸出的,可防止在焊接内引线时产生接触故障。
不仅能进行2次光刻工艺,而且可以进行多次光刻工艺,以便形成光致抗蚀剂图形,通过正确配合光致抗蚀剂溶液的厚度和图形掩模,而可随意调整凸块的形状。
按照如上所述的本发明,采用多次光刻工艺,兼用正性和负性溶液,选择使用各自光致抗蚀剂溶液,还采用适合上述光刻工艺的图形掩模,就能形成用于确定形成凸块区域的光致抗蚀剂图形。
结果,凸块上部的直径小于或者等同于它下部的直径,以防止凸块之间相互接触,即使在TAB封装内引线焊接时由于加压使凸块上部延伸也能防止各凸块互相接触。
此外,由几次光刻工艺形成限定凸块的光致抗蚀剂图形,以便形成有高宽比的凸块,由此防止内引线与半导体芯片表面的接触。在形成凸块后,还很容易去掉光致抗蚀剂图形,以便简化所有的工艺。
参考具体的实施例,具体地表示和叙述了本发明,其中,通过多次光刻工艺,由光致抗蚀剂图形形成了半导体芯片凸块,采用正确配合的光致抗蚀剂溶液的厚度和图形掩模能任意调整凸块的形状。本领域的技术人员应该了解,在不偏离附加权利要求书限定本发明的精神和范围的情况下,可以进行形式上和细节上的各种变化。
Claims (8)
1、一种在半导体基片焊接区上面,制造有预定形状的半导体芯片凸块的方法,包括下述步骤:
在所述半导体基片的整个表面上涂覆第1和第2光致抗蚀剂溶液,用于限定所述半导体基片焊接区上的凸块形成区;
用预定的能量,至少两次,给用所述第1和第2光致抗蚀剂溶液形成的所述正性第1和第2光致抗蚀剂层曝光。
通过显影所述曝光的第1和第2光致抗蚀剂层,形成所述的光致抗蚀剂图形;
在所述的光致抗蚀剂图形限定的所述凸块形成区上,形成具有预定图形的所述半导体芯片凸块;以及
在形成所述半导体芯片凸块后,去掉所述光致抗蚀剂图形。
2、根据权利要求1的一种制造半导体芯片凸块的方法,其特征在于,所述光致抗蚀剂图形的厚度大于10μm。
3、根据权利要求1的一种制造半导体芯片凸块的方法,其特征在于,所述半导体芯片凸块上部直径是等同于或者小于它的下部直径。
4、根据权利要求1的一种制造半导体芯片凸块的方法,其特征在于,对所述的第1光致抗蚀剂层进行全面曝光,而利用具有预定图形的图形掩模,对于所述的第2光致抗蚀剂层,在其形成所述半导体芯片凸块的区域,进行曝光。
5、根据权利要求4的一种制造半导体芯片凸块的方法,其特征在于用正性胶涂第1和第2光致抗蚀剂层。
6、一种在半导体基片焊接区上,制造具有预定形状的半导体芯片凸块的方法,包括下列步骤:
在所述半导体基片的整个表面上面,涂覆正性第1光致抗蚀剂溶液,用于形成第1光致抗蚀剂层,以限定所述半导体基片焊接区上的凸块形成区,把光照射在第1图形掩模上面,用预定的能量对所述第1光致抗蚀剂层进行曝光;
在所述曝光的正性第1光致抗蚀剂溶液的上部,涂覆负性第2光致抗蚀剂溶液,通过把光照射在第2图形掩模上面,而该掩模具有与第1图形掩模的图形相反的图形,用预定的能量对所述的第2光致抗蚀剂层进行曝光;
通过对已曝光的所述正性第1光致抗蚀剂溶液显影,而形成光致抗蚀剂图形,以露出所述金属阻挡和负性第2光致抗蚀剂层;
在所述光致抗蚀剂图形限定的所述凸块形成区上,形成具有预定形状的所述半导体芯片凸块;以及
在形成所述半导体芯片凸块后,去掉所述光致抗蚀剂图形。
7、一种在半导体基片焊接区上制造具有预定形状的半导体芯片凸块的方法,包括下列步骤:
在所述半导体基片的整个表面上涂覆正性第1和第2光致抗蚀剂溶液,用于限定所述半导体基片的所述焊接区上的凸块形成区;
把光照射到第1和第2掩模上,用预定能量对光致抗蚀剂层进行曝光;
通过显影已曝光的正性第1和第2光致抗蚀剂层,形成伸出到其上部的光致抗蚀剂层;
在由所述光致抗蚀剂图形限定的所述凸块形成区上,形成具有预定形状的所述半导体芯片凸块;以及
在形成所述半导体芯片凸块以后,除去所述光致抗蚀剂图形。
8、根据权利要求7的一种制造半导体芯片凸块的方法,其特征在于,用所述第1图形掩模,该掩模具有所述金属阻挡层上表面要露出用于形成所述的半导体芯片凸块的预定形状,进行所述第1曝光步骤,以形成第1光致抗蚀剂层;以及
用所述的第2图形掩模,该掩模曝光区域小于或者大于所述第1图形掩模曝光区域,进行所述的第2曝光步骤,以形成第2光致抗蚀剂层。
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KR940010510B1 (ko) * | 1988-11-21 | 1994-10-24 | 세이꼬 엡슨 가부시끼가이샤 | 반도체 장치 제조 방법 |
JPH02246218A (ja) * | 1989-03-20 | 1990-10-02 | Fujitsu Ltd | 半導体装置の製造方法 |
GB8910961D0 (en) * | 1989-05-12 | 1989-06-28 | Am Int | Method of forming a pattern on a surface |
JPH03119550A (ja) * | 1989-10-02 | 1991-05-21 | Toshiba Corp | 磁気記録再生装置 |
US5091288A (en) * | 1989-10-27 | 1992-02-25 | Rockwell International Corporation | Method of forming detector array contact bumps for improved lift off of excess metal |
JPH0432235A (ja) * | 1990-05-28 | 1992-02-04 | Fujitsu Ltd | バンプ電極の形成方法 |
KR940001149B1 (ko) * | 1991-04-16 | 1994-02-14 | 삼성전자 주식회사 | 반도체 장치의 칩 본딩 방법 |
-
1993
- 1993-02-08 KR KR1019930001663A patent/KR960016007B1/ko not_active IP Right Cessation
-
1994
- 1994-02-08 DE DE4403916A patent/DE4403916C2/de not_active Expired - Lifetime
- 1994-02-08 JP JP6014337A patent/JP2803987B2/ja not_active Expired - Fee Related
- 1994-02-08 US US08/194,361 patent/US5496770A/en not_active Expired - Lifetime
- 1994-02-08 CN CN94102787A patent/CN1061470C/zh not_active Expired - Lifetime
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102022511A (zh) * | 2009-09-09 | 2011-04-20 | 吴志强 | 一种复合型双泵轮液力变矩器 |
CN102022511B (zh) * | 2009-09-09 | 2014-07-30 | 吴志强 | 一种复合型双泵轮液力变矩器 |
CN102376638A (zh) * | 2010-08-12 | 2012-03-14 | 台湾积体电路制造股份有限公司 | 集成电路元件的形成方法 |
CN102376638B (zh) * | 2010-08-12 | 2013-12-25 | 台湾积体电路制造股份有限公司 | 集成电路元件的形成方法 |
CN108122782A (zh) * | 2016-11-29 | 2018-06-05 | 台湾积体电路制造股份有限公司 | 半导体结构的制造方法 |
CN108122782B (zh) * | 2016-11-29 | 2021-08-20 | 台湾积体电路制造股份有限公司 | 集成电路装置与半导体结构的制造方法 |
US11114395B2 (en) | 2016-11-29 | 2021-09-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Post passivation interconnect |
US11817404B2 (en) | 2016-11-29 | 2023-11-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Post passivation interconnect |
Also Published As
Publication number | Publication date |
---|---|
KR960016007B1 (ko) | 1996-11-25 |
DE4403916C2 (de) | 2002-05-29 |
CN1061470C (zh) | 2001-01-31 |
US5496770A (en) | 1996-03-05 |
JP2803987B2 (ja) | 1998-09-24 |
KR940020508A (ko) | 1994-09-16 |
JPH06252151A (ja) | 1994-09-09 |
DE4403916A1 (de) | 1994-09-01 |
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