CN102376638B - 集成电路元件的形成方法 - Google Patents

集成电路元件的形成方法 Download PDF

Info

Publication number
CN102376638B
CN102376638B CN2010106039702A CN201010603970A CN102376638B CN 102376638 B CN102376638 B CN 102376638B CN 2010106039702 A CN2010106039702 A CN 2010106039702A CN 201010603970 A CN201010603970 A CN 201010603970A CN 102376638 B CN102376638 B CN 102376638B
Authority
CN
China
Prior art keywords
photoresist film
opening
layer
photoresist
projection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2010106039702A
Other languages
English (en)
Other versions
CN102376638A (zh
Inventor
郭正铮
陈承先
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN102376638A publication Critical patent/CN102376638A/zh
Application granted granted Critical
Publication of CN102376638B publication Critical patent/CN102376638B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11472—Profile of the lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11474—Multilayer masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H01L2224/11902—Multiple masking steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01038—Strontium [Sr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0104—Zirconium [Zr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01061—Promethium [Pm]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Abstract

本发明公开了一种集成电路元件的形成方法，根据一实施例提供一种具有基脚形状的铜柱工艺，在凸块下冶金层上采用两道不同光敏性及厚度的光致抗蚀剂膜。在曝光显影工艺后，在第一光致抗蚀剂膜中形成具有实质上垂直的侧壁的第一开口，并在第二光致抗蚀剂层中形成具有倾斜侧壁的第二开口。第二开口的底部直径大于第二开口的顶部直径，且第二开口的底部直径大于第一开口的直径。接着形成导电层于第一开口及第二开口中，之后移除两道光致抗蚀剂膜。本发明在不需额外化学或等离子体工艺的情况下，即可轻易定义基脚形状的尺寸，大幅节省制造成本。

Description

集成电路元件的形成方法
技术领域
本发明涉及一种制造集成电路元件的方法，尤其涉及一种制造半导体集成电路中凸块结构的方法。
背景技术
现有的集成电路由横向排列的百万个有源元件如晶体管及电容所组成。这些元件在初步工艺中彼此绝缘，但在后段工艺中将以内连线连接元件以形成功能电路。一般的内连线结构包含横向内连线如金属线路，与垂直内连线如通孔与接点。现有的集成电路其效能与密度的上限取决于内连线。在内连线结构的顶部上方，每一芯片表面上各自有对应的接合垫。经由接合垫，芯片可电性连接至封装基板或其他裸片。接合垫可应用于打线接合或倒装芯片接合。在倒装芯片封装中，凸块可在封装结构的导线架或基板，与芯片的输出/输入焊盘之间形成电性接触。上述凸块结构除了凸块本身，还具有凸块与输出/输入焊盘之间的凸块下冶金层(UBM)。UBM通常含有粘着层、阻挡层、与润湿层依序形成于输入/输出焊盘上。凸块的分类可依材质分为焊料凸块、金凸块、铜柱凸块、或混合金属凸块。近来发展的铜柱凸块技术中，采用铜柱凸块而非焊料凸块将电子构件连接至基板。铜柱凸块的间距较小，其短路桥接的可能性较低，可降低电路的电容负载并提高电子构件的操作频率。
在采用铜柱的完全倒装芯片封装中，不论是测试或组装后使用均发现热应力问题如超低介电常数(ELK)的介电材料的分层，或底填材料、保护层、及预焊材料的碎裂。上述材料分层会碎裂的原因为铜柱周围的上述材料，在热循环时会产生实质上的热应力。当集成电路元件的尺寸持续缩减，终端与铜柱之间的间距亦随之缩减。如此一来，采用铜柱的相关热应力问题必然增加。在公知采用铜柱的集成电路倒装芯片封装中，先以单一光致抗蚀剂层如干膜或湿膜搭配光刻工艺在UBM层上定义一开口，再以电镀法沉积铜层以形成具有垂直侧壁或倾斜侧壁的铜柱。然而，公知方法难以增加铜柱的底部尺寸，且无法将应力分摊至UBM层与保护层之间的界面。综上所述，目前亟需一种改良的集成电路倒装芯片连线如铜柱以解决热应力的问题。
发明内容
为了解决上述问题，本发明一实施例提供一种集成电路元件的形成方法，包括形成凸块下冶金层于半导体基板上；形成光致抗蚀剂结构于凸块下冶金层上，其中光致抗蚀剂结构包括第一光致抗蚀剂膜与位于第一光致抗蚀剂膜上的第二光致抗蚀剂膜，且第一光致抗蚀剂膜的光敏性不同于第二光致抗蚀剂膜的光敏性；形成开口于光致抗蚀剂结构中以露出部分的凸块下冶金层，其中开口包括第一开口位于第一光致抗蚀剂膜中及第二开口位于第二光致抗蚀剂膜中，且第一开口的底部直径大于第一开口的顶部直径；形成导电层于光致抗蚀剂结构的开口中，且导电层电性连接至露出的部分凸块下冶金层；以及移除光致抗蚀剂结构，其中导电层形成导电柱。
本发明又一实施例提供一种集成电路元件的形成方法，包括形成凸块下冶金层于半导体基板上；形成第一光致抗蚀剂膜于凸块下冶金层上，第一光致抗蚀剂膜具有第一厚度与第一光敏性；形成第二光致抗蚀剂膜于第一光致抗蚀剂膜上，且第二光致抗蚀剂膜具有第二厚度与第二光敏性；其中第二光敏性大于第一光敏性，且第二厚度大于第一厚度；进行曝光工艺至第二光致抗蚀剂膜与第一光致抗蚀剂膜；移除未曝光的部分第二光致抗蚀剂膜以形成第一开口；移除未曝光的部分第一光致抗蚀剂膜以露出部分凸块下冶金层，形成第二开口于第一开口下，以及形成第三开口于第二开口下；其中第一光致抗蚀剂膜围绕第二开口，且第二开口的底部直径大于第二开口的顶部直径；形成铜层于第一开口、第二开口、与第三开口中以电性连接至露出的部分凸块下冶金层；以及移除第二光致抗蚀剂膜与第一光致抗蚀剂膜，其中铜层形成铜柱。
本发明再一实施例提供一种集成电路元件的形成方法，包括形成凸块下冶金层于半导体基板上；形成第一光致抗蚀剂膜于凸块下冶金层上，第一光致抗蚀剂膜具有第一厚度与第一光敏性；形成第二光致抗蚀剂膜于第一光致抗蚀剂膜上，且第二光致抗蚀剂膜具有第二厚度与第二光敏性；其中第一光敏性大于第二光敏性，且第二厚度大于第一厚度；进行曝光工艺至第二光致抗蚀剂膜与第一光致抗蚀剂膜；移除曝光的部分第二光致抗蚀剂膜以形成第一开口；移除曝光的部分第一光致抗蚀剂膜以露出部分凸块下冶金层，形成第二开口于第一开口下，以及形成第三开口于第二开口下；其中第一光致抗蚀剂膜围绕第二开口，且第二开口的底部直径大于第二开口的顶部直径；形成铜层于第一开口、第二开口、与第三开口中以电性连接至露出的部分凸块下冶金层；以及移除第二光致抗蚀剂膜与第一光致抗蚀剂膜，其中铜层形成铜柱。
本发明上述方法的光刻工艺中，形成不同光敏性的正光致抗蚀剂膜的堆叠结构于UBM层上。在较低光致抗蚀剂膜中可形成鸟嘴开口，这将使后续形成的铜柱具有基脚形状。此方法在不需额外化学或等离子体工艺的情况下，即可轻易定义基脚形状的尺寸，这将大幅节省制造成本。
附图说明
图1A至图1G为本发明一实施例中，采用负光致抗蚀剂形成集成电路中铜柱的工艺剖视图；以及
图2A-图2D为本发明一实施例中，采用正光致抗蚀剂形成集成电路中铜柱的工艺剖视图
上述附图中的附图标记说明如下：
保留的第一电阻膜侧壁与凸块下冶金层之间的夹角；D1b～第一开口其较高部分的底部直径；D1t～第一开口其较高部分的顶部直径；D2～第二开口的直径；H1～铜层高度；W1～铜层的上层部分的宽度；W2～铜层的中间部分的顶宽；W3～铜层的中间部分的底宽；10～半导体基板；12～导电区；14～保护层；16～高分子层；18～凸块下冶金层；18”～图案化的凸块下冶金层；20、40～光致抗蚀剂结构；20a、40a～开口；22、42～第一光致抗蚀剂膜；22a、42a～第一开口；22a1、42a1～第一开口的较低部分；22a2、42a2～第一开口的较高部分；22b、42b～鸟嘴开口；22s～保留的第一电阻膜侧壁表面；24、44～第二光致抗蚀剂膜；24a、44a～第二开口；24s、44s～第二开口的侧壁；26、36～光掩膜；28～铜层；28a～铜层的上层部分；28b～铜层的中间部分；28c～铜层的底层部分；28s～铜层的中间部分的侧壁；28v～铜层的上层部分的侧壁；30～盖层；32～焊料层。
具体实施方式
下述说明将揭示形成铜柱的方法，其基脚形状可应用于倒装芯片组装、晶片等级的芯片尺寸封装(WLCPS)、三维集成电路堆叠、及/或任何高级的封装技术领域。图示将搭配标号以说明实施例。图示及对应说明尽可能采用相同标号标示相同或类似的部分。图示中结构的形状及厚度可能会夸大以突显结构特点。下列说明将直接针对装置的构成要素或操作要素。可以理解的是，本领域普通技术人员可自行调整或变化未特别显示或叙述的要素。此外，当某层被在另一层上时，指的可能是直接位于另一层上或两者间隔有其他层。
在下述说明中，“一实施例”指的是特定特征、结构、或至少一实施例中包含的实施例所连结的结构。因此，不同段落中的“一实施例”指的不一定是同一实施例。此外，一或多个实施例中的特定特征、结构、或特点可由任何合适态样组合。可以理解的是，下述图示并非依比例绘示，仅用以方便说明而已。
图1A至图1G为本发明一实施例中，采用负光致抗蚀剂形成集成电路中铜柱的工艺剖视图。如图1所示，半导体基板10可用以形成凸块以制备集成电路元件，且集成电路可形成于半导体基板10中及/或其上。半导体基板10的定义为半导体材料，包括但不限定于基体硅、半导体晶片、绝缘层上硅(SOI)基板、或硅锗基板。其他适用于半导体基板10的半导体材料可采用III族、IV族、或V族元素。半导体基板10可还包含多个绝缘结构(未图示)，如浅沟槽绝缘(STI)结构或区域氧化硅(LOCOS)结构。绝缘结构可绝缘多个微电子元件(未图示)。上述形成于半导体基板10中的微电子元件可为金属氧化物半导体场效晶体管(MOSFET)、互补式金属氧化物半导体(CMOS)晶体管、双极性结晶体管(BJT)、高电压晶体管、高频晶体管、p沟道及/或n沟道场效晶体管、或其他晶体管，电阻，二极体，电容，电感，熔丝，或其他合适元件。不同的微电子元件的形成方法可包含不同工艺如沉积、蚀刻、注入、光刻、回火、或他合适工艺。微电子元件可借由内连线形成集成电路元件如逻辑元件、存储元件(例如静态随机存取存储器，SRAM)、射频(RF)元件、输入/输出(I/O)元件、单芯片系统(SoC)元件、上述的组合、或其他合适型态的元件。
半导体基板10可具有层间介电层与金属结构形成于集成电路上。层间介电层可为低介电常数的介电材料、未掺杂的硅酸盐玻璃(USG)、氮化硅、氮氧化硅、或其他一般常用材料。低介电常数的介电材料其介电常数(k)可小于约3.9，或小于约2.8。金属结构中的金属线路可由铜或铜合金组成。金属结构与层间介电层的形成方法为本领域普通技术人员所熟知，在此不赘述。
导电区12为形成于最顶层的层间介电层上的金属层。导电区12为导电线路的一部分，其露出的表面可视情况进行平坦化工艺如化学机械研磨(CMP)。适用于导电区12的材料可为但不限定于铜、铝、铜合金、或其他现有的导电材料。在某些实施例中，导电区12作为焊盘区以用于接合工艺，可将每一芯片中的集成电路连接至外部结构。在某些实施例中，导电区12为再布线层，亦称为后保护内连线(PPI)线路。
保护层14形成于半导体基板10上。图案化保护层14可形成开口露出部分的导电区12，以利后续工艺形成凸块。在某些实施例中，保护层14的组成可为未掺杂硅酸盐玻璃(USG)、氮化硅、氮氧化硅、氧化硅、或上述的组合。在某些实施例中，保护层14的组成为高分子层如环氧树脂、聚酰亚胺、双苯并环丁烷(BCB)、聚苯并恶唑(PBO)、或其他较软的有机介电材料。
高分子层16形成于保护层14上。图案化高分子层16可形成开口露出部分的导电区12，以利后续工艺形成凸块。高分子层16中的开口可小于、等于、或大于保护层14中的开口。在某些实施例中，高分子层16的组成为高分子如环氧树脂、聚酰亚胺、双苯并环丁烷(BCB)、聚苯并恶唑(PBO)、或其他较软的有机介电材料。在某些实施例中，高分子层16为聚酰亚胺层。在某些实施例中，高分子层16为聚苯并恶唑(PBO)层。
图1A亦显示凸块下冶金(UBM)层18形成于半导体基板10上。UBM层18形成于导电区12的露出部分上，并延伸至高分子层16上。在某些实施例中，UBM层16包含作为扩散阻挡层或粘着层的第一层，其组成可为钛、钽、氮化钛、氮化钽、或类似物，且其形成方法可为物理气相沉积法(PVD)或溅镀法。第一层的沉积厚度介于约
Figure BSA00000397786500051
至之间。在某些实施例中，UBM层16包含作为晶种层的第二层，其组成可为铜或铜合金，且其形成方法可为PVD或溅镀法。第二层的沉积厚度介于约
Figure BSA00000397786500053
至之间。
如图1B所示，光致抗蚀剂结构20形成于UBM层18上。光致抗蚀剂结构20为堆叠结构，包含至少两层不同光敏性的光致抗蚀剂膜。每一光致抗蚀剂膜可为正光致抗蚀剂膜或负光致抗蚀剂膜，取决于这些光致抗蚀剂膜在曝光时的化学变化性。若光致抗蚀剂膜在曝光后具有较佳的化学稳定性，则此光致抗蚀剂膜为负光致抗蚀剂膜。若采用负光致抗蚀剂，则未曝光的负光致抗蚀剂部分将被显影移除。若光致抗蚀剂膜在曝光后具有较差的化学稳定性，则此光致抗蚀剂膜为正光致抗蚀剂膜。若采用正光致抗蚀剂，则曝光的正光致抗蚀剂部分将被显影移除。在一实施例中，光致抗蚀剂结构20包含第一光致抗蚀剂膜22，与位于第一光致抗蚀剂膜22上的第二光致抗蚀剂膜24。第一光致抗蚀剂膜22为负光致抗蚀剂，具有第一光敏性及第一厚度。第二光致抗蚀剂膜24为负光致抗蚀剂，具有第二光敏性及第二厚度。第二光敏性比第一光敏性大，且第一厚度小于第二厚度。举例来说，第一光致抗蚀剂膜22的第一厚度约介于3μm至15μm之间，而第二光致抗蚀剂膜24的第二厚度约介于40μm至85μm之间。
接着如图1C所示，进行单一曝光工艺以图案化光致抗蚀剂结构20，其曝光光源可为深紫外线(DUV)、中紫外线(MUV)、或X光射线。在其他实施例中，光致抗蚀剂结构20的曝光源为电子束光刻的能量化电子。搭配光掩膜26，光子或电子能量可使光致抗蚀剂结构20的曝光部分的组成产生化学变化，例如交联、断链、或移除支链等等。光致抗蚀剂可进行预烘烤或后烘烤工艺，这将最大化光致抗蚀剂中曝光部分与未曝光部分之间的化学性质变化差异。由于第一光致抗蚀剂膜22与第二光致抗蚀剂膜24为负光致抗蚀剂，光致抗蚀剂结构20其未曝光的部分将被显影移除以露出部分的UBM层18。
上述光刻工艺将形成开口20a于光致抗蚀剂结构20中。开口20a包含借由移除未曝光的第一光致抗蚀剂膜22所形成的第一开口22a，以及借由移除未曝光的第二光致抗蚀剂膜24所形成的第二开口24a。第二开口24a具有实质上垂直的侧壁24s。在第一开口22a中，还包含被UBM层18露出的部分所包围的较低部分22a1，以及被第一光致抗蚀剂膜22保留的部分所包围的较高部分22a2。总体来说，较高部分22a2其底部直径D1b大于顶部直径D1t，且第一电阻膜22保留的部分其倾斜的侧壁表面22s与UBM层18的夹角θ小于90度。如此一来，鸟嘴开口22b将形成于第一光致抗蚀剂膜22与UBM层18的界面之间。此外，第一开口22a其较高部分22a2的底部直径比第二开口24a的直径D2宽。在某些实施例中，直径D1b与直径D2的差距大于约3μm。在后续工艺中，导电材料将填入开口中，即完成具有基脚形状的导电柱。
如图1D所示，将具有焊料润湿性的导电材料形成于开口22a及24a中。在某些实施例中，将铜层28填入第一开22a以接触其下的UBM层18。沉积铜层28的作法可连续性地将其填入第二开口24a直到预定的高度。在本揭示中，所谓的铜层实质上包含纯元素铜、含有无可避免的杂质的铜、或次要成份为钽、铟、锡、锌、锰、铬、钛、锗、锶、铂、镁、铝、或锆的铜合金。铜层28的形成方法可为溅镀、印刷、电镀、无电电镀、或化学气相沉积法(CVD)。举例来说，电化学电镀法(ECP)可用以形成铜层28。在某些实施例中，ECP工艺的起始沉积速率较慢以达到“填隙”效果，这可帮助电镀铜层填入鸟嘴开口22b，进而使铜层28的基脚形状能贴近UBM层18。在一实施例中，铜层28的高度H1定义为最低表面至最高表面的距离，可大于25μm。在某些实施例中，铜层28的高度H1大于40μm。举例来说，铜层28的高度H1介于约40μm至50μm之间，或介于40μm至70μm之间，但铜层28的高度H1可大于或小于上述范围。在某些实施例中，第二开口24a实质上填入铜层28，且铜层28的上表面低于第二光致抗蚀剂膜24的上表面。在其他实施例中(未图示)，可控制铜层的沉积工艺以将其填入开口24a，并使铜层的上表面高于或等高于第二光致抗蚀剂膜24的上表面。
接着如图1E所示，盖层30与焊料层32成功地形成于第二开口24a中的铜层28其上表面上。在某些实施例中，盖层30可作为扩散阻挡层，以避免铜柱中的铜扩散至接合材料如焊料合金。上述接合材料用以接合半导体基板10至外部结构。避免铜扩散可增加封装的接合强度与可信度。盖层30包含下列材料中至少一者：镍、锡、锡铅、金、银、钯、铟、镍钯金、镍金、其他类似材料、或电镀法沉积的合金。盖层30的厚度约介于1μm至10μm之间。在某些实施例中，盖层30为多层结构，其中的每一层包含下列材料中至少一者：镍、金、钯、镍为主合金、金为主合金、或钯为主合金。在某些实施例中，盖层30为镍膜或镍合金膜，其形成方法可为电极电镀工艺、无电电镀工艺、或含浸电镀工艺。
焊料层32可为锡、锡银、锡铅、铜的重量％小于0.3％的锡金铜、锡银锌、锡锌、锡铋铟、锡铟、锡金、锡铅、锡铜、锡锌铟、锡银锡、或类似物，其形成方法可为电镀工艺。在某些实施例中，焊料层32为无铅焊料层。在无铅焊料系统中，焊料层32为银含量小于3.0重量％的锡银。在某些实施例中，无铅焊料层为银含量小于2.5重量％的锡银。
接着如图1F所示，移除光致抗蚀剂结构20以露出UBM层18。铜层28形成铜柱。接着移除露出的UBM层18。如图1G所示，以铜柱(铜层28)作为遮罩，可移除露出的部分UBM层18并露出其下方的高分子层16。
如图1G所示，完成的凸块结构包含图案化的UBM层18”、铜层28、盖层30、与焊料层32。铜层28具有剖面为柱状的上层部分28a、剖面为梯形的中间部分28b、以及被图案化UBM层18”包围的底层部分28c。上层部分28a具有宽度W1及垂直侧壁28v。中间部分28b具有顶宽W2、底宽W3、及倾斜侧壁28s。中间部分28b的底宽W3大于顶宽W2，且底宽W3亦大于上层部分28a的宽度W1。上层部分28a的宽度W1实质上可等同于中间部分28b的底宽W2。在某些实施例中，中间部分28b的底宽W3比顶宽W2大了约3μm。侧壁28s自较宽的上部朝较窄的下部倾斜直到接触图案化UBM层18”，两者的夹角小于90度。上述倾斜的侧壁28s使柱状结构其垂直的侧壁28v底部具有基脚形状。此外，铜层28覆盖图案化UBM层18”的部分较宽，可保留较多的UBM材料不致被移除。在复杂的集成电路构件中，上述实施例中的铜柱中不同材料如ELK、UBM、底填材料、预焊料、或焊料凸块上的热应力，低于公知技艺中单纯柱状铜柱中上述材料上的热应力。
接着进行再流动工艺以形成再流动的焊料层。接着切割半导体基板10，再以焊球或铜凸块将其固定于封装基板或另一裸片上的焊盘层上，至此完成封装结构。
上述方法的光刻工艺中，形成不同光敏性的负光致抗蚀剂膜的堆叠结构于UBM层上。在较低光致抗蚀剂膜中可形成鸟嘴开口，这将使后续形成的铜柱具有基脚形状。此方法在不需额外化学或等离子体工艺的情况下，即可轻易定义基脚形状的尺寸，这将大幅节省制造成本。
图2A-图2D为本发明一实施例中，采用正光致抗蚀剂形成集成电路中铜柱的工艺剖视图。下述说明将省略与图1A-图1G类似或相同的部分。
如图2A所示，形成光致抗蚀剂结构40于UBM层18上。光致抗蚀剂结构40为堆叠结构，包含至少两层不同光敏性的光致抗蚀剂膜。在一实施例中，光致抗蚀剂结构40包含第一光致抗蚀剂膜42，与位于第一光致抗蚀剂膜42上的第二光致抗蚀剂膜44。第一光致抗蚀剂膜42为正光致抗蚀剂，具有第一光敏性及第一厚度。第二光致抗蚀剂膜44为正负光致抗蚀剂，具有第二光敏性及第二厚度。第一光敏性比第二光敏性大，且第一厚度小于第二厚度。举例来说，第一光致抗蚀剂膜42的第一厚度约介于3μm至15μm之间，而第二光致抗蚀剂膜44的第二厚度约介于40μm至85μm之间。
接着如图2B所示，进行单一曝光工艺以图案化光致抗蚀剂结构40，其曝光光源可为DUV、MUV、或X光射线。在其他实施例中，光致抗蚀剂结构40的曝光源为电子束光刻的能量化电子。搭配光掩膜36，光子或电子能量可使光致抗蚀剂结构40的曝光部分的组成产生化学变化，例如交联、断链、或移除支链等等。光致抗蚀剂可进行预烘烤或后烘烤工艺，这将最大化光致抗蚀剂中曝光部分与未曝光部分之间的化学性质变化差异。由于第一光致抗蚀剂膜42与第二光致抗蚀剂膜44为正光致抗蚀剂，光致抗蚀剂结构40其曝光的部分将被显影移除。
上述光刻工艺将形成开口40a于光致抗蚀剂结构40中。开口40a包含借由移除曝光的第一光致抗蚀剂膜42所形成的第一开口42a，以及借由移除曝光的第二光致抗蚀剂膜44所形成的第二开口44a。在第一开口42a中，还包含被UBM层18露出的部分所包围的较低部分42a1，以及被第一光致抗蚀剂膜42保留的部分所包围的较高部分42a2。总体来说，较高部分42a2中，第一电阻膜42保留的部分其倾斜的侧壁表面42s与UBM层18的夹角θ小于90度。如此一来，鸟嘴开口42b将形成于第一光致抗蚀剂膜42与UBM层18的界面之间。此外，第一开口42a其较高部分42a2的底部直径D1b比第二开口44a的直径D2宽。在后续工艺中，导电材料将填入开口中，即完成具有基脚形状的导电柱。
如图2C所示，将铜层28填入开口42a及44a中后，接着形成盖层30与焊料层32。在某些实施例中，ECP工艺的起始沉积速率较慢以达到“填隙”效果，这可帮助电镀铜层填入鸟嘴开口42b，进而使铜层28的基脚形状能贴近UBM层18。
接着如图2D所示，移除光致抗蚀剂结构40以露出UBM层18。意UBM层18突出的铜层28即铜柱。接着蚀刻移除露出的UBM层18，露出其下方的高分子层16。之后进行再流动工艺以形成再流动的焊料层。接着切割半导体基板10，再以焊球或铜凸块将其固定于封装基板或另一裸片上的焊盘层上，至此完成封装结构。
上述方法的光刻工艺中，形成不同光敏性的正光致抗蚀剂膜的堆叠结构于UBM层上。在较低光致抗蚀剂膜中可形成鸟嘴开口，这将使后续形成的铜柱具有基脚形状。此方法在不需额外化学或等离子体工艺的情况下，即可轻易定义基脚形状的尺寸，这将大幅节省制造成本。
虽然本发明已以多个较佳实施例揭示如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视所附的权利要求所界定的范围为准。

Claims (8)

1.一种集成电路元件的形成方法，包括：
形成一凸块下冶金层于一半导体基板上；
形成一光致抗蚀剂结构于该凸块下冶金层上，其中该光致抗蚀剂结构包括一第一光致抗蚀剂膜与位于该第一光致抗蚀剂膜上的一第二光致抗蚀剂膜，且该第一光致抗蚀剂膜的光敏性不同于该第二光致抗蚀剂膜的光敏性；
形成一开口于该光致抗蚀剂结构中以露出部分的该凸块下冶金层，其中该开口包括一第一开口位于该第一光致抗蚀剂膜中及一第二开口位于该第二光致抗蚀剂膜中，且该第一开口的底部直径大于该第一开口的顶部直径；
形成一导电层于该光致抗蚀剂结构的该开口中，且该导电层电性连接至露出的部分该凸块下冶金层；以及
移除该光致抗蚀剂结构，其中该导电层形成一导电柱；
其中该第一光致抗蚀剂膜与该第二光致抗蚀剂膜的组成均为负光致抗蚀剂材料，或均为正光致抗蚀剂材料；
当该第一光致抗蚀剂膜与该第二光致抗蚀剂膜的组成均为负光致抗蚀剂材料时，该第二光致抗蚀剂膜的光敏性大于该第一光致抗蚀剂膜的光敏性，或者
当该第一光致抗蚀剂膜与该第二光致抗蚀剂膜的组成均为正光致抗蚀剂材料时，该第一光致抗蚀剂膜的光敏性大于该第二光致抗蚀剂膜的光敏性。
2.如权利要求1所述的集成电路元件的形成方法，其中该第一光致抗蚀剂膜比该第二光致抗蚀剂膜厚，且该第二开口的直径小于该第一开口的底部直径。
3.如权利要求1所述的集成电路元件的形成方法，更包括在移除该光致抗蚀剂结构的步骤前，先形成一盖层于该开口中的该导电层上，以及形成一焊料层于该盖层上，其中该盖层包括镍或镍合金两者中至少一者。
4.如权利要求1所述的集成电路元件的形成方法，其中该导电层包括铜或铜合金两者中至少一者。
5.一种集成电路元件的形成方法，包括：
形成一凸块下冶金层于一半导体基板上；
形成一第一光致抗蚀剂膜于该凸块下冶金层上，该第一光致抗蚀剂膜具有一第一厚度与一第一光敏性；
形成一第二光致抗蚀剂膜于该第一光致抗蚀剂膜上，且该第二光致抗蚀剂膜具有一第二厚度与一第二光敏性；
其中该第二光敏性大于该第一光敏性，且该第二厚度大于该第一厚度；
进行一曝光工艺至该第二光致抗蚀剂膜与该第一光致抗蚀剂膜；
移除未曝光的部分该第二光致抗蚀剂膜以形成一第一开口；
移除未曝光的部分该第一光致抗蚀剂膜以露出部分该凸块下冶金层，形成一第二开口于该第一开口下，以及形成一第三开口于该第二开口下；
其中该第一光致抗蚀剂膜围绕该第二开口，且该第二开口的底部直径大于该第二开口的顶部直径；
形成一铜层于该第一开口、该第二开口、与该第三开口中以电性连接至露出的部分该凸块下冶金层；以及
移除该第二光致抗蚀剂膜与该第一光致抗蚀剂膜，其中该铜层形成一铜柱；
其中该第一光致抗蚀剂膜与该第二光致抗蚀剂膜均为负光致抗蚀剂材料。
6.如权利要求5所述的集成电路元件的形成方法，其中该第二开口的侧壁与该凸块下冶金层交会的夹角小于90度，其中该第二开口的底部直径比该第二开口的顶部直径大2μm以上。
7.一种集成电路元件的形成方法，包括：
形成一凸块下冶金层于一半导体基板上；
形成一第一光致抗蚀剂膜于该凸块下冶金层上，该第一光致抗蚀剂膜具有一第一厚度与一第一光敏性；
形成一第二光致抗蚀剂膜于该第一光致抗蚀剂膜上，且该第二光致抗蚀剂膜具有一第二厚度与一第二光敏性；
其中该第一光敏性大于该第二光敏性，且该第二厚度大于该第一厚度；
进行一曝光工艺至该第二光致抗蚀剂膜与该第一光致抗蚀剂膜；
移除曝光的部分该第二光致抗蚀剂膜以形成一第一开口；
移除曝光的部分该第一光致抗蚀剂膜以露出部分该凸块下冶金层，形成一第二开口于该第一开口下，以及形成一第三开口于该第二开口下；
其中该第一光致抗蚀剂膜围绕该第二开口，且该第二开口的底部直径大于该第二开口的顶部直径；
形成一铜层于该第一开口、该第二开口、与该第三开口中以电性连接至露出的部分该凸块下冶金层；以及
移除该第二光致抗蚀剂膜与该第一光致抗蚀剂膜，其中该铜层形成一铜柱；
其中该第一光致抗蚀剂膜与该第二光致抗蚀剂膜均为正光致抗蚀剂材料。
8.如权利要求7所述的集成电路元件的形成方法，其中该第二开口的侧壁与该凸块下冶金层交会的夹角小于90度，其中该第二开口的底部直径比该第二开口的顶部直径大2μm以上。
CN2010106039702A 2010-08-12 2010-12-22 集成电路元件的形成方法 Expired - Fee Related CN102376638B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/855,360 2010-08-12
US12/855,360 US8598030B2 (en) 2010-08-12 2010-08-12 Process for making conductive post with footing profile

Publications (2)

Publication Number Publication Date
CN102376638A CN102376638A (zh) 2012-03-14
CN102376638B true CN102376638B (zh) 2013-12-25

Family

ID=45565131

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2010106039702A Expired - Fee Related CN102376638B (zh) 2010-08-12 2010-12-22 集成电路元件的形成方法

Country Status (3)

Country Link
US (2) US8598030B2 (zh)
CN (1) CN102376638B (zh)
TW (1) TWI423357B (zh)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9142533B2 (en) 2010-05-20 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate interconnections having different sizes
US8823166B2 (en) * 2010-08-30 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar bumps and process for making same
US9105588B2 (en) * 2010-10-21 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor component having a second passivation layer having a first opening exposing a bond pad and a plurality of second openings exposing a top surface of an underlying first passivation layer
KR101782503B1 (ko) * 2011-05-18 2017-09-28 삼성전자 주식회사 솔더 범프 붕괴를 억제하는 반도체 소자의 범프 형성방법
TWI456676B (zh) * 2012-02-17 2014-10-11 Chipbond Technology Corp 微細間距凸塊製造方法及其結構
US9425136B2 (en) 2012-04-17 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US9299674B2 (en) 2012-04-18 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace interconnect
TWI484610B (zh) * 2012-07-09 2015-05-11 矽品精密工業股份有限公司 半導體結構之製法與導電凸塊
US9111817B2 (en) 2012-09-18 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure and method of forming same
TWI473227B (zh) * 2012-11-15 2015-02-11 矽品精密工業股份有限公司 基板之連接結構及其製法
CN103219305B (zh) * 2013-04-18 2016-04-06 南通富士通微电子股份有限公司 凸点底部保护结构
US9295163B2 (en) * 2013-05-30 2016-03-22 Dyi-chung Hu Method of making a circuit board structure with embedded fine-pitch wires
JP2014241320A (ja) * 2013-06-11 2014-12-25 ソニー株式会社 半導体装置、半導体装置の製造方法
TWI576870B (zh) 2013-08-26 2017-04-01 精材科技股份有限公司 電感結構及其製作方法
TWI511251B (zh) * 2013-09-06 2015-12-01 矽品精密工業股份有限公司 半導體裝置及其製法與半導體結構
WO2015055247A1 (de) * 2013-10-17 2015-04-23 Osram Opto Semiconductors Gmbh Verfahren zur herstellung einer vielzahl von oberflächenmontierbaren trägervorrichtungen, anordnung einer vielzahl von oberflächenmontierbaren trägervorrichtungen und oberflächenmontierbare trägervorrichtung
US10163828B2 (en) * 2013-11-18 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and fabricating method thereof
US10090267B2 (en) 2014-03-13 2018-10-02 Taiwan Semiconductor Manufacturing Co., Ltd Bump structure and method for forming the same
CN104952735B (zh) * 2014-03-25 2018-10-16 中芯国际集成电路制造(上海)有限公司 具有金属柱的芯片封装结构及其形成方法
US20150279793A1 (en) * 2014-03-27 2015-10-01 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US9214454B2 (en) * 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US10147692B2 (en) 2014-09-15 2018-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package with UBM and methods of forming
US10269752B2 (en) * 2014-09-15 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package with UBM and methods of forming
CN104465426B (zh) * 2014-12-25 2018-04-27 颀中科技（苏州）有限公司 凸块的制作方法
WO2017073350A1 (ja) * 2015-10-30 2017-05-04 株式会社村田製作所 薄膜素子およびその製造方法
CN105977177A (zh) * 2016-05-11 2016-09-28 上海华虹宏力半导体制造有限公司 解决半导体测试失败的半导体结构以及半导体测试方法
US9905522B1 (en) * 2016-09-01 2018-02-27 Semiconductor Components Industries, Llc Semiconductor copper metallization structure and related methods
CN106783637A (zh) * 2016-12-30 2017-05-31 通富微电子股份有限公司 一种芯片及其制造方法
US10593638B2 (en) * 2017-03-29 2020-03-17 Xilinx, Inc. Methods of interconnect for high density 2.5D and 3D integration
JP7117615B2 (ja) * 2017-12-08 2022-08-15 パナソニックＩｐマネジメント株式会社 半導体装置の製造方法
CN109920787B (zh) * 2017-12-12 2021-05-25 中芯国际集成电路制造(北京)有限公司 互连结构的设计方法、装置及制造方法
TWI678743B (zh) * 2018-12-10 2019-12-01 南茂科技股份有限公司 半導體線路結構及其製作方法
US20200411317A1 (en) * 2019-06-26 2020-12-31 Intel Corporation Integrated circuit package assemblies with high-aspect ratio metallization features
KR20210126188A (ko) 2020-04-09 2021-10-20 삼성전자주식회사 반도체 소자
WO2023026984A1 (ja) * 2021-08-26 2023-03-02 ローム株式会社 電子部品

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1094850A (zh) * 1993-02-08 1994-11-09 三星电子株式会社 制造半导体芯片凸块的方法
US6586322B1 (en) * 2001-12-21 2003-07-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a bump on a substrate using multiple photoresist layers
US6962771B1 (en) * 2000-10-13 2005-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Dual damascene process
CN101154049A (zh) * 2006-09-29 2008-04-02 中国科学院长春光学精密机械与物理研究所 一种制备光刻胶图形的方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8259464B2 (en) * 2010-06-24 2012-09-04 Maxim Integrated Products, Inc. Wafer level package (WLP) device having bump assemblies including a barrier metal

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1094850A (zh) * 1993-02-08 1994-11-09 三星电子株式会社 制造半导体芯片凸块的方法
US6962771B1 (en) * 2000-10-13 2005-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Dual damascene process
US6586322B1 (en) * 2001-12-21 2003-07-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a bump on a substrate using multiple photoresist layers
CN101154049A (zh) * 2006-09-29 2008-04-02 中国科学院长春光学精密机械与物理研究所 一种制备光刻胶图形的方法

Also Published As

Publication number Publication date
US8598030B2 (en) 2013-12-03
US20140051244A1 (en) 2014-02-20
TWI423357B (zh) 2014-01-11
CN102376638A (zh) 2012-03-14
TW201207967A (en) 2012-02-16
US20120040524A1 (en) 2012-02-16
US8716123B2 (en) 2014-05-06

Similar Documents

Publication Publication Date Title
CN102376638B (zh) 集成电路元件的形成方法
CN102148201B (zh) 半导体元件、封装结构、及半导体元件的形成方法
US8390125B2 (en) Through-silicon via formed with a post passivation interconnect structure
US7494912B2 (en) Terminal pad structures and methods of fabricating same
US7919835B2 (en) Semiconductor device and method for manufacturing the same
CN101771012B (zh) 半导体装置及其制造方法
US20060163734A1 (en) Fuse structure and method for making the same
US10109605B2 (en) Polymer layers embedded with metal pads for heat dissipation
US8450206B2 (en) Method of forming a semiconductor device including a stress buffer material formed above a low-k metallization system
US8022543B2 (en) Underbump metallurgy for enhanced electromigration resistance
US20150130057A1 (en) Post Passivation Interconnect Structures and Methods for Forming the Same
KR101708981B1 (ko) 반도체 디바이스 구조 및 제조 방법
CN102347298A (zh) 基板上的凸块结构与其形成方法
CN102403290A (zh) 半导体组件及制造半导体组件的方法
JP2018006391A (ja) 半導体装置およびその製造方法
CN101510536A (zh) 半导体装置及半导体装置的制造方法
KR101132825B1 (ko) 알루미늄이 함유되지 않은 솔더 범프 연결용 다이 영역 및 알루미늄이 함유되지 않은 와이어 본딩 용 테스트 구조를 포함하는 반도체 디바이스
TW201513284A (zh) 半導體元件及其製造方法
TWI820351B (zh) 半導體封裝及其製造方法
US20220238467A1 (en) Methods of fabricating semiconductor devices having conductive pad structures with multi-barrier films
KR20190062268A (ko) 범프 구조물을 갖는 반도체 디바이스 및 반도체 디바이스의 제조 방법
US8299611B2 (en) Ball-limiting-metallurgy layers in solder ball structures
US11315904B2 (en) Semiconductor assembly and method of manufacturing the same
KR20090075883A (ko) 알루미늄 단자 금속층이 없는 금속화층 스택
TW202407937A (zh) 凸塊結構及其製作方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20131225

CF01 Termination of patent right due to non-payment of annual fee