CN1532906A - 半导体装置及其制造方法、电路基板及电子机器 - Google Patents
半导体装置及其制造方法、电路基板及电子机器 Download PDFInfo
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Abstract
一种半导体装置的制造方法,在包含电连接于集成电路(12)上的焊点(16)的半导体基板(10)中形成与焊点(16)电连接的布线层(20);覆盖布线层(20)地形成树脂层(22);在树脂层(22)与布线层(20)交迭的区域中,通过第1方法形成凹部(23);使具有凹部(23)的树脂层(22)固化。通过与第1方法不同的第2方法,去除凹部(23)的底部,在树脂层(22)中形成贯穿孔(24)。在布线层(20)的从贯穿孔24露出的部分上中设置外部端子(28)。根据本发明的半导体装置的制造方法,可以去除布线的活化工序,简化过程。
Description
技术领域
本发明涉及一种半导体装置及其制造方法、电路基板及电子机器。
背景技术
在半导体装置的制造过程中,在布线上形成树脂层(例如焊料抗蚀剂层),在树脂层中形成开口,在布线从开口露出的部分上设置外部端子(例如焊球)。在以往的过程中,在从在树脂层中形成开口开始到设置外部端子之间,使树脂层固化。在该固化工序中,钝化布线从开口露出的部分(例如形成氧化膜)。因此,还必需活化工序(例如氧化膜去除工序)。
专利文献1:国际公开第WO98/32170号申请
发明内容
本发明的目的在于去除布线的活化工序,简化过程。
(1)根据本发明的半导体装置的制造方法,包含以下工序:
(a)在形成集成电路、含有电连接于所述集成电路上的焊点的半导体基板上形成与所述焊点电连接的布线层;
(b)覆盖所述布线层地形成树脂层;
(c)在所述树脂层与所述布线层交迭的区域中,通过第1方法形成凹部;
(d)使具有所述凹部的所述树脂层固化;
(e)通过与所述第1方法不同的第2方法,去除所述凹部的底部,在所述树脂层中形成贯穿孔;和
(f)在所述布线层的从所述贯穿孔中露出的部分上设置外部端子。
根据本发明,当使树脂层固化时,在树脂层中形成凹部,但因为布线层未露出,所以可防止布线层钝化。
(2)在该半导体装置的制造方法中,可以在上述(b)工序中,由热固化性树脂前体来形成所述树脂层,
在所述(d)工序中,加热所述热固化性树脂前体。
(3)在该半导体装置的制造方法中,可以在所述工序(b)中,由感应放射线的树脂前体来形成所述树脂层,所述第1方法包含向所述树脂前体照射所述放射线及显影的工序。
(4)在该半导体装置的制造方法中,所述第2方法可以是干蚀刻。
(5)在该半导体装置的制造方法中,可以由焊料抗蚀剂形成所述树脂层。
(6)本发明的半导体装置,通过上述方法制造。
(7)本发明的电路基板,安装上述半导体装置。
(8)本发明的电子机器,具有上述半导体装置。
附图说明
图1是说明本发明实施方式1的半导体装置制造方法的图。
图2是说明本发明实施方式1的半导体装置制造方法的图。
图3是说明本发明实施方式1的半导体装置制造方法的图。
图4是说明本发明实施方式1的半导体装置制造方法的图。
图5是说明本发明实施方式1的半导体装置制造方法的图。
图6是图7的VI-VI线截面的局部放大图。
图7是说明本发明实施方式1的半导体装置的图。
图8是说明本发明实施方式2的半导体装置制造方法的图。
图9是说明本发明实施方式2的半导体装置的图。
图10是表示安装本实施方式的半导体装置的电路基板的图。
图11是表示具有本实施方式的半导体装置的电子机器的图。
图12是表示具有本实施方式的半导体装置的电子机器的图。
图13是说明本发明实施方式1的半导体装置制造方法的图。
图14是说明本发明实施方式1的半导体装置制造方法的图。
图15是说明本发明实施方式1的变形例的半导体装置制造方法的图。
图16是说明本发明实施方式1的变形例的半导体装置制造方法的图。
图中:10-半导体基板,12-集成电路,14-钝化膜,16-垫片,18-应力缓冲层,20-布线层,22-树脂层,23-凹部,24-贯穿孔,26-凹部,28-外部端子,30-第2树脂层,36-凹部,38-外部端子,40-半导体芯片。
具体实施方式
下面,参照附图来说明本发明的实施方式。
(实施方式1)
图1-图5及图13-图16是说明根据本发明实施方式1的半导体装置制造方法的图。在本实施方式中,如图1所示,使用半导体基板10。在半导体基板10上形成集成电路12。在将半导体基板10切成多个半导体芯片的情况下,在半导体基板10中形成多个集成电路12,各半导体芯片具有各集成电路12。
可以在半导体基板10的表面中形成钝化膜14。例如,也可由SiO2或SiN等无机材料来形成钝化膜14。或以多层方式形成钝化膜14。此时,也可由有机材料形成至少1层(例如表面层)。在半导体基板10(其表面)中形成焊点16。焊点16电连接于集成电路(例如半导体集成电路)12。钝化膜14避开焊点16的至少中央部来形成。
也可在半导体基板10中形成应力缓冲层18。应力缓冲层18也可在半导体基板10中涂布树脂前体(例如热固化性树脂前体)来形成,也可通过在半导体基板10上旋涂扩展树脂前体来形成。应力缓冲层18可由多层形成,也可由1层形成。应力缓冲层18是电绝缘层。应力缓冲层18也可由聚酰亚胺树脂、硅酮改质聚酰亚胺树脂、环氧树脂、硅酮改质环氧树脂、苯并环丁烯(BCB:benzocyclobutene)、聚苯并噁唑(PBO:polybenzoxazole)等形成。应力缓冲层18不含导电性粒子。应力缓冲层18也可由具有遮光性的材料形成。
应力缓冲层18也可由具有感应放射线(光线(紫外线、可视光线)、X射线、电子线)的性质的放射线感应性树脂前体形成。作为放射线感应性树脂前体(例如感光性树脂前体),有照射放射线的部分的溶解性减少而变为不溶性的负型与照射放射线的部分的溶解性增加的正型。
应力缓冲层18也可避开焊点16形成。应力缓冲层18也可避开半导体基板10的切断用区域来形成。应力缓冲层18也可连续或一体地形成于半导体基板10上后再进行图形形成。也可在半导体基板10的多个区域(形成多个集成电路12的区域)的各个中形成应力缓冲层18。此时,在相邻的应力缓冲层18之间有间隙。
在应力缓冲层18上形成布线层20。布线层20可由1层形成,也可由多层形成。例如,也可由溅射法层叠TiW层及Cu层,在其上通过电镀形成Cu层。该形成方法中可适用公知技术。布线层20通过焊点16上(与焊点16电连接)地形成。布线层20从焊点16上开始形成于应力缓冲层18上。
布线层20也可具有脊(land)(比线宽的部分)地形成。脊用于在其上设置外部端子28。
在应力缓冲层18上形成树脂层22。在本申请中,树脂层22包含固化(聚合)前的状态(树脂前体)及固化(聚合)后的状态(树脂)两者。树脂层22也可由焊料抗蚀剂形成。树脂层22覆盖布线层20(例如其整体)形成。树脂层22也可覆盖(例如完全覆盖)应力缓冲层18地形成(例如以完全覆盖的方式)。树脂层22也可露出半导体基板10的切断用区域(避开切断用区域)地形成。树脂层22不包含导电性粒子。树脂层22也可由具有遮光性的材料形成。树脂层22也可在连续或一体地形成于半导体基板10上后进行图形形成。也可在半导体基板10的多个区域的各个中(形成多个集成电路12的区域)形成树脂层22。相邻的树脂层22之间有间隙。
树脂层22也可由热固化性树脂前体来形成。树脂层22也可由具有感应于放射线(光线(紫外线、可视光线)、X射线、电子线)的性质的放射线感应性树脂前体(例如感光性树脂前体)形成。
如图2所示,在树脂层22中形成凹部(第1凹部)23。凹部23形成于树脂层22与布线层20(例如脊)交迭的区域中。凹部23由第1方法形成。第1方法可以包含平版印刷术。例如,树脂层22由放射线感应性树脂前体形成,向其照射放射线,进行图形形成(例如显影)。作为放射线感应性树脂前体(例如感光性树脂前体),有照射放射线(例如光)的部分的溶解性减少而变为不溶性的负型和照射放射线(例如光)的部分的溶解性增加的正型。凹部23也可形成为随着深度增加其宽度比其开口的宽度小。凹部23也可形成为其内表面不具备角。凹部23也可形成为其内表面为平缓的曲面。
进一步详细说明凹部23的形成方法(第1方法)。在图13及图14所示实例中,在曝光工序中,通过减少放射线的照射量(例如缩短照射时间、降低光的强度),形成凹部23。如图13所示,在树脂层22的上方配置掩模50,经掩模50向树脂层22照射放射线60。在本实施方式中,作为一例,使用阳极型的放射线感应性树脂前体。掩模50具有相对放射线60的遮蔽部分52和相对放射线60的透过部分54。掩模50包含玻璃基材,经玻璃基材向树脂层22照射放射线60。
在本工序中,放射线60的照射量比通常的情况(例如在树脂层22中形成具有直线延伸的壁面的开口的情况)少。因此,放射线60未到达树脂层22的下部(接触布线20的部分)。放射线60不仅垂直而且还倾斜入射到树脂层22。对应于掩模50的布图形状(对应于透过部分54的布图形状)来向树脂层22照射垂直入射的放射线60。倾斜入射的放射线60从掩模50的遮蔽部分52与透过部分54的边界绕回地照射到树脂层22。因此,在掩模50的遮蔽部分52与透过部分54的正下方附近,随着从透过部分52的中央部向遮蔽部分54的方向前进,放射线60向树脂层22的照射缓慢减少,照射放射线60的深度缓慢变浅。由此,可将树脂层22中通过放射线60的照射溶解性增加的部分形成凹部形状。之后,在显影工序中,溶解及去除树脂层22的溶解性增加的部分,如图14所示,形成凹部23。
作为凹部23的形成方法(第1方法)的变形例,在图15及图16所示实例中,在显影工序中,通过减少基于显影的溶解量(例如缩短显影时间、降低显影液的浓度),形成凹部23。首先如图15所示进行曝光工序。在本工序中,可适用上述形态(参照图13)中说明的内容,但在本变形例中,照射足够量(例如可在树脂层22中形成具有直线延伸的壁面的开口的程度)的放射线60。因此,放射线60到达树脂层22的下部(接触布线20的部分)。放射线60照射到交迭于树脂层22的透过部分52的部分上。如图15所示,放射线60也可通过向树脂层22的倾斜入射,以比透过部分54的幅度大的幅度照射。之后,在显影工序中,使树脂层22的溶解性增加的部分溶解,但在本变形例中,因为减少基于显影的溶解量来进行,所以如图16所示,可仅去除树脂层22的溶解性增加的部分的局部。显影液从树脂层22的表面(与布线20相反的面)浸入,从溶解性增加的部分的中央部向端部方向前进,浸入深度缓慢变浅。因此,可如图16所示,形成凹部23。
另外,即使在进行通常的曝光及显影工序的情况下,树脂层22的开口多不形成直线状的壁面,而是随着从开口的中央部的距离的增加残余树脂层22的厚度变大的曲线状壁面,这样可由该残余来形成凹部23。
如图3所示,使树脂层22固化。树脂层22的固化过程也可是使布线层20钝化(例如形成氧化膜)。例如,在由热固化性树脂前体来形成树脂层22的情况下,加热树脂层22并使固化(聚合)。在本实施方式中,当使树脂层22固化时,在树脂层22中形成凹部23,但因为布线层20未露出,所以可防止布线层20钝化。因此,可去除布线层20的活化工序,简化过程。
如图4所示,在树脂层22中形成贯穿孔24。贯穿孔24的形成在树脂层22固化之后进行。通过去除凹部23的底部来形成贯穿孔24。贯穿孔24的形成通过第2方法进行。第2方法与凹部23的形成方法(第1方法)不同。第2方法例如可以是干蚀刻。
另外,在布线层20中形成凹部(第2凹部)26。凹部26可以形成为与贯穿孔24交迭。凹部26的开口整体可以形成在贯穿孔24内。可以在凹部26的形成中适用蚀刻(例如干蚀刻)。凹部26的形成方法可以与贯穿孔24的形成相同。也可形成贯穿孔24,并接着形成凹部26。凹部26也可形成为随着深度增加其宽度比其开口宽度小。凹部26也可形成为其内表面不具备角。凹部26也可形成为其内表面为平缓的曲面。
如图5所示,形成外部端子28。在布线层20从贯穿孔24露出的部分(例如凹部26)中形成外部端子28。外部端子28形成为接合于布线层20(例如其凹部26)。外部端子28也可接触树脂层22的贯穿孔24的内表面。外部端子28可由软焊料(soft solder)或硬焊料(hard solder)之一形成。作为软焊料,也可使用不含铅的焊料(下面称为无铅焊料)。作为无铅焊料,也可使用锡-银(Sn-Ag)类、锡-铋(Sn-Bi)类、锡-锌(Sn-Zn)类或锡-铜(Sn-Cu)类的合金,也可向这些合金中添加银、铋、锌、铜中的至少之一。在外部端子28的形成中可适用公知技术。
如图5所示,也可在树脂层22上形成第2树脂层30。应力缓冲层18的内容也可适用于第2树脂层30。第2树脂层30包围外部端子28地设置。第2树脂层30也可覆盖外部端子28的一部分(例如根部)。第2树脂层30也可覆盖树脂层22(例如完全覆盖)地形成。第2树脂层30也可在覆盖半导体基板10的整体地形成后进行图形形成。也可在覆盖外部端子28地设置第2树脂层30后,从外部端子28的上端部中去除第2树脂层30。可在图形形成中适用应力缓冲层18的图形形成中说明的内容。或者,通过使用激光或灰化,也可去除第2树脂层30的一部分。
本发明实施方式的半导体晶片具有半导体基板10。在半导体基板10中形成多个集成电路12(参照图1),在表面形成焊点16。焊点16电连接于各集成电路12。与焊点16电连接地形成布线层20。在布线层20上形成树脂层22。在布线层20上形成外部端子28。包围外部端子28地形成第2树脂层30。
在树脂层22中形成贯穿孔24。可以在布线层20中形成凹部26。贯穿孔24及凹部26也可交迭地形成。也可在贯穿孔24内形成凹部26的整个开口。外部端子28也可接触树脂层22的贯穿孔24的内表面。
在本实施方式中,外部端子28设置成接合在凹部26上。因此,通过凹部26,布线层20与外部端子28的接合强度提高。另外,通过形成凹部26,布线层20与外部端子28的接触面积变大,所以布线层20与外部端子28的电气连接性能提高。其它细节如上所述。
如图5所示,通过例如刀具(或刀片)32等切断(例如划片或切割)半导体基板10。这样可得到半导体装置。
图6及图7是说明本实施方式的半导体装置,图6是图7的VI-VI线截面图。半导体装置具有半导体芯片40。半导体芯片40可从半导体基板10中切出。半导体装置的其它细节对应于半导体晶片的内容。
(实施方式2)
图8是说明根据本发明实施方式2的半导体装置制造方法的图。在本实施方式中,形成于布线层20中的凹部36的形状与实施方式1的凹部26不同。凹部36形成为随着深度增加其宽度比其开口宽度大。凹部36形成为在随着深度增加的深度方向的第1位置处的第1宽度比其开口宽度大,进而在随着深度增加的第2位置的第2宽度比第1宽度小。若等方性地蚀刻布线层20,则得到该形状的凹部36。例如,也可在树脂层22中形成贯穿孔24后,通过湿蚀刻来形成凹部36。此外的内容相当于实施方式1中说明的内容。
图9是表示根据本发明实施方式2的半导体装置的图。半导体装置也可由图8所示的半导体晶片制造。在本实施方式中,接合在布线层20的凹部36上地设置外部端子38。因此,通过凹部36,布线层20与外部端子28的接合强度提高。另外,通过形成凹部36,布线层20与外部端子38的接触面积变大,所以布线层20与外部端子38的电气连接性能提高。其它内容相当于实施方式1中说明的内容。
图10中示出安装上述实施方式中说明的半导体装置1的电路基板1000。作为具有该半导体装置的电子机器,图11中示出笔记本型个人计算机2000,图12中示出便携电话3000。
本发明不限于上述实施方式,可进行各种变形。
例如,本发明包含实质上与实施方式中说明的结构相同的结构(例如功能、方法及结果相同的结构或目的及结果相同的结构)。另外,本发明包含置换实施方式中说明的结构的非本质的部分的结构。另外,本发明包含可实现与实施方式中说明的结构相同的作用效果的结构或实现相同目的的结构。另外,本发明包含向实施方式中说明的结构中附加公知技术的结构。
Claims (8)
1、一种半导体装置的制造方法,包含以下工序:
(a)在形成集成电路、含有电连接于所述集成电路上的焊点的半导体基板上形成与所述焊点电连接的布线层;
(b)覆盖所述布线层地形成树脂层;
(c)在所述树脂层的与所述布线层交迭的区域中,通过第1方法形成凹部;
(d)使具有所述凹部的所述树脂层固化;
(e)通过与所述第1方法不同的第2方法,去除所述凹部的底部,在所述树脂层中形成贯穿孔;和
(f)在所述布线层的从所述贯穿孔中露出的部分上设置外部端子。
2、根据权利要求1所述的半导体装置的制造方法,其中,
在上述(b)工序中,由热固化性树脂前体来形成所述树脂层,
在所述(d)工序中,加热所述热固化性树脂前体。
3、根据权利要求1或2所述的半导体装置的制造方法,其中,
在所述工序(b)中,由对放射线感应的树脂前体来形成所述树脂层,
所述第1方法包括向所述树脂前体照射所述放射线和显影。
4、根据权利要求1~3中任一项所述的半导体装置的制造方法,其中,
所述第2方法是干蚀刻。
5、根据权利要求1~4中任一项所述的半导体装置的制造方法,其中,
由焊料抗蚀剂形成所述树脂层。
6、一种半导体装置,通过权利要求1~5中任一项所述的方法制造。
7、一种电路基板,安装有权利要求6所述的半导体装置。
8、一种电子机器,具有权利要求6所述的半导体装置。
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JPH11297873A (ja) | 1998-04-13 | 1999-10-29 | Seiko Epson Corp | 半導体装置およびその製造方法 |
JPH11340277A (ja) * | 1998-05-22 | 1999-12-10 | Nec Corp | 半導体チップ搭載基板、半導体装置及び前記半導体チップ搭載基板への半導体チップ搭載方法 |
WO2000055898A1 (fr) | 1999-03-16 | 2000-09-21 | Seiko Epson Corporation | Dispositif a semi-conducteur, son procede de fabrication, carte de circuit et dispositif electronique |
US6707153B2 (en) | 2000-03-23 | 2004-03-16 | Seiko Epson Corporation | Semiconductor chip with plural resin layers on a surface thereof and method of manufacturing same |
JP3886712B2 (ja) * | 2000-09-08 | 2007-02-28 | シャープ株式会社 | 半導体装置の製造方法 |
JP2003209137A (ja) | 2002-01-17 | 2003-07-25 | Seiko Epson Corp | 実装構造基板及びその製造方法並びに電子機器 |
-
2003
- 2003-11-14 JP JP2003385421A patent/JP3918941B2/ja not_active Expired - Fee Related
-
2004
- 2004-03-11 CN CNB2004100284438A patent/CN1301541C/zh not_active Expired - Fee Related
- 2004-03-15 US US10/801,110 patent/US6894394B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113891200A (zh) * | 2021-09-24 | 2022-01-04 | 青岛歌尔智能传感器有限公司 | 一种麦克风的封装结构 |
Also Published As
Publication number | Publication date |
---|---|
US6894394B2 (en) | 2005-05-17 |
JP2004304153A (ja) | 2004-10-28 |
CN1301541C (zh) | 2007-02-21 |
JP3918941B2 (ja) | 2007-05-23 |
US20040245625A1 (en) | 2004-12-09 |
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