CN1089441C - 用于jtag测试asic中的兆单元的方法和装置 - Google Patents

用于jtag测试asic中的兆单元的方法和装置 Download PDF

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Publication number
CN1089441C
CN1089441C CN96194624A CN96194624A CN1089441C CN 1089441 C CN1089441 C CN 1089441C CN 96194624 A CN96194624 A CN 96194624A CN 96194624 A CN96194624 A CN 96194624A CN 1089441 C CN1089441 C CN 1089441C
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Prior art keywords
circuit
megacell
test
integrated circuit
input
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Expired - Fee Related
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CN96194624A
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Chinese (zh)
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CN1187244A (zh
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小·R·J·莫特
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558Addressing or selecting of subparts of the device under test

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Semiconductor Integrated Circuits (AREA)
CN96194624A 1995-06-07 1996-06-06 用于jtag测试asic中的兆单元的方法和装置 Expired - Fee Related CN1089441C (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US48048395A 1995-06-07 1995-06-07
US08/480,483 1995-06-07
US52839795A 1995-09-14 1995-09-14
US08/528,397 1995-09-14

Publications (2)

Publication Number Publication Date
CN1187244A CN1187244A (zh) 1998-07-08
CN1089441C true CN1089441C (zh) 2002-08-21

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CN96194624A Expired - Fee Related CN1089441C (zh) 1995-06-07 1996-06-06 用于jtag测试asic中的兆单元的方法和装置

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US (1) US5805609A (enExample)
EP (1) EP0834081B1 (enExample)
JP (1) JP3698166B2 (enExample)
KR (1) KR100248258B1 (enExample)
CN (1) CN1089441C (enExample)
AU (1) AU6251896A (enExample)
DE (1) DE69631658T2 (enExample)
IL (2) IL120927A (enExample)
TW (1) TW297096B (enExample)
WO (2) WO1996041205A1 (enExample)

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CN100365423C (zh) * 2004-10-20 2008-01-30 华为技术有限公司 一种jtag链自动连接系统及其实现方法

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CN103097902B (zh) * 2010-07-29 2015-12-09 德克萨斯仪器股份有限公司 改进全速测试访问端口操作
CN102778645B (zh) * 2011-05-09 2014-09-17 京微雅格(北京)科技有限公司 一种jtag主控制器及其实现方法
CN104899123B (zh) * 2015-04-24 2017-06-06 英业达科技有限公司 一种主板上dimm插槽的地址设置信号的连接测试装置与方法
KR20160139496A (ko) * 2015-05-27 2016-12-07 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템
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CN108957283B (zh) * 2017-05-19 2021-08-03 龙芯中科技术股份有限公司 辐照实验板、监控终端、asic芯片辐照实验系统
CN107843828A (zh) * 2017-10-26 2018-03-27 电子科技大学 一种基于fpga的数字电路边界扫描控制系统
CN109917277B (zh) * 2019-05-16 2019-08-23 上海燧原智能科技有限公司 虚拟测试方法、装置、设备及存储介质
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CN100365423C (zh) * 2004-10-20 2008-01-30 华为技术有限公司 一种jtag链自动连接系统及其实现方法

Also Published As

Publication number Publication date
EP0834081B1 (en) 2004-02-25
WO1996041205A1 (en) 1996-12-19
CN1187244A (zh) 1998-07-08
DE69631658T2 (de) 2004-12-16
KR19990022049A (ko) 1999-03-25
JP3698166B2 (ja) 2005-09-21
DE69631658D1 (de) 2004-04-01
WO1996041206A1 (en) 1996-12-19
IL120927A0 (en) 1997-09-30
AU6251896A (en) 1996-12-30
US5805609A (en) 1998-09-08
EP0834081A1 (en) 1998-04-08
IL120927A (en) 2000-06-01
JPH11506833A (ja) 1999-06-15
EP0834081A4 (en) 1999-03-24
TW297096B (enExample) 1997-02-01
KR100248258B1 (ko) 2000-03-15

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Granted publication date: 20020821

Termination date: 20130606