CN108493183B - 一种阵列基板、覆晶薄膜及其对位方法及显示装置 - Google Patents

一种阵列基板、覆晶薄膜及其对位方法及显示装置 Download PDF

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Publication number
CN108493183B
CN108493183B CN201810283325.3A CN201810283325A CN108493183B CN 108493183 B CN108493183 B CN 108493183B CN 201810283325 A CN201810283325 A CN 201810283325A CN 108493183 B CN108493183 B CN 108493183B
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China
Prior art keywords
alignment
pin
chip
mark
alignment mark
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CN201810283325.3A
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English (en)
Chinese (zh)
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CN108493183A (zh
Inventor
刘仁杰
王向前
陈玲艳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kunshan Govisionox Optoelectronics Co Ltd
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Kunshan Govisionox Optoelectronics Co Ltd
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Priority to CN201810283325.3A priority Critical patent/CN108493183B/zh
Application filed by Kunshan Govisionox Optoelectronics Co Ltd filed Critical Kunshan Govisionox Optoelectronics Co Ltd
Priority to JP2020501522A priority patent/JP7058319B2/ja
Priority to EP18913777.1A priority patent/EP3640980A4/en
Priority to PCT/CN2018/102687 priority patent/WO2019192137A1/zh
Priority to KR1020207000274A priority patent/KR20200008655A/ko
Publication of CN108493183A publication Critical patent/CN108493183A/zh
Priority to TW107133340A priority patent/TWI659513B/zh
Priority to US16/265,630 priority patent/US10964644B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/50—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for positioning, orientation or alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/147—Structural association of two or more printed circuits at least one of the printed circuits being bent or folded, e.g. by using a flexible printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10128—Display
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/101—Marks applied to devices, e.g. for alignment or identification characterised by the type of information, e.g. logos or symbols
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H10W46/607—Located on parts of packages, e.g. on encapsulations or on package substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07221—Aligning
    • H10W72/07223—Active alignment, e.g. using optical alignment using marks or sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07521—Aligning
    • H10W72/07523—Active alignment, e.g. using optical alignment using marks or sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Wire Bonding (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
CN201810283325.3A 2018-04-02 2018-04-02 一种阵列基板、覆晶薄膜及其对位方法及显示装置 Active CN108493183B (zh)

Priority Applications (7)

Application Number Priority Date Filing Date Title
CN201810283325.3A CN108493183B (zh) 2018-04-02 2018-04-02 一种阵列基板、覆晶薄膜及其对位方法及显示装置
EP18913777.1A EP3640980A4 (en) 2018-04-02 2018-08-28 MATRIX SUBSTRATE, CHIP ON FILM, DISPLAY AND ALIGNMENT PROCESS
PCT/CN2018/102687 WO2019192137A1 (zh) 2018-04-02 2018-08-28 阵列基板、覆晶薄膜、显示装置及对位方法
KR1020207000274A KR20200008655A (ko) 2018-04-02 2018-08-28 어레이 기판, 칩 온 필름, 표시 장치 및 얼라인먼트 방법
JP2020501522A JP7058319B2 (ja) 2018-04-02 2018-08-28 アレイ基板、ｃｏｆ、表示装置及び位置合わせ方法
TW107133340A TWI659513B (zh) 2018-04-02 2018-09-21 陣列基板、覆晶薄膜、顯示裝置及對位方法
US16/265,630 US10964644B2 (en) 2018-04-02 2019-02-01 Array substrate, chip on film, and alignment method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810283325.3A CN108493183B (zh) 2018-04-02 2018-04-02 一种阵列基板、覆晶薄膜及其对位方法及显示装置

Publications (2)

Publication Number Publication Date
CN108493183A CN108493183A (zh) 2018-09-04
CN108493183B true CN108493183B (zh) 2020-05-08

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CN201810283325.3A Active CN108493183B (zh) 2018-04-02 2018-04-02 一种阵列基板、覆晶薄膜及其对位方法及显示装置

Country Status (6)

Country Link
EP (1) EP3640980A4 (https=)
JP (1) JP7058319B2 (https=)
KR (1) KR20200008655A (https=)
CN (1) CN108493183B (https=)
TW (1) TWI659513B (https=)
WO (1) WO2019192137A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110097823B (zh) * 2019-04-09 2021-02-02 深圳市华星光电半导体显示技术有限公司 显示面板及显示模组
CN110930866B (zh) * 2019-11-26 2021-07-06 Tcl华星光电技术有限公司 覆晶薄膜及显示装置
CN111081151A (zh) * 2020-01-08 2020-04-28 深圳市华星光电半导体显示技术有限公司 显示面板
CN114696129B (zh) * 2020-12-28 2026-03-20 超聚变数字技术股份有限公司 显示模组及电子设备
WO2022236780A1 (zh) * 2021-05-13 2022-11-17 京东方科技集团股份有限公司 电路板、覆晶膜、显示装置和绑定方法
KR102802969B1 (ko) * 2022-10-24 2025-05-08 세메스 주식회사 반도체 기판 장치와, 반도체 처리 방법 및 반도체 처리 장치

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JPH11274670A (ja) * 1998-03-19 1999-10-08 Kyocera Corp 積層基板
JP4651886B2 (ja) * 2001-09-14 2011-03-16 東北パイオニア株式会社 電子機器及び電子機器の製造方法
JP4214357B2 (ja) * 2002-02-28 2009-01-28 セイコーエプソン株式会社 電子デバイスの製造方法
JP3544970B2 (ja) * 2002-09-30 2004-07-21 沖電気工業株式会社 Ｃｏｆテープキャリア、半導体素子、半導体装置
JP2006119321A (ja) * 2004-10-21 2006-05-11 Kofu Casio Co Ltd 電気回路間の導通接続構造
JP2006245514A (ja) * 2005-03-07 2006-09-14 Hitachi Media Electoronics Co Ltd フレキシブル基板同士の接続方法
CN100461984C (zh) * 2005-09-30 2009-02-11 友达光电股份有限公司 电路组装结构
TWI292936B (en) * 2006-03-24 2008-01-21 Chipmos Technologies Inc Inner lead bonding tape and tape carrier package utilizing the tape
TW200822303A (en) * 2006-11-07 2008-05-16 Chipmos Technologies Inc Substrate for chip on film packages
CN100545890C (zh) * 2007-03-22 2009-09-30 中华映管股份有限公司 显示面板、显示面板的引脚接合及检测方法
TWI343090B (en) * 2007-05-18 2011-06-01 Au Optronics Corp System and method for alignment
CN101060112B (zh) * 2007-06-11 2010-10-06 友达光电股份有限公司 基板对位系统及其对位方法
JP2012013719A (ja) * 2010-06-29 2012-01-19 Funai Electric Co Ltd Ｃｏｆアライメントマーク
US8994898B2 (en) * 2012-10-18 2015-03-31 Shenzhen China Star Optoelectronics Technology Co., Ltd COF base tape and manufacturing method thereof and liquid crystal display module comprising same
CN203365865U (zh) * 2013-07-04 2013-12-25 京东方科技集团股份有限公司 一种阵列基板、覆晶薄膜和显示装置
CN105551378A (zh) * 2016-02-04 2016-05-04 京东方科技集团股份有限公司 一种覆晶薄膜、柔性显示面板及显示装置
CN106783664B (zh) * 2017-01-03 2020-04-21 京东方科技集团股份有限公司 一种显示模组、绑定检测方法及绑定系统

Also Published As

Publication number Publication date
TWI659513B (zh) 2019-05-11
EP3640980A1 (en) 2020-04-22
KR20200008655A (ko) 2020-01-28
JP2020526934A (ja) 2020-08-31
TW201943044A (zh) 2019-11-01
EP3640980A4 (en) 2020-10-28
CN108493183A (zh) 2018-09-04
JP7058319B2 (ja) 2022-04-21
WO2019192137A1 (zh) 2019-10-10

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Application publication date: 20180904

Assignee: Yungu (Gu'an) Technology Co., Ltd.|Bazhou Yungu Electronic Technology Co., Ltd.|Kunshan Institute of technology new flat panel display technology center Co., Ltd

Assignor: Kunshan Guo Xian Photoelectric Co., Ltd.

Contract record no.: X2019990000156

Denomination of invention: Array substrate, chip on film and alignment method thereof, and display apparatus

License type: Common License

Record date: 20191030

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