^ 200822303 九、發明說明： 【發明所屬之技術領域】 本發明係有關於薄膜覆晶封裝基板（COF substrate)，特別 係有關於一種有助於晶片接合對位之薄膜覆晶封裝基板。 【先前技術】 在目前的薄膜覆晶封裝構造中，晶片之凸塊與薄膜基板 之引腳兩者的間隔必須對應相同且越來越小，甚至可到 被米以内’故可谷許的對位誤差也越來越嚴格。因此，晶片 接合之對位技術需有所提昇，否則會有橋接短路與訊號連接 失敗的問題。然而，隨著薄膜基板之引腳間隔越小，即引腳 數里θ加基板上可供引腳配置區域要求越大，相對使得對 位標記的設置位置受到局限。 如第1圖所示，一種習知薄膜覆晶封裝基板丨〇〇主要包 含一可撓性介電層11 〇、複數個引腳i2〇以及至少一對位標 記130。該可撓性介電層110係具有一晶片覆蓋區m，以 ( 供一晶片11之設置（如第2圖所示）。該些引腳12〇係設置在 該可撓性介電層110上。該對位標記13〇係設置在該可撓性 介電層11〇上。該基板100另包含有一防銲層14〇，其係形 成於該可撓性介電層110上，並局部覆蓋該些引腳12〇。該 防銲層140之一開孔141略大於該晶片覆蓋區ln，以顯露 該些引腳120之内端121，以供一晶片η之複數個凸塊13 接合。習知地，該對位標記i3〇係位於該防銲層i 4Q之該開 孔141之外或是設在該防銲層14〇之該開孔141與晶片覆蓋 區111之間之狹小區域。當引腳配置的密度提高時，會影響 5 200822303 該基板100之引腳設置區域，並且在晶片接合前之基板對位 時，該對位標記130可能會有被夾具遮蔽之問題。 【發明内容】 本發明之主要目的係在於提供一種薄膜覆晶封裝基板， 改變對位標記之配置位置，以避免佔用引腳設置區域並解決 在對位時對位標記可能被夾具遮蔽之問題。 本發明之次一目的係在於提供一種薄膜覆晶封裝基板， 用以增進對位標記之固定力。 本發明的目的及解決其技術問題主要是採用以下 技術方案來實現的。依據本發明揭示一種薄膜覆晶封 裝基板係包含一可撓性介電層、複數個引腳以及至少 一對位標記。該可撓性介電層係具有一晶片覆蓋區（chip footprint area)。該些引腳係設置於該可撓性介電層上，其中 該些引腳之内端更延伸至該晶片覆蓋區内。該對位標記係設 置於該可撓性介電層上且位於該晶片覆蓋區内。另揭示使用 該基板之一薄膜覆晶封裝構造。 本發明的目的及解決其技術問題還可採用以下技 術措施進一步實現。 在如述的薄膜覆晶封裝基板中，該對位標記係可直接貼 附於該可撓性介電層。 在前述的薄膜覆晶封裝基板中，該對位標記與該些引腳 係可為相同之金屬材質。 在前述的薄膜覆晶封裝基板中，該對位標記之形狀係可 選自於十字形、方形、T字形與L形之其中之一。 6 ,200822303 在前述的薄膜覆晶封裝基板中，可另包含有一防銲層， 其係形成於該可撓性介電層上並局部覆蓋該些引腳，該防銲 層係具有一開孔’其係對應於該晶片覆蓋區。 在前述的薄膜覆晶封裝基板中，該對位標記係延伸有一 虛置引腳’其一端係延伸至該防銲層之該開孔之外而被該防 銲層所覆蓋。 【實施方式】 在本發明之第一具體實施例中，揭示一種薄膜覆晶 封裝基板，如第3圖所示並可配合參閱第4圖，該薄膜 覆晶封裝基板200係包含一可撓性介電層210、複數 個引腳220以及至少一對位標記23〇。該可撓性介電 層210係具有一晶片覆蓋區211。其中，該晶片覆蓋 區211之尺寸係實質對應於一晶片21之尺寸（如第4 圖所示）。通常該可撓性介電層2丨〇係為聚亞醯胺層 (PI)，而具有良好可撓曲性。 該些引腳220係設置於該可撓性介電層210上，其 中該些引腳220之内端221更延伸至該晶片覆蓋區211 内’而呈顯露狀。通常該些引腳22〇之材質係為鋼， °亥些引腳220之内端221與外端係為顯露狀並電鍍有 一鮮接層（圖未繪出），如錫層。 該對位標記23 〇係設置於該可撓性介電層2丨〇上且 位於該晶片覆蓋區21 1内，例如可位於該晶片覆蓋區 2 1 1之角隅。一般而言，該對位標記2 3 〇與該些引腳 220係可為相同之金屬材質，以與該些引腳220為同 200822303 層結構’以利製造* i 並月b精準作為該些引腳220之對位 基準點。該對位檁& 230係可直接貼附於該可撓性介 電層210。通常該對位標記23〇只需要有一個或一個以上 約9〇。的f角形狀即可，例如其形狀係可…十字形、 方形、T字形血L形#山 一、^之其中之一。在本實施例中，該 對位標記230係為十字形。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a film-on-film package substrate (COF substrate), and more particularly to a film-coated package substrate that facilitates wafer bonding alignment. [Prior Art] In the current film flip-chip package structure, the spacing between the bumps of the wafer and the pins of the film substrate must be the same and smaller, and even can be within the meter. The bit error is also getting stricter. Therefore, the alignment technology of the wafer bonding needs to be improved, otherwise there will be a problem that the bridge short circuit and the signal connection fail. However, as the pin spacing of the film substrate is smaller, that is, the number of pins in the pin number plus the larger the pin configuration area available on the substrate, the position of the alignment mark is relatively limited. As shown in FIG. 1, a conventional thin film flip chip substrate 丨〇〇 mainly includes a flexible dielectric layer 11 〇, a plurality of pins i2 〇, and at least one pair of bit marks 130. The flexible dielectric layer 110 has a wafer footprint m for (providing a wafer 11 (as shown in Figure 2). The pins 12 are disposed on the flexible dielectric layer 110. The alignment mark 13 is disposed on the flexible dielectric layer 11 . The substrate 100 further includes a solder resist layer 14 形成 formed on the flexible dielectric layer 110 and partially Covering the pins 12A. The opening 141 of the solder resist layer 140 is slightly larger than the wafer footprint ln to expose the inner ends 121 of the pins 120 for bonding a plurality of bumps 13 of a wafer η. Conventionally, the alignment mark i3 is located outside the opening 141 of the solder resist layer i 4Q or is narrow between the opening 141 of the solder resist layer 14 and the wafer cover area 111. When the density of the pin configuration is increased, it affects the pin setting area of the substrate 100, and the alignment mark 130 may be shielded by the jig when the substrate is aligned before the wafer bonding. SUMMARY OF THE INVENTION The main object of the present invention is to provide a thin film flip chip package substrate, changing the configuration bit of the alignment mark In order to avoid occupying the pin setting area and solving the problem that the alignment mark may be shielded by the jig when the alignment is performed. A second object of the present invention is to provide a film flip chip package substrate for enhancing the fixing force of the alignment mark. The object of the present invention and the technical problem thereof are mainly achieved by the following technical solutions. According to the invention, a thin film flip chip package substrate comprises a flexible dielectric layer, a plurality of pins and at least one pair of bit marks. The flexible dielectric layer has a chip footprint area. The pins are disposed on the flexible dielectric layer, wherein the inner ends of the pins extend to the wafer footprint The alignment mark is disposed on the flexible dielectric layer and located in the wafer cover area. Another film-on-film package structure using the substrate is disclosed. The object of the present invention and solving the technical problem thereof can also be adopted. The following technical measures are further achieved. In the thin film flip chip package substrate as described, the alignment mark can be directly attached to the flexible dielectric layer. In the board, the alignment mark and the lead wires may be the same metal material. In the foregoing film flip chip package substrate, the shape of the alignment mark may be selected from a cross shape, a square shape, a T shape and an L shape. In the above-mentioned thin film flip chip package substrate, a solder resist layer may be further formed on the flexible dielectric layer and partially cover the pins, the solder resist The layer has an opening corresponding to the wafer footprint. In the foregoing film flip chip package substrate, the alignment mark extends with a dummy pin 'one end extending to the solder resist layer In addition, in the first embodiment of the present invention, a thin film flip chip package substrate is disclosed, as shown in FIG. 3, and can be referred to FIG. 4, The thin film flip chip package substrate 200 includes a flexible dielectric layer 210, a plurality of pins 220, and at least a pair of bit marks 23A. The flexible dielectric layer 210 has a wafer footprint 211. The size of the wafer footprint 211 substantially corresponds to the size of a wafer 21 (as shown in FIG. 4). Typically, the flexible dielectric layer 2 is a polyimide layer (PI) with good flexibility. The pins 220 are disposed on the flexible dielectric layer 210, wherein the inner ends 221 of the pins 220 extend into the wafer footprint 211 to be exposed. Usually, the materials of the pins 22 are made of steel, and the inner ends 221 and the outer ends of the pins 220 are exposed and plated with a fresh layer (not shown), such as a tin layer. The alignment mark 23 is disposed on the flexible dielectric layer 2 and located in the wafer footprint 21 1 , for example, at a corner 该 of the wafer coverage area 21 1 . In general, the alignment mark 2 3 〇 and the pins 220 can be the same metal material, and the same as the pin 220 is used for the 200822303 layer structure to facilitate the manufacture of * i and the monthly b precision as the The alignment reference point of pin 220. The para-position & 230 series can be directly attached to the flexible dielectric layer 210. Usually, the alignment mark 23〇 only needs to have one or more than about 9 inches. The shape of the f-angle can be, for example, its shape can be... a cross, a square, a T-shaped blood L-shaped #山一, ^ one of them. In the present embodiment, the alignment mark 230 is in the shape of a cross.
( 該基板200可另包含有一防銲層240，纟係形成於 該可撓性介電層210上並局部覆蓋該些引腳22〇。該 防銲層240係具有一開孔241，概呈矩形，其係對應 於該晶片覆蓋區2U，以顯露該些引腳22〇之内端221 與該對位標記230。通常該防銲層24〇之開孔241係 稍大於該晶片覆蓋區2 1 1。 如第4圖所示，使用前述之基板2〇〇可以製成一薄 膜覆晶封裝構造，主要包含該基板200、一晶片21與一封膠 體22,該晶片21係設置於該基板2〇〇上，該晶片21係具有 複數個凸塊23。依據該對位標記230之參考座標，可將該4b 凸塊23準確接合至該些引腳之内端221。再利用點塗形成之 封膠體22密封該些凸塊23。此外，該對位標記23〇不會佔 用該基板200之引腳設置區域並解決在對位時習知對位標記 可能被夾具遮蔽之問題。 如第5A與5B圖所示，上述在晶片覆蓋區211之 對位標記230能以不同形狀的對位標記23 〇a與230 b 替換之。例如第5A圖之對位標記230A係為方形，第 5B圖之對位標記230B係為T形。 200822303 依據本發明之第二具體實施例，揭示另一薄膜覆晶封裝 基板。如笫6圖所示並配合參閱第7圖，該薄膜覆晶封裝基 板3 00係包含一可撓性介電層3 1〇、複數個引腳32〇以 及至少一對位標記3 3 〇。該可撓性介電層3 1 0係具有 一晶片覆篕區3 1 1，其係指預定被晶片佔用的區域。The substrate 200 may further include a solder resist layer 240 formed on the flexible dielectric layer 210 and partially covering the leads 22 . The solder resist layer 240 has an opening 241. a rectangle corresponding to the wafer footprint 2U to expose the inner end 221 of the pins 22 and the alignment mark 230. Typically, the solder mask 24 opening 241 is slightly larger than the wafer footprint 2 1 . As shown in FIG. 4 , a thin film flip chip package structure can be formed by using the substrate 2 , and the substrate 200 , a wafer 21 and a gel 22 are disposed on the substrate. 2, the wafer 21 has a plurality of bumps 23. According to the reference coordinates of the alignment mark 230, the 4b bumps 23 can be accurately bonded to the inner ends 221 of the pins. The sealing body 22 seals the bumps 23. In addition, the alignment mark 23〇 does not occupy the pin setting area of the substrate 200 and solves the problem that the conventional alignment mark may be shielded by the jig when the alignment is performed. As shown in Figures 5A and 5B, the alignment mark 230 in the wafer footprint 211 can be aligned in different shapes. The marks 23 〇a and 230 b are replaced. For example, the alignment mark 230A of FIG. 5A is square, and the alignment mark 230B of FIG. 5B is T-shaped. 200822303 According to the second embodiment of the present invention, another The film flip chip package substrate. As shown in FIG. 6 and referring to FIG. 7 , the film flip chip package substrate 300 includes a flexible dielectric layer 3 1 , a plurality of pins 32 〇 and at least one pair. The bit mark 3 3 〇. The flexible dielectric layer 310 has a wafer capping region 31, which refers to a region that is intended to be occupied by the wafer.
如第6及7圖所示，該些引腳3 2 0係設置於該可撓性 介電層31〇上，其中該些引腳32〇之内端321更延伸 至該晶片覆蓋區311内。 如第6及7圖所示，該對位標記3 3 〇係設置於該可撓 性介電層3 1 0上且位於該晶片覆蓋區3丨丨内。藉由該 對位軚圮33 0之設置位置，避免佔用該基板3〇〇之引腳 α置區域並解決在對位時習知對位標記可能被夾具遮蔽之 問題在本實施例中，該對位標記3 3 〇係為l形。 此外該基板3〇〇係可另包含有一防銲層34〇，其 係形成於該可撓性介雷爲 J規『玍）丨電層3 1 〇上並局部覆蓋該些引腳 3曰20 4防銲層34()係具有—開孔“I，其係對應於該 曰曰片覆蓋區3"，以顯露該些引腳320之内端321。 較佳地，該對位標記330係延伸有一虛置引腳331’盆 :端=至該防銲層34。之該開孔Μ之外而被該防銲層 =心能增進該對位標記33。於該可挽性介電層 疋力，以避免不當偏移或鬆脫。 以上所述，僅是本發明的較佳 明作任何形式上的PP別^ 卫非對本發 上，鈇而並非用、々1然本發明已以較佳實施例揭露如 …#用以限定本發明，任何熟悉本項技術者，在不 200822303 脫離本發明之中請專利範圍内，所作的任何簡單修改等效 性變化與修飾’皆涵蓋於本發明的技術範圍内。 ’ 【圖式簡單說明】 第1圖·習知薄膜覆晶封裝基板之俯視示意圖。 第2圖：習知使用該基板之一薄膜覆晶封裝構造之局部截面 示意圖。 第3圖：依據本發明之第一具體實施例，一種薄膜覆晶封裝 基板之俯視示意圖。 第4圖：依據本發明之第一具體實施例，使用該基板之一薄 膜覆晶封裝構造之局部截面示意圖。 第5A與5B圖：依據本發明之第一具體實施例，繪示該薄 膜覆晶封裝基板内對位標記之形狀可等效性變化 之示意圖。 第6圖··依據本發明之第二具體實施例，另一種薄膜覆晶封 裝基板之俯視示意圖。 第7圖：依據本發明之第二具體實施例，使用該基板之一薄 膜覆晶封装構造之局部截面示意圖。 【主要元件符號說明】 11 晶片 12 封膠體 13 凸土鬼 21 晶片 22 封膠體 23 凸塊 31 晶片 32 封膠體 33 凸塊 100 薄膜覆晶封襄基板 110 可撓性介電層 111 晶片覆蓋區 120 引腳 121 内端 200822303 130 對位標記 140 防銲層 141開孔 200 薄膜覆晶封裝基板 210 可撓性介電層 211 晶片覆盖區 220 引腳 221 内端 230 對位標記 230A對位標記 230B對位標記 240 防鲜層 241 開孔 300 薄膜覆晶封裝基板 310 可撓性介電層 311 晶片覆蓋區 320 引腳 321 内端 330 對位標記 331 虛置引腳 340 防銲層 341 開孔 11As shown in FIGS. 6 and 7, the pins 320 are disposed on the flexible dielectric layer 31, wherein the inner ends 321 of the pins 32 extend further into the wafer footprint 311. . As shown in Figures 6 and 7, the alignment mark 3 3 is disposed on the flexible dielectric layer 310 and is located within the wafer footprint 3丨丨. By setting the position of the alignment 軚圮330, the occupation of the pin α area of the substrate is avoided, and the problem that the conventional alignment mark may be shielded by the jig during the alignment is solved. In this embodiment, The alignment mark 3 3 〇 is l-shaped. In addition, the substrate 3 can further include a solder resist layer 34 形成 formed on the flexible dielectric layer 3 1 〇 and partially cover the pins 3 曰 20 The solder resist layer 34() has an opening "I corresponding to the cymbal footprint 3" to expose the inner end 321 of the pins 320. Preferably, the alignment mark 330 is Extending a dummy pin 331' basin: end = to the solder resist layer 34. The solder mask layer is external to the solder mask layer = the core energy can enhance the alignment mark 33. The traceable dielectric layer In order to avoid improper offset or looseness. As described above, it is only preferred that the present invention is in any form of PP. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S) </ RTI> <RTIgt; </ RTI> </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; Within the technical scope. ' [Simple description of the drawing] Fig. 1 is a schematic plan view of a conventional film flip chip package substrate. Fig. 2: A schematic partial cross-sectional view of a thin film flip chip package structure using the substrate. FIG. 3 is a top plan view of a thin film flip chip package substrate according to a first embodiment of the present invention. FIG. 4 is a first specific view of the present invention. Embodiments, a partial cross-sectional view of a thin film flip chip package structure using the substrate. FIGS. 5A and 5B are diagrams showing the shape of the alignment mark in the film flip chip package substrate according to the first embodiment of the present invention. Schematic diagram of the effect change. Fig. 6 is a top plan view of another thin film flip chip package substrate according to a second embodiment of the present invention. Fig. 7 is a view showing a second embodiment of the present invention, using the substrate A partial cross-sectional view of a thin film flip-chip package structure. [Main component symbol description] 11 Wafer 12 Sealant 13 Naked ghost 21 Wafer 22 Sealant 23 Bump 31 Wafer 32 Sealant 33 Bump 100 Thin film flip-chip substrate 110 Flexible Dielectric Layer 111 Wafer Covering Area 120 Pin 121 Inner End 200822303 130 Alignment Marking 140 Solder Mask 141 Opening 200 Film Flip Mounting substrate 210 Flexible dielectric layer 211 Wafer footprint 220 Pin 221 Inner end 230 Alignment mark 230A Alignment mark 230B Alignment mark 240 Fresh-keeping layer 241 Opening 300 Film flip-chip package substrate 310 Flexible dielectric Layer 311 Wafer Cover Area 320 Pin 321 Inner End 330 Alignment Mark 331 dummy pin 340 solder mask 341 opening 11