TWI562312B - Chip-on-film package structure - Google Patents

Chip-on-film package structure

Info

Publication number
TWI562312B
TWI562312B TW103110877A TW103110877A TWI562312B TW I562312 B TWI562312 B TW I562312B TW 103110877 A TW103110877 A TW 103110877A TW 103110877 A TW103110877 A TW 103110877A TW I562312 B TWI562312 B TW I562312B
Authority
TW
Taiwan
Prior art keywords
chip
package structure
film package
film
package
Prior art date
Application number
TW103110877A
Other languages
Chinese (zh)
Other versions
TW201537713A (en
Inventor
Shih Hsi Lin
Original Assignee
Chipmos Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipmos Technologies Inc filed Critical Chipmos Technologies Inc
Priority to TW103110877A priority Critical patent/TWI562312B/en
Priority to CN201410319830.0A priority patent/CN104952830A/en
Publication of TW201537713A publication Critical patent/TW201537713A/en
Application granted granted Critical
Publication of TWI562312B publication Critical patent/TWI562312B/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/27011Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
TW103110877A 2014-03-24 2014-03-24 Chip-on-film package structure TWI562312B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW103110877A TWI562312B (en) 2014-03-24 2014-03-24 Chip-on-film package structure
CN201410319830.0A CN104952830A (en) 2014-03-24 2014-07-07 Packaging structure of thin-film flip chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW103110877A TWI562312B (en) 2014-03-24 2014-03-24 Chip-on-film package structure

Publications (2)

Publication Number Publication Date
TW201537713A TW201537713A (en) 2015-10-01
TWI562312B true TWI562312B (en) 2016-12-11

Family

ID=54167385

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103110877A TWI562312B (en) 2014-03-24 2014-03-24 Chip-on-film package structure

Country Status (2)

Country Link
CN (1) CN104952830A (en)
TW (1) TWI562312B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170192453A1 (en) * 2015-12-30 2017-07-06 Novatek Microelectronics Corp. Wearable device with a chip on film package structure

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200822303A (en) * 2006-11-07 2008-05-16 Chipmos Technologies Inc Substrate for chip on film packages

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0590336A (en) * 1991-09-30 1993-04-09 Mitsubishi Electric Corp Tape carrier package
KR960001345B1 (en) * 1992-08-28 1996-01-26 금성일렉트론주식회사 Glass lead mounting style semiconductor device
KR100384437B1 (en) * 1995-02-28 2003-08-21 텍사스 인스트루먼츠 인코포레이티드 Semiconductor device and assembly method thereof
JP4056424B2 (en) * 2003-05-16 2008-03-05 シャープ株式会社 Manufacturing method of semiconductor device
JP2005109377A (en) * 2003-10-02 2005-04-21 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method therefor
JP2005175205A (en) * 2003-12-11 2005-06-30 Shinko Electric Ind Co Ltd Semiconductor device and its manufacturing method
CN100539110C (en) * 2007-01-22 2009-09-09 南茂科技股份有限公司 Preventing that film from subsiding forms the thin-film flip-chip packaging construction of filler bubble
TW201121006A (en) * 2009-12-03 2011-06-16 Hannstar Display Corp Connection structure for chip-on-glass driver IC and connection method therefor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200822303A (en) * 2006-11-07 2008-05-16 Chipmos Technologies Inc Substrate for chip on film packages

Also Published As

Publication number Publication date
TW201537713A (en) 2015-10-01
CN104952830A (en) 2015-09-30

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