JP2008034681A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method with which a manufacture yield of a semiconductor device can be improved and the semiconductor device can be small-sized. <P>SOLUTION: On a lower surface 31b of each of a number of wiring boards 31 used for manufacturing the semiconductor device; a target mark for determining a cutting position of the wiring board 31 is formed for each dicing area, and a pattern deviation detector 36 is provided in the vicinity of the target mark. The pattern deviation detector 36 includes a through-hole land 37a formed on an upper surface 11a of a substrate layer 11 of the wiring board 31, a through-hole land 37b formed on a lower surface 11b of the substrate layer 11, and a through-hole 38 formed on the substrate layer 11. With the through-hole 38 as a criterion, the amount of deviation (third deviation amount D<SB>3</SB>) between plane positions of the through-hole land 37a and the through-hole land 37b is investigated and used to correct the cutting position on the basis of the target mark, and the wiring board 31 is cut at the corrected cutting position. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique effective when applied to a method for manufacturing a semiconductor device in the form of a semiconductor package in which a semiconductor chip is mounted on a wiring board.

  A semiconductor chip is mounted on the wiring board, the electrodes of the semiconductor chip and the connection terminals of the wiring board are electrically connected with bonding wires, the semiconductor chip and the bonding wires are sealed with resin, and solder balls are connected to the back surface of the wiring board. Thus, a semiconductor device in the form of a semiconductor package is manufactured. Such a semiconductor device includes, for example, a chip size called a CSP (Chip Size Package) or a small semiconductor package that is slightly larger than the semiconductor chip.

  In Japanese Patent Laid-Open No. 2001-77235 (Patent Document 1), dicing is performed on a semiconductor element mounting substrate of a type in which a plurality of semiconductor devices are collectively encapsulated with resin and then separated into individual semiconductor devices by dicing. A technique relating to a semiconductor element mounting substrate in which marks are previously provided on the extensions of the locations where the boundary portions of the respective semiconductor devices to be located are described.

Japanese Patent Application Laid-Open No. 11-186481 (Patent Document 2) describes a technique for forming alignment marks on a frame portion of a lead frame.
JP 2001-77235 A Japanese Patent Laid-Open No. 11-186481

  According to the study of the present inventor, the following has been found.

  Prepare a multi-piece wiring board having a plurality of device regions formed on the main surface, fix a semiconductor chip to each of the plurality of device regions, and after fixing the semiconductor chip, encapsulate the plurality of semiconductor chips in a batch Then, the semiconductor device can be manufactured by forming the collective sealing portion and dividing the collective sealing portion and the multi-piece wiring substrate into the device regions by dicing.

  When external terminals such as solder balls are formed on a semiconductor device, it is not easy to connect the solder balls to a semiconductor device separated by dicing, and the throughput of the semiconductor device is reduced. Before performing, it is necessary to connect the solder balls to the multi-piece wiring board to form external terminals.

  For this reason, after forming the collective sealing portion, it is conceivable to separate the chips by dicing after connecting the solder balls to the lower surface of the multi-piece wiring board. In this case, since dicing is performed with the solder balls connected to the lower surface of the multi-piece wiring board, if the lower surface side of the wiring board is tried to be fixed, the solder balls cannot get in the way and cannot be fixed well. The upper surface side of the stop portion is fixed, and the wiring substrate and the batch sealing portion are cut from the lower surface side of the multi-piece wiring substrate.

  When dicing is performed from the lower surface side of the wiring substrate, the dicing can be performed based on the target mark formed on the lower surface of the wiring substrate. However, since the target mark formed on the lower surface of the wiring board is formed by the pattern of the conductor layer or the solder resist layer on the lower surface side of the wiring board, the relative position with the pattern on the lower surface side of the wiring board is accurate. While it can be formed, it is likely to be shifted from the pattern on the upper surface side of the wiring board. For this reason, the accuracy of the relative position between the target mark formed on the lower surface of the wiring board and the pattern on the upper surface side of the wiring board (for example, a bonding wire connection terminal) tends to be lowered. This is because, for example, the conductor pattern is formed on the upper surface side and the lower surface side of the wiring board by different exposure processes using different photomasks. This is because the general positional accuracy is likely to be lowered.

  For this reason, when individualization is performed by dicing from the lower surface side of the wiring substrate based on the target mark formed on the lower surface of the wiring substrate, the pattern on the upper surface side of the wiring substrate, for example, a connection terminal for connecting a bonding wire, etc. The relative positional accuracy of the dicing position is lowered. When the dicing position is shifted, there is a possibility that the connection terminals and the bonding wires are exposed on the cut surface of the collective sealing portion, that is, the side surface of the sealing resin of the manufactured semiconductor device. This is because, especially in the case of a CSP type semiconductor device, the plane size of the semiconductor chip and the plane size of the semiconductor device formed by cutting are almost the same size, so that the wires provided on the upper surface side of the wiring board are connected. This is because the distance from the connection terminal to the cut surface of the batch sealing portion is short. As a result, the manufacturing yield of the semiconductor device is reduced. In order to prevent the connection terminals and bonding wires from being exposed from the cut surface of the batch sealing portion, that is, the side surface of the sealing resin of the manufactured semiconductor device, even if the dicing position is shifted, the margin of the dicing region is increased. However, this increases the size of the semiconductor device.

  An object of the present invention is to provide a technique capable of improving the manufacturing yield of a semiconductor device.

  Another object of the present invention is to provide a technique capable of downsizing a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  According to the present invention, in a multi-piece wiring board used for manufacturing a semiconductor device, a target mark for positioning the cutting position of the wiring board is provided on the second main surface of the wiring board, and a target mark on the second main surface of the wiring board is provided. The first conductor pattern in the vicinity, the second conductor pattern at a position corresponding to the first conductor pattern on the second principal surface opposite to the first principal surface, and the first conductor pattern and the second conductor pattern in plan view The first opening is provided at the overlapping position, and the amount of deviation of the planar position between the first conductor pattern and the second conductor pattern is examined with reference to the first opening. Further, the cutting position of the wiring board based on the target mark is corrected using the displacement amount of the planar position between the first conductor pattern and the second conductor pattern thus examined.

  According to the present invention, a semiconductor chip is mounted on a first main surface of a wiring board having a plurality of unit substrate regions from which semiconductor devices are manufactured, and the semiconductor is formed on the first main surface of the wiring board. After forming a sealing resin so as to cover the chip, the wiring substrate and the wiring substrate along the dicing region between each unit substrate region from the second main surface side opposite to the first main surface of the wiring substrate A method of manufacturing a semiconductor device for cutting the sealing resin, wherein a target mark for positioning a cutting position of the wiring board is formed on the second main surface for each of the dicing regions on the wiring board, A first conductor pattern is formed in the vicinity of each target mark on the second main surface, a second conductor pattern is formed at a position corresponding to the first conductor pattern on the first main surface, and the first conductor pattern And a first opening is formed at a position overlapping the second conductor pattern in a plane, and (a) a planar position between the second conductor pattern and the first opening on the first main surface of the wiring board is formed. Detecting a first shift amount; and (b) detecting a second shift amount of a planar position between the first conductor pattern and the first opening on the second main surface of the wiring board. And using the second shift amount detected in the step (b) to correct the cutting position based on the target mark, and from the second main surface side of the wiring board at the corrected cutting position. The wiring board and the sealing resin are cut.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The manufacturing yield of the semiconductor device can be improved.

  Further, the semiconductor device can be reduced in size.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

  A method for manufacturing a semiconductor device and a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

  1 is a top view of a semiconductor device 1 according to an embodiment of the present invention, FIG. 2 is a bottom view thereof, FIG. 3 is a cross-sectional view (overall cross-sectional view), and FIG. FIG. 5 is a side view thereof. FIG. 6 is a plan perspective view (top view) of the semiconductor device 1 when the sealing resin 5 is seen through. 1 and 6 substantially corresponds to FIG. 3, and an enlarged view of the end vicinity region of FIG. 3 substantially corresponds to FIG.

  The semiconductor device 1 of the present embodiment shown in FIGS. 1 to 6 is a semiconductor device (semiconductor package) in which a semiconductor chip 2 is mounted (bonded, connected, or mounted) on a wiring board 3. This is a semiconductor device in the form of a CSP (Chip Size Package), which is a small semiconductor package that is slightly larger than the semiconductor chip 2.

  A semiconductor device 1 according to the present embodiment includes a semiconductor chip 2, a wiring board 3 that supports or mounts the semiconductor chip 2, a plurality of electrodes 2a on the surface of the semiconductor chip 2, and a plurality of wiring boards 3 corresponding thereto. A plurality of bonding wires 4 that are electrically connected to the terminals 15, a sealing resin 5 that covers the upper surface 3 a of the wiring substrate 3 including the semiconductor chip 2 and the bonding wires 4, and areas as external terminals on the lower surface 3 b of the wiring substrate 3. And a plurality of solder balls 6 provided in an array arrangement.

  The semiconductor chip 2 has a square planar shape that intersects its thickness. For example, various semiconductor elements or semiconductor integrated circuits are formed on the main surface of a semiconductor substrate (semiconductor wafer) made of single crystal silicon or the like. Accordingly, after the back surface of the semiconductor substrate is ground, the semiconductor substrate is separated into the respective semiconductor chips 2 by dicing or the like. The semiconductor chip 2 has a front surface (main surface and upper surface on the semiconductor element formation side) 2b and a rear surface (main surface and lower surface opposite to the main surface on the semiconductor element formation side) 2c, which are opposite to each other. It is mounted (arranged) on the upper surface (chip support surface) 3 a of the wiring substrate 3 so as to face upward, and the back surface 2 c of the semiconductor chip 2 is attached to the upper surface 3 a of the wiring substrate 3 via an adhesive (die bond material, bonding material) 8. Glued and fixed. As the adhesive 8, for example, an insulating or conductive paste material or a film-like adhesive (die bonding film, die attach film) or the like can be used. The thickness of the adhesive material 8 can be about 20-30 micrometers, for example. The semiconductor chip 2 has a plurality of electrodes (bonding pads, pad electrodes) 2a on the surface 2b, and the electrodes 2a are electrically connected to a semiconductor element or a semiconductor integrated circuit formed in the semiconductor chip 2 or in a surface layer portion. Connected.

  The wiring substrate 3 includes an upper surface (first main surface) 3a that is one main surface, a lower surface (second main surface) 3b that is a main surface opposite to the upper surface 3a, and a plurality of connections formed on the upper surface 3a. It has a terminal 15 and a plurality of lands (land portions) 16 formed on the lower surface 3b.

  The wiring substrate 3 includes an insulating base material layer (insulating substrate, core material) 11 and a conductor layer (conductor pattern, conductor film pattern, wiring layer) 12 formed on the upper surface 11a and the lower surface 11b of the base material layer 11. And a solder resist layer (insulating film, solder resist layer) 14 as an insulating layer (insulator layer, insulating film) formed so as to cover the conductor layer 12 on the upper surface 11a and the lower surface 11b of the base material layer 11. Have. As another form, the wiring board 3 can be formed of a multilayer wiring board in which a plurality of insulating layers and a plurality of wiring layers are laminated.

  The conductor layer 12 (12a, 12b) is patterned and is a conductor pattern that becomes a terminal, a wiring, or a wiring layer of the wiring board 3. The conductor layer 12 is made of a conductive material, and can be formed of, for example, a copper thin film formed by plating. The conductor layer 12 of the wiring board 3 includes a conductor layer 12a formed on the upper surface 11a of the base material layer 11, a conductor layer 12b formed on the lower surface 11b of the base material layer 11, and an opening of the base material layer 11. 17 and a conductor layer 12c formed on the side wall.

  A plurality of connection terminals (electrodes, bonding pads, pad electrodes) 15 for connecting the bonding wires 4 are formed by the conductor layer 12 a formed on the upper surface 11 a of the base material layer 11. Also, a plurality of conductive lands (electrodes, pads, terminals) 16 for connecting the solder balls 6 are formed by the conductor layer 12b formed on the lower surface 11b of the base material layer 11. In addition, a plurality of openings (through holes, vias, through holes) 17 are formed in the base material layer 11, and a conductor layer 12 c is formed on the side wall of each opening 17.

  The connection terminal 15 on the upper surface 11 a of the base material layer 11 includes a conductor layer 12 a (leading wiring made of the conductor layer 12 a) on the upper surface 11 a of the base material layer 11, a conductor layer 12 c on the sidewall of the opening 17, and the base material layer 11. It is electrically connected to the land 16 on the lower surface 11b of the base material layer 11 through the conductor layer 12b on the lower surface 11b. Accordingly, the plurality of electrodes 2 a of the semiconductor chip 2 are electrically connected to the plurality of connection terminals 15 of the wiring board 3 through the plurality of bonding wires 4, and further, the wiring board 3 through the conductor layer 12 of the wiring board 3. The plurality of lands 16 are electrically connected. The bonding wire 4 is made of a fine metal wire such as a gold wire.

  The solder resist layer 14 has a function as an insulating layer (insulating film) for protecting the conductor layer 12, and is made of an insulating material such as an organic resin material. The solder resist layer 14 is formed on the upper surface 11 a and the lower surface 11 b of the base material layer 11 so as to cover the conductor layer 12, and the solder resist layer 14 fills the inside of the opening 17 of the base material layer 11. Yes. Since the solder resist layer 14 fills the opening 17 of the base material layer 11, the adhesive 8 for bonding the semiconductor chip 2 to the wiring board 3 leaks from the opening 17 to the lower surface 3 b side of the wiring board 3. In addition, the back surface 2c of the semiconductor chip 2 can be prevented from being exposed from the opening 17. Further, in the conductor layer 12 of the wiring board 3, the connection terminal 15 and the land 16 are exposed from the openings 19 a and 19 b of the solder resist layer 14. Moreover, the thickness of the solder resist layer 14 on the upper surface 11a and the lower surface 11b of the base material layer 11 can be about 20-30 micrometers, for example. The semiconductor chip 2 is mounted on and bonded to the solder resist layer 14 on the upper surface 3 a side of the wiring substrate 3 via an adhesive material 8. The solder resist layer 14 on the upper surface 3a side of the wiring board 3 is also formed with an opening (conductor portion exposed from the opening) 18 as a package index. An opening (conductor portion exposed from the opening) 18 as a package index formed in the solder resist layer 14 is positioned during the manufacturing process of the semiconductor device 1 (the process until a sealing resin 5a described later is formed). It can be used for orientation recognition.

  The plurality of lands 16 are arranged in an array on the lower surface 3 b of the wiring board 3. An opening 17 is formed next to or in the vicinity of each land 16. Also, solder balls (ball electrodes, protruding electrodes, electrodes, external terminals, external connection terminals) 6 are connected (formed) to each land 16. For this reason, a plurality of solder balls 6 are arranged in an array on the lower surface 3 b of the wiring board 3. The solder ball 6 can function as an external terminal (external connection terminal) of the semiconductor device 1. For this reason, the semiconductor device 1 of the present embodiment has a plurality of external connection terminals (here, solder balls 6) formed on the plurality of lands 16 on the lower surface 3 b of the wiring board 3. Accordingly, the plurality of electrodes 2 a of the semiconductor chip 2 are electrically connected to the plurality of connection terminals 15 of the wiring board 3 through the plurality of bonding wires 4, and further, the wiring board 3 through the conductor layer 12 of the wiring board 3. The plurality of lands 16 and the plurality of solder balls 6 connected to the plurality of lands 16 are electrically connected. Although the number of solder balls 6 in FIG. 2 and the number of connection terminals 15 in FIG. 6 do not match, FIGS. 1 to 6 schematically show the structure of the semiconductor device 1. The number of solder balls 6 and the number of connection terminals 15 in 1 can be variously changed as necessary, and the number of solder balls 6 and the number of connection terminals 15 in the semiconductor device 1 can be made the same. It can also be made. Also, the solder balls 6 that are not electrically connected to the electrodes 2a of the semiconductor chip 2 can be used for heat dissipation. The same applies to an LGA (Land Grid Array) structure in which a conductor land not connected to a solder ball is used as an external connection terminal.

  Solder resist layers 14 are formed on the upper and lower surfaces of the wiring board 3. The solder resist layer 14 formed on the upper surface 3 a of the wiring board 3 has an opening 19 a for exposing the connection terminals 15. . The bonding wire 4 is connected to the connection terminal 15 exposed from the opening 19 a of the solder resist layer 14. In order to facilitate or ensure the connection of the bonding wire 4 to the connection terminal 15, the upper surface of the connection terminal 15 exposed from the opening 19 a of the solder resist layer 14 (the connection surface of the bonding wire 4) is a gold plating layer (or A nickel plating layer (lower layer side) and a gold plating layer (upper layer side) are formed. The solder resist layer 14 formed on the lower surface 3 b of the wiring board 3 has an opening 19 b for exposing the land 16. Solder balls 6 are connected to the lands 16 exposed from the openings 19b of the solder resist layer 14.

  The sealing resin (sealing resin portion, sealing portion, sealing body) 5 is made of, for example, a resin material such as a thermosetting resin material, and can include a filler. For example, the sealing resin 5 can be formed using an epoxy resin containing a filler. The sealing resin 5 is formed on the upper surface 3 a of the wiring substrate 3 so as to cover the semiconductor chip 2 and the bonding wires 4. That is, the sealing resin 5 is formed on the upper surface 3 a of the wiring substrate 3 and seals the semiconductor chip 2 and the bonding wires 4. The semiconductor chip 2 and the bonding wire 4 are sealed and protected by the sealing resin 5.

  Next, a manufacturing method (manufacturing process) of the semiconductor device according to the present embodiment will be described.

  FIG. 7 is a manufacturing process flow chart showing the manufacturing process of the semiconductor device of the present embodiment. 8 to 14 are explanatory views (sectional views) of the manufacturing process of the semiconductor device of the present embodiment. 8 to 14 show cross-sections of the respective process steps of the same region (region straddling the two semiconductor device regions 32a), and are cross-sectional views for easy understanding of the drawings, but hatching is omitted. Yes.

  In the present embodiment, individual semiconductor devices 1 are manufactured using a multi-piece wiring substrate (wiring substrate base) 31 formed by connecting a plurality of wiring substrates 3 (semiconductor device regions 32a) in an array. To do. The wiring board 31 is a base body of the wiring board 3. The semiconductor device is obtained by cutting the wiring board 31 in a cutting process to be described later and separating it into each semiconductor device region (substrate region, unit substrate region, device region) 32a. This corresponds to one wiring board 3. The wiring substrate 31 has a configuration in which a plurality of semiconductor device regions 32a from which one semiconductor device 1 is formed are arranged in a matrix.

  First, as shown in FIG. 8, a wiring board 31 is prepared (step S1). The structural features of the wiring board 31 will be described in detail later. In step S1, the wiring substrate 31 includes a plurality of semiconductor device regions 32a, each of which is a unit substrate region from which the semiconductor device 1 is manufactured, and includes an upper surface 31a (first main surface) and an opposite side of the upper surface 31a. A wiring board 31 having a lower surface 31b (second main surface), a plurality of connection terminals 15 on the upper surface 31a of each semiconductor device region 32a, and a plurality of lands 16 on the lower surface 31b of each semiconductor device region 32a is prepared. The

  After preparing the wiring board 31 in step S1, a die bonding process is performed, and as shown in FIG. 9, the semiconductor chip 2 is bonded to the adhesive material 8 on each semiconductor device region 32a of the upper surface 31a of the wiring board 31. Are mounted and bonded (die bonding, chip mounting) (step S2). As the adhesive 8, a paste adhesive, a film adhesive, or the like can be used.

  Next, as shown in FIG. 10, a wire bonding step is performed to electrically connect each electrode 2 a of the semiconductor chip 2 and the connection terminal 15 formed on the wiring substrate 31 corresponding thereto through the bonding wire 4. (Step S3). That is, the plurality of connection terminals 15 of each semiconductor device region 32 a on the upper surface 31 a of the wiring substrate 31 and the plurality of electrodes 2 a of the semiconductor chip 2 bonded on the semiconductor device region 32 a are electrically connected via the plurality of bonding wires 4. Connect.

  Next, as shown in FIG. 11, resin sealing is performed by a molding process (resin molding process, for example, transfer molding process) so that the semiconductor chip 2 and the bonding wires 4 are covered on the wiring substrate 31. (Sealing part, collective sealing part) 5a is formed, and the semiconductor chip 2 and the bonding wire 4 are sealed with the sealing resin 5a (step S4).

  In the molding process of step S4, collective sealing (collective molding) is performed in which the plurality of semiconductor device regions 32a on the upper surface 31a of the wiring substrate 31 are collectively sealed with the sealing resin 5a. That is, the sealing resin 5a is formed on the whole of the plurality of semiconductor device regions 32a on the upper surface 31a of the wiring substrate 31 so as to cover the semiconductor chip 2 and the bonding wires 4 in those semiconductor device regions 32a. For this reason, the sealing resin 5 a is formed so as to cover the whole of the plurality of semiconductor device regions 32 a on the upper surface 31 a of the wiring substrate 31. The sealing resin 5a is made of, for example, a resin material such as a thermosetting resin material, and may include a filler. For example, the sealing resin 5a can be formed using an epoxy resin containing a filler. With the wiring substrate 31 and the sealing resin 5a on the wiring substrate 31 (including the semiconductor chip 2 and the bonding wire 4 sealed in the sealing resin 5a), a sealing body (collective sealing body, assembly) 41 is formed. It is formed. That is, a structure in which the sealing resin 5 a that is a batch sealing portion is formed on the multi-cavity wiring substrate 31 is referred to as a sealing body 41.

  Next, as shown in FIG. 12, the solder balls 6 are connected (bonded and formed) to the lands 16 on the lower surface 31b of the wiring board 31 (step S5). In the solder ball 6 connecting step in step S5, for example, the solder balls 6 are disposed (mounted) on the plurality of lands 16 of each semiconductor device region 32a of the lower surface 31b of the wiring board 31 with the lower surface 31b of the wiring board 31 facing upward. The solder balls 6 and the lands 16 on the lower surface 31b of the wiring board 31 can be joined together by temporarily fixing with a flux or the like, and performing reflow processing (solder reflow processing, heat treatment) to melt the solder. Thereafter, if necessary, a cleaning process can be performed to remove the flux and the like attached to the surface of the solder ball 6. In this way, the solder balls 6 as the external terminals (external connection terminals) of the semiconductor device 1 are joined (formed).

  In the present embodiment, the case where the solder ball 6 is joined as the external terminal of the semiconductor device 1 has been described. However, the present invention is not limited to this. External terminals (bump electrodes, solder bumps) made of solder of the semiconductor device 1 can also be formed by supplying solder to the semiconductor device 1. In this case, solder is supplied to the plurality of lands 16 of the respective semiconductor device regions 32a on the lower surface of the wiring substrate 31, and then solder reflow processing is performed, so that external terminals (bumps) made of solder are respectively formed on the plurality of lands 16. Electrodes, solder bumps) can be formed.

  The material of the external terminal (here, solder ball 6) of the semiconductor device 1 can be lead-containing solder or lead-free solder that does not contain lead, and the external terminal (bump electrode) of the semiconductor device 1 by plating. Can also be formed.

  As described above, in step S5, the external connection terminals (here, the solder balls 6) are formed on the plurality of lands 16 of the respective semiconductor device regions 32a on the lower surface 31b of the wiring board 31.

  Next, marking is performed as necessary, and a mark such as a product number is attached to the upper surface (front surface) 5b of the sealing resin 5a (step S6). In step S6, for example, a laser mark for marking with a laser can be performed, but an ink mark for marking with ink can also be performed. Alternatively, the solder ball 6 connecting step in step S5 may be performed after the order of the solder ball 6 connecting step in step S5 and the marking step in step S6 are interchanged and the marking step in step S6 is performed. Moreover, if unnecessary, the marking process of step S6 can also be skipped.

  Next, as shown in FIG. 13, using a dicing blade (dicing saw, blade) 43 or the like, along dicing regions (dicing lines, boundaries between the semiconductor device regions 32a) 32b between the semiconductor device regions 32a. Then, dicing (cutting, cutting) is performed from the lower surface 31b side of the wiring board 31 to cut (divide) the sealing body 41 (the wiring board 31 and the sealing resin 5a) (step S7). For example, in step S7, the dicing process by the dicing blade 43 can be performed in a state where the upper surface 5b of the sealing resin 5a is attached to the package fixing tape (fixing tape) 42 and the sealing body 41 is fixed. Thereby, as shown in FIG. 14, the sealing body 41 (the wiring substrate 31 and the sealing resin 5a) is cut along the dicing region 32b, and each semiconductor device region 32a (CSP region) is individually ( The separated semiconductor device 1 (CSP) is cut and separated (divided). That is, the sealing body 41 (the wiring board 31 and the sealing resin 5a) is cut and divided into each semiconductor device region 32a, and the semiconductor device 1 is formed from each semiconductor device region 32a.

  Thus, the semiconductor device 1 as shown in FIGS. 1 to 6 can be manufactured by cutting and dividing. The wiring substrate 31 cut and separated (divided) into each semiconductor device region 32a corresponds to the wiring substrate 3, and the sealing resin 5a cut and separated (divided) into each semiconductor device region 32a corresponds to the sealing resin 5. To do.

  Next, the wiring board 31 used for manufacturing the semiconductor device 1 of the present embodiment will be described in more detail.

  FIG. 15 is a top view (overall plan view) showing the entire wiring board 31 used for manufacturing the semiconductor device 1 of the present embodiment, and FIG. 16 is a bottom view (overall plan view) showing the entire wiring board 31. ). FIG. 17 is a partially enlarged top view (main part plan view) of the wiring board 31, and FIG. 18 is a partial enlarged bottom view (main part plan view) of the wiring board 31. For example, a cross-sectional view taken along line BB in FIGS. 15 and 17 corresponds to FIG. 15 to 18, the dicing region 32b between the semiconductor device regions 32a is schematically shown by dotted lines. FIG. 19 is a cross-sectional view of the wiring board 31 and substantially corresponds to the cross section taken along the line CC of FIGS. 15 and 17. FIG. 20 is a top perspective view of the wiring substrate 31, and corresponds to the wiring board 31 corresponding to the solder resist layer 14 that is not shown (that is, the solder resist layer 14 is seen through). FIG. 21 is a perspective view of the lower surface of the wiring board 31, and corresponds to the wiring board 31 corresponding to the solder resist layer 14 that is not shown (that is, the solder resist layer 14 is seen through). 15 and 16, the number of semiconductor device regions 32a arranged in the X direction is seven, and in FIGS. 17, 18, 20, and 21, they are arranged in the X direction. Although the number of semiconductor device regions 32a is six, in reality, the number of both coincides.

  As shown in FIGS. 15 to 21, the wiring substrate 31 used in the present embodiment includes a plurality of semiconductor device regions 32 a that are unit substrate regions from which the semiconductor device 1 is manufactured. The semiconductor device regions 32a are arranged in a matrix (array or matrix) in the X and Y directions. Here, the X direction and the Y direction intersect each other (preferably orthogonally). Note that the number of semiconductor device regions 32a arranged in the X direction and the Y direction in one wiring substrate 31 can be changed as necessary.

  Since the semiconductor device regions 32a are arranged in a matrix in the X direction and the Y direction, a dicing region (dicing line, a boundary portion between the semiconductor device regions 32a) 32b between the semiconductor device regions 32a in the wiring substrate 31 is X. A plurality of each extend in the direction and the Y direction. In the dicing process of step S7, the sealing body 41 (the wiring substrate 31 and the sealing resin 5a is formed from the lower surface 31b side of the wiring substrate 31 along the dicing region (dicing line) 32b extending in the X direction and the Y direction. ). That is, in the dicing process of step S7, the sealing body 41 is diced (cut) from the lower surface 31b side of the wiring board 31 along the X direction and the Y direction.

  Various methods can be used to manufacture the wiring substrate 31. For example, conductor layers 12a and 12b (patterns) are formed on the upper surface 11a and the lower surface 11b of the base material layer 11, and then through holes (the opening 17 and a through hole 38 described later) are formed in the base material layer 11. After forming a conductor layer (the conductor layer 12c and a conductor layer 37c described later) on the side wall of the through hole by a plating method or the like, a solder resist is formed on the upper surface 11a and the lower surface 11b of the base material layer 11 by a printing method or the like. By forming the layer 14, the wiring substrate 31 can be manufactured. Alternatively, after forming a through hole (the opening 17 or a through hole 38 to be described later) in the insulating base material layer 11 as the core material, the conductor layer 12 is formed by a plating method or the like. The wiring substrate 31 can be manufactured by forming the solder resist layer 14 on the upper surface 11a and the lower surface 11b by a printing method or the like.

  As shown in FIG. 20, a patterned conductor layer 12 a is formed on the upper surface 11 a of the base material layer 11 constituting the wiring board 31. The pattern of the conductor layer 12 a is the connection terminal 15. Conductor pattern, power supply line (plating wiring) 33a, and through-hole land 37a. Further, although a conductor pattern for the opening 17 and a pattern such as a lead-out wiring for connecting the conductor pattern to the connection terminal 15 are also formed, the illustration is omitted in FIG. 20 for easy understanding of the drawing. The through-hole land 37a will be described in detail later.

  In addition, as shown in FIG. 21, a patterned conductor layer 12b is formed on the lower surface 11b of the base material layer 11 constituting the wiring board 31, and the pattern of the conductor layer 12b is 16 conductor patterns, power supply lines (plated wiring) 33b, target marks 34, and through-hole lands 37b. The target mark 34 and the through-hole land 37b will be described in detail later.

  Therefore, the connection terminal 15, the feed line 33 a, and the through-hole land 37 a are formed by the same layer conductor pattern (conductor layer 12 a) formed on the upper surface 11 a of the substrate layer 11. The land 16, the feeder line 33b, the target mark 34, and the through-hole land 37b are formed by the same-layer conductor pattern (conductor layer 12b) formed on the lower surface 11b.

  Since electrolytic plating is used to form the conductor layers 12a and 12b themselves and the surface films of the connection terminals 15 and the lands 16, feed lines 33a and 33b are formed on the upper surface 11a and the lower surface 11b of the base material layer 11, respectively. The electrolytic plating layer can be formed by supplying a predetermined potential (electric power) through the feeder lines 33a and 33b.

  The power supply line 33 is formed on the upper surface 11a of the base material layer 11 constituting the wiring board 31 so as to extend along the dicing area 32b between the semiconductor device areas 32a. Branching from a portion extending along the line 32 b is connected to the conductor pattern for each connection terminal 15. The power supply line 33b is formed on the lower surface 11b of the base material layer 11 constituting the wiring board 31 so as to extend along the dicing area 32b between the semiconductor device areas 32a. Branching from the portion extending along the line 32 b is connected to the conductor pattern for each land 16.

  As shown in FIGS. 16, 18 and 21, the wiring substrate 31 used in the present embodiment has a target mark (target pattern, dicing) for each dicing area 32b (dicing line) on the lower surface 31b of the wiring substrate 31. Mark, dicing target, alignment pattern, alignment mark) 34 is formed. The target mark 34 is formed on the lower surface 31b of the wiring board 31 at a position on the extension of the dicing area (dicing line) 32b between the semiconductor device areas 32a.

  The target mark 34 is an alignment mark for positioning a dicing position (cutting position) when the sealing body 41 is diced (cut) by the dicing blade 43 from the lower surface 31b side of the wiring board 31 in the dicing process of step S7. Target mark). That is, the target mark 34 is a target mark for positioning the cutting position of the wiring board 31. In the dicing process of step S7, the dicing position (cutting position) is based on the target mark 34 on the lower surface 31b of the wiring board 31. Then, the sealing body 41 can be diced (cut) by the dicing blade 43 from the lower surface 31 b side of the wiring board 31. It is more preferable if the target marks 34 are formed at positions on both ends of one dicing area 32b (dicing line), and in this case, in step S7, on both ends of the dicing area 32b (dicing line). Can be diced (cut) along the dicing area (dicing line) 32b. However, in this embodiment, although details will be described later, an operation for correcting the cutting position based on the target mark 34 is performed.

  The target mark 34 is configured by a conductor layer 12b (a conductor pattern made of) formed on the lower surface 11b of the base material layer 11 (the lower surface 31b of the wiring board 31). For this reason, the target mark 34 is formed by the conductor pattern for the land 16 and the like and the same layer conductor pattern (conductor layer 12b) formed in the same process. As described above, the solder resist layer 14 is formed on the lower surface 11 b of the base material layer 11 so as to cover the conductor layer 12 b, but the target mark 34 is exposed from the opening 35 of the solder resist layer 14. .

  In the dicing process of step S7, since the sealing body 41 is diced (cut) from the lower surface 31b side of the wiring substrate 31, the target mark 34 must be provided on the lower surface 31b side of the wiring substrate 31.

  Furthermore, the wiring board 31 used in the present embodiment has a pattern deviation detection unit 36 as shown in FIGS.

  FIG. 22 is a partially enlarged plan view of FIG. 21, and shows a region near the target mark 34 on the lower surface 31 b of the wiring board 31. In FIG. 22, the solder resist layer 14 is not shown (that is, the solder resist layer 14 is seen through) as in FIG. 21. FIG. 23 is a cross-sectional view of a main part of the wiring board 31 and corresponds to a cross section taken along line EE in FIG.

  Each pattern shift detection unit 36 includes through-hole lands (conductor patterns) 37a formed on the upper surface 11a of the base material layer 11 (upper surface 31a of the wiring substrate 31), and the lower surface 11b of the base material layer 11 (of the wiring substrate 31). It has through-hole lands (conductor patterns) 37b formed in the lower surface 31b) and through-holes (openings, vias, through-holes) 38 formed in the base material layer 11.

  The through-hole land 37a (second conductor pattern) on the upper surface 31a side of the wiring board 31 is formed by the pattern (conductor pattern) of the conductor layer 12a formed on the upper surface 11a of the base material layer 11 (upper surface 31a of the wiring board 31). It is configured. For this reason, the through-hole land 37a on the upper surface 31a side of the wiring board 31 is formed by the conductor pattern for the connection terminal 15 and the conductor pattern in the same layer formed in the same process as the feeder line 33a.

  The through-hole land 37b (first conductor pattern) on the lower surface 31b side of the wiring board 31 is formed by the pattern (conductor pattern) of the conductor layer 12b formed on the lower surface 11b of the base material layer 11 (lower surface 31b of the wiring board 31). It is configured. For this reason, the through-hole land 37b on the lower surface 31b side of the wiring board 31 is formed by the same-layer conductor pattern formed in the same process as the conductor pattern for the land 16, the feeder line 33b, and the target mark 34. Further, it is more preferable that the through-hole lands 37b and the target marks 34 are formed in a continuous pattern.

  On the upper surface 31 a and the lower surface 31 b of the wiring substrate 31, the through-hole lands 37 a and 37 b are covered with the solder resist layer 14.

  In each pattern misalignment detection unit 36, the through hole land 37a and the through hole land 37b are formed at positions corresponding to each other, and the through hole land 37b is formed at a position corresponding to the through hole land 37b on the upper surface 31a of the wiring board 31. Hall lands 37a are provided. That is, the through-hole lands 37a on the upper surface 31a side of the wiring board 31 and the through-hole lands 37b on the lower surface 31b side of the wiring board 31 are formed in positions and shapes that coincide (overlap) in plan view. ing. However, as will be described later, in actuality, a deviation may occur in the planar positions of the through-hole land 37a and the through-hole land 37b. It is more preferable that the through-hole lands 37a and 37b are formed in a circular pattern.

  In each pattern deviation detection unit 36, the through hole 38 (first opening) is formed at a position overlapping the through hole land 37a and the through hole land 37b in a planar manner. When the through-hole lands 37a and 37b have a circular pattern, the through-hole 38 is formed in the plane of the circular pattern.

  In the wiring board 31, a pattern deviation detection unit 36 is provided in the vicinity of the target mark 34. That is, on the lower surface 31 b of the wiring substrate 31 (the lower surface 11 b of the base material layer 11), the through-hole lands 37 b constituting the pattern deviation detection unit 36 are disposed in the vicinity of the target mark 34. The pattern deviation detection unit 36 (through-hole lands 37a and 37b and through-hole 38) is preferably arranged in a dicing area (dicing line) 32b of the wiring board 31. Accordingly, on the lower surface 31b of the wiring substrate 31 (the lower surface 11b of the base material layer 11), through-hole lands 37b are formed at positions almost at both ends of one dicing area (dicing line) 32b, respectively. It is preferable that the target mark 34 is formed in the vicinity of 37b and on the extension of the dicing region (dicing line) 32b. That is, at least two pattern deviation detectors 36 and two target marks 34 are provided for each dicing area (dicing line) 32b of the wiring board 31, and these pattern deviation detectors 36 and target marks 34 are respectively provided. It is preferable to arrange on the dicing area (dicing line) 32b or on the extension thereof.

  Further, by forming a part of the feed lines 33a and 33b into a circular wide pattern, the through-hole lands 37a and 37b can be formed, whereby the feed lines 33a and 33b are arranged along the dicing region 32b. While extending, the through-hole lands 37a and 37b can be arranged in the dicing region 32b. In this case, the feed line 33a and the through hole land 37a are formed in a continuous pattern, and the feed line 33b and the through hole land 37b are formed in a continuous pattern.

  The through-hole 38 includes a through-hole land 37a and a through-hole land 37b that constitute the pattern deviation detection unit 36 to which the through-hole 38 belongs, and a base material layer between the through-hole land 37a and the through-hole land 37b. 11, and the interior of the through hole 38 is filled (filled) with a solder resist layer 14 (insulator, insulating material).

  When the conductor layer 12 c is formed on the side wall of the opening 17, the same conductor layer 37 c as the conductor layer 12 c is formed on the side wall of the through hole 38. For this reason, the conductor layer 37c is formed on the side wall of the through hole 38, and a portion not filled with the conductor layer 37c in the through hole 38 is filled (filled) with the solder resist layer 14. . The conductor layer 12c on the side wall of the opening 17 is necessary for electrical connection between the connection terminal 15 and the land 16, but the through hole 38 is formed on the upper surface 11a side of the base material layer 11 as will be described later. Therefore, the conductor layer 37c on the side wall of the through hole 38 does not have to be formed. However, when the pattern of the through-hole land 37a is formed continuously with the pattern of the power supply line 33a and the pattern of the through-hole land 37b is formed continuously with the pattern of the power supply line 33b, the pattern is formed on the side wall of the through-hole 38. If the conductor layer 37c is formed, the feeder line 33a and the feeder line 33b can be electrically connected via the conductor layer 37c on the side wall of the through hole 38.

In each pattern deviation detection unit 36, the planar dimension (diameter T ₂ ) of the through hole 38 is smaller than the planar dimension (diameter T ₁ ) of the through-hole lands 37a and 37b (T ₂ <T ₁ ). Further, in each pattern misalignment detection unit 36, the center position of the through hole 38, the center position of the through hole land 37a, and the center position of the through hole land 37b are formed to coincide with each other in design. As will be described later, in practice, a deviation may occur. The planar shape of the through hole 38 is preferably a circular shape.

  In the wiring board 31, the pattern deviation detection unit 36 detects a deviation between the conductor pattern on the upper surface 31 a side of the wiring board 31 (pattern of the conductor layer 12 a) and the conductor pattern on the lower surface 31 b side of the wiring board 31 (pattern of the conductor layer 12 b). This is provided for detecting (pattern deviation). In the present embodiment, the pattern deviation detection unit 36 (that is, the through-hole lands 37a and 37b and the through-hole 38) is used to form a conductor pattern on the upper surface 31a side of the wiring board 31 and a conductor pattern on the lower surface 31b side of the wiring board 31. Deviation (pattern deviation) is detected, and using the detected deviation amount (pattern deviation amount), the dicing position (cutting position of the wiring board 31) in the dicing process in step S7 is corrected.

  Here, unlike the present embodiment, the pattern deviation detection unit 36 is not used to detect a deviation (pattern deviation) between the conductor pattern on the upper surface 31 a side of the wiring board 31 and the conductor pattern on the lower surface 31 b side of the wiring board 31. The problem of will be described.

  When dicing is performed from the lower surface 31b side of the wiring substrate 31 in step S7, dicing can be performed based on the target mark 34 formed on the lower surface 31b of the wiring substrate 31. Since the target mark 34 formed on the lower surface 31b of the wiring substrate 31 is formed by a conductor pattern (pattern of the conductor layer 12b) on the lower surface 31b side of the wiring substrate 31, another conductor pattern on the lower surface 31b side of the wiring substrate 31 is formed. The relative position with respect to the conductor pattern (for example, the conductor pattern for the land 16) can be formed with high accuracy.

  However, the target mark 34 formed on the lower surface 31b of the wiring board 31 is likely to deviate from the conductor pattern (pattern of the conductor layer 12a) on the upper surface 31a side of the wiring board 31 and is formed on the lower surface 31b of the wiring board 31. The accuracy of the relative position between the target mark 34 and the conductor pattern (for example, the connection terminal 15) on the upper surface 31a side of the wiring board 31 tends to be low. This is because, for example, when forming a conductor pattern on the upper surface 31a side of the wiring substrate 31 (pattern of the conductor layer 12a) and a conductor pattern on the lower surface 31b side of the wiring substrate 31 (pattern of the conductor layer 12b), This is because the relative positional accuracy of the conductor pattern on the upper surface 31a side and the conductor pattern on the lower surface 31b side of the wiring substrate 31 is likely to be lowered by performing different exposure processes using a mask.

  Therefore, even if the sealing body 41 is diced from the lower surface 31b side of the wiring substrate 31 based on the target mark 34 formed on the lower surface 31b of the wiring substrate 31, a conductor pattern on the upper surface 31a side of the wiring substrate 31, for example, The relative positional accuracy of the dicing position with respect to the connection terminal 15 is lowered. When the dicing position is shifted, there is a possibility that the connection terminals 15 and the bonding wires 4 are exposed on the cut surface of the sealing resin 5a, that is, the side surface of the sealing resin 5 of the manufactured semiconductor device. Reduce yield. In order to prevent the connection terminals 15 and the bonding wires 4 from being exposed from the cut surface of the sealing resin 5a, that is, the side surface of the sealing resin 5 of the manufactured semiconductor device, even if the dicing position is shifted, the dicing region 32b is used. However, this increases the size of the semiconductor device.

  Therefore, in the present embodiment, by using the wiring substrate 31 having the pattern deviation detection unit 36 as described above, the conductor pattern on the upper surface 31a side of the wiring substrate 31 and the conductor pattern on the lower surface 31b side of the wiring substrate 31 are used. A deviation (pattern deviation) is detected.

  FIG. 24 is an explanatory diagram (flowchart) showing a process for detecting a pattern deviation on the upper surface 31a side and the lower surface 31b side of the wiring board 31 and a method for correcting the dicing position based on the detected pattern deviation. FIG. 25 is a bottom view of the main part of the wiring board 31 when a deviation (pattern deviation) occurs between the conductor pattern on the upper surface 31a side of the wiring board 31 and the conductor pattern on the lower surface 31b side of the wiring board 31. FIG. 25 and FIG. 26 show regions corresponding to each other. 25 and FIG. 26 show regions substantially corresponding to FIG. 22, but in FIGS. 25 and 26, the patterns of the conductor layers 12a and 12b (here, the feed lines 33a and 33b, the target mark 34). The through holes lands 37a, 37b) and the through holes 38 are shown in a planar arrangement (layout), and other components are not shown. FIG. 27 is a diagram in which the planar arrangement (layout) of the through-hole lands 37a is superimposed on FIG. 25, and the through-hole lands 37a when the wiring board 31 is seen through from the lower surface 31a side are indicated by dotted lines. Yes (however, in FIG. 27, illustration of the right region of FIG. 25 is omitted). FIG. 28 is a cross-sectional view of the main part of the wiring board 31 when a pattern shift occurs between the upper surface 31a side and the lower surface 31b side of the wiring board 31 as shown in FIGS. Corresponds to a cross-sectional view of the line.

  In each pattern deviation detection unit 36, a through hole land 37a is provided at a position corresponding to the through hole land 37b on the upper surface 31a of the wiring board 31, and the center position of the through hole 38 and the through hole land 37a are arranged. The center position and the center position of the through-hole land 37b are formed to coincide with each other in design. If the pattern deviation detector 36 is formed as designed, the structure shown in FIGS. 22 and 23 is obtained. However, in the actually manufactured wiring board 31, as shown in FIGS. 25 to 28, the conductor pattern on the upper surface 31 a side (pattern of the conductor layer 12 a) of the wiring board 31 and the conductor pattern on the lower surface 31 b side of the wiring board 31. Deviation may occur in the (pattern of the conductor layer 12b).

  Therefore, a deviation (pattern deviation) between the conductor pattern on the upper surface 31a side of the wiring board 31 and the conductor pattern on the lower surface 31b side of the wiring board 31 is detected as follows.

First, on the upper surface 31a of the wiring board 31, the amount of displacement of the planar position between the through-hole land 37a and the through-hole 38 constituting each pattern displacement detector 36 (this amount of displacement is hereinafter referred to as a first amount of displacement D). ₁ ) (step S11).

In step S11, for example, an image recognition device or the like is used for the pattern deviation detection unit 36 for dicing in the X direction (the pattern deviation detection unit 36 formed at both ends of the dicing area 32b extending in the X direction). Accordingly, as shown in FIG. 26, for detecting the center position of the through hole land 37a, a first shift amount D ₁ the displacement amount in the Y direction between the center position of the through hole 38. Here, assuming that the coordinates of the center position of the through-hole land 37a are (X ₁ , Y ₁ ) and the coordinates of the center position of the through-hole 38 are (X ₂ , Y ₂ ), D ₁ = Y ₂ −Y ₁ Can be represented. The coordinates (X _n , Y _n ) indicate that the coordinate in the X direction is X _n and the coordinate in the Y direction is Y _n .

In step S11, for example, an image recognition device is used for the Y-direction dicing pattern deviation detector 36 (pattern deviation detectors 36 formed at both ends of the dicing area 32b extending in the Y direction). it allows to detect the center position of the through hole land 37a, a shift amount D ₁ the displacement amount in the X direction first between the center position of the through hole 38 to be used. Here, assuming that the coordinates of the center position of the through-hole land 37a are (X ₁ , Y ₁ ) and the coordinates of the center position of the through-hole 38 are (X ₂ , Y ₂ ), D ₁ = X ₂ −X ₁ Can be represented.

Then, on the lower surface 31 b of the wiring board 31, the amount of displacement of the planar position between the through-hole lands 37 b and the through-holes 38 constituting each pattern displacement detector 36 (this amount of displacement is hereinafter referred to as a second amount of displacement D). ₂ ) (step S12).

In step S12, for example, an image recognition device or the like is used for the pattern misalignment detection unit 36 for dicing in the X direction (the pattern misalignment detection unit 36 formed at both ends of the dicing region 32b extending in the X direction). Accordingly, as shown in FIG. 25, the center position of the through hole land 37b, the displacement amount in the Y direction between the center position of the through hole 38, is detected as the second shift amount D _2. Here, assuming that the coordinates of the center position of the through hole land 37b are (X ₃ , Y ₃ ) and the coordinates of the center position of the through hole 38 are (X ₂ , Y ₂ ), D ₂ = Y ₃ −Y ₂ Can be represented.

In step S12, for example, an image recognition device is used for the Y-direction dicing pattern deviation detector 36 (pattern deviation detectors 36 formed at both ends of the dicing area 32b extending in the Y direction). it allows the center position of the through hole land 37b, the X-direction displacement amount between the center position of the through hole 38, is detected as the second shift amount D ₂ is used. Here, assuming that the coordinates of the center position of the through hole land 37b are (X ₃ , Y ₃ ) and the coordinates of the center position of the through hole 38 are (X ₂ , Y ₂ ), D ₂ = X ₃ −X ₂ Can be represented.

  Note that, on both the upper surface 31a and the lower surface 31b of the wiring board 31, the direction toward one of the four side surfaces of the wiring substrate 31 is the direction in which the coordinate in the X direction increases, and intersects (orthogonal) the side surface. The direction toward the same other side surface is the direction in which the coordinate in the Y direction increases. Accordingly, when the wiring substrate 31 is seen through, the directions in which the X-direction coordinates increase on the upper surface 31a and the lower surface 31b of the wiring substrate 31 match, and the Y-direction coordinates on the upper surface 31a and the lower surface 31b of the wiring substrate 31. The direction in which increases is consistent.

  Since the through-hole lands 37a and 37b are covered with the solder resist layer 14 on the upper surface 31a and the lower surface 31b of the wiring board 31, the base material (through-hole lands 37a and 37b and through-holes) is used as the material of the solder resist layer 14. It is preferable to select a material capable of observing the pattern shape of 38) (that is, a material through which the underlying pattern shape can be seen). Thereby, in steps S11 and S12, the positions of the through-hole lands 37a and 37b and the through-hole 38 can be accurately recognized through the solder resist layer 14 (see through).

  Further, even if the pattern of the through hole 38 recognized in steps S11 and S12 is a pattern defined by the side wall of the base material layer 11, the solder resist layer 14 filling the through hole lands 37a and 37b and the through hole 38 is filled. Or a pattern defined by an interface (boundary) between the conductor layer 37c and the solder resist layer 14 filling the through hole 38. In any case, the center position of the through hole 38 is substantially the same.

Steps S11, S12 and the first deviation amount D ₁ performed after detecting the second shift amount D _2, from a first shift amount D ₁ and the second shift amount D ₂ detected, the pattern shift detection A displacement amount of the planar position between the through-hole land 37a and the through-hole land 37b constituting the portion 36 (hereinafter referred to as a _third displacement amount D3) is obtained (step S13).

In step S13, with respect to the pattern shift detection unit 36 for the X-direction of the dicing, as can be seen from FIGS. 27 and 28, the first shift amount D ₁ and the second sum of the shift amounts D _2, A deviation amount in the Y direction between the center position of the through-hole land 37a and the center position of the through-hole land 37b can be calculated as a _third deviation amount D3 (that is, D ₃ = D ₁ + D). ₂ ). Here, if the coordinates of the center position of the through-hole land 37b are (X ₃ , Y ₃ ) and the coordinates of the center position of the through-hole land 37a are (X ₁ , Y ₁ ), D ₃ = Y ₃ −Y ₁ can be expressed. This is because the coordinates (X ₂ , Y ₂ ) of the through hole 38 are the same on the upper surface 31 a and the lower surface 31 b of the wiring substrate 31, so the coordinates of the center position of the through hole 38 are the upper surface 31 a and the lower surface 31 b of the wiring substrate 31. And (X ₂ , Y ₂ ) common to each other, D ₂ = Y ₃ −Y ₂ and D ₁ = Y ₂ −Y ₁ as described above, so that D ₂ + D ₁ = (Y ₃ −Y _2). ) + (Y ₂ −Y ₁ ) = Y ₃ −Y ₁ = D ₃ .

In step S13, with respect to the pattern shift detection unit 36 for Y-direction of the dicing, the first shift amount D ₁ and the second sum of the shift amounts D _2, and the center position of the through hole land 37a the X-direction displacement amount between the center position of the through hole land 37b, it is possible to calculate a third deviation amount _{D 3} (i.e. _{D 3 = D 1 + D 2} ). Here, if the coordinates of the center position of the through-hole land 37b are (X ₃ , Y ₃ ) and the coordinates of the center position of the through-hole land 37a are (X ₁ , Y ₁ ), D ₃ = X ₃ −X ₁ can be expressed. This is because the coordinates (X ₂ , Y ₂ ) of the through hole 38 are the same on the upper surface 31 a and the lower surface 31 b of the wiring substrate 31, so the coordinates of the center position of the through hole 38 are the upper surface 31 a and the lower surface 31 b of the wiring substrate 31. And (X ₂ , Y ₂ ) common to each other, D ₂ = X ₃ −X ₂ and D ₁ = X ₂ −X ₁ as described above, so that D ₂ + D ₁ = (X ₃ −X _2). ) + (X ₂ −X ₁ ) = X ₃ −X ₁ = D ₃ is satisfied.

Thus, (corresponding to a first shift amount D ₁₎ displacement of the plane position of the through hole land 37a and a through hole 38 (center position), and the plane position of the land 37b and a through hole 38 for a through-hole ( detecting a deviation of the center position) (second corresponds to the deviation amount D _2), the thereby a planar position of the through hole land 37a (center position) and the plane position of the through hole land 37b (the center position) relative displacement (corresponding to the third shift amount D ₃₎ can be obtained. That is, since the through hole 38 is provided so as to pass through the base material layer 11 almost vertically, the position (X, Y coordinate) where the through hole 38 corresponds (matches) between the upper surface 31a and the lower surface 31b of the wiring substrate 31 is the same. That is formed in the position). Then, with reference to the through-hole 38, the displacement amount of the planar position between the through-hole land 37a on the upper surface 31a side of the wiring substrate 31 and the through-hole land 37b on the lower surface 31b side of the wiring substrate 31 (third displacement). The quantity D ₃ ) can be determined.

In the dicing process of step S7, dicing is performed from the lower surface 31b side of the wiring substrate 31, and at this time, dicing is performed based on the target mark 34 formed on the lower surface 31b of the wiring substrate 31. However, in the present embodiment, the cutting position determined based on the target mark 34 is corrected using the _third shift amount D3 obtained in step S13, and the wiring board 31 is corrected at the corrected cutting position. The sealing body 41 (the wiring substrate 31 and the sealing resin 5a) is cut (diced) from the lower surface 31b side.

Unlike this embodiment, if not corrected by the third shift amount D _3, in step S7, for example, by using a like image recognition device, on the extension of the ends of the dicing region 32b should be performed cutting operation The center coordinates of two existing target marks 34 are recognized (detected), and a line (line) 51 connecting (passing) the center coordinates of the two target marks 34 is used as a cutting position (dicing line) and sealed with a dicing blade 43. Cut the body 41. The target mark 34 and the through hole land 37b are provided close to the dicing region 32b or an extension thereof, and both are formed by the same pattern of the conductor layer 12b. 51 passes substantially over the center of the through-hole land 37b. When the sealing body 41 is cut using the line 51 as a cutting position (dicing line), as can be seen from FIG. 27, the cutting position (dicing position) with respect to the conductor pattern (pattern of the conductor layer 12a) on the upper surface 31a side of the wiring board 31. The relative positional accuracy of becomes low.

On the other hand, in the present embodiment, as described above, the through hole lands 37a and the wiring on the upper surface 31a side of the wiring board 31 in the pattern deviation detection unit 36 provided in the vicinity of the target mark 34 in steps S11 to S13. A relative deviation of the planar position of the through-hole land 37b on the lower surface 31b side of the substrate 31 (that is, the third deviation D ₃ ) is obtained. Therefore, in the dicing step of the step S7, by using the third shift amount D _3, to correct the cutting position based on the target mark 34, the sealing body from the lower surface 31a side of the wiring board 31 in the corrected cutting position 41 (Wiring substrate 31 and sealing resin 5a) are cut (step S14).

That is, in step S7 (that is, step S14), for the cutting operation in the X direction (cutting along the dicing region 32b extending in the X direction), the cutting operation is performed by using, for example, an image recognition device. The center coordinates of the two target marks 34 existing on the extension of both ends of the power dicing area (dicing line) 32b are recognized (detected), and a line 51 connecting (passing) the center coordinates of the two target marks 34 is determined. Then, the line 51, the third half of the deviation amount D ₃ (i.e. D _3/2) only shifted in the Y-direction cutting position after correction (dicing position, dicing line) and 52, the cutting position after the correction At 52, the wiring substrate 31 and the sealing resin 5 a (that is, the sealing body 41) are cut by the dicing blade 43.

Specifically, the cutting position can be corrected as follows. The center coordinates of the two target marks 34 existing on the extension of both ends of the dicing region 32b to be cut in the X direction are (X ₄ , Y ₄ ) and (X ₅ , Y ₅ ), respectively. Then, the third deviation amount D ₃ obtained for the pattern deviation detection unit 36 located in the vicinity of the target mark 34 having (X ₄ , Y ₄ ) as the center coordinates is defined as D ₃ a, and (X ₅ , Y The third deviation D ₃ obtained for the pattern deviation detector 36 located in the vicinity of the target mark 34 having ₅ ) as the center coordinate is defined as D ₃ b. In this case, the corrected cutting position 52 can be a line that passes through the coordinates (X ₄ , Y ₄ + D ₃ a / 2) and the coordinates (X ₅ , Y ₅ + D ₃ b / 2). Alternatively, the corrected cutting position 52 is a line that passes through coordinates (X ₄ , Y ₄ + (D ₃ a + D ₃ b) / 2) and coordinates (X ₅ , Y ₅ + (D ₃ a + D ₃ b) / 2). It can also be.

In step S7 (ie, step S14), for the cutting operation in the Y direction (cutting along the dicing area 32b extending in the Y direction), the cutting operation is performed by using, for example, an image recognition device. The center coordinates of the two target marks 34 existing on the extension of both ends of the power dicing area (dicing line) 32b are recognized (detected), and a line 51 connecting (passing) the center coordinates of the two target marks 34 is determined. Then, the line 51, the third half of the deviation amount D ₃ (i.e. D _3/2) only shifted in the X direction and the cutting position 52 of the corrected wiring board 31 and sealed at the cutting position 52 of the corrected The stop resin 5 a (that is, the sealing body 41) is cut by the dicing blade 43.

Specifically, the cutting position can be corrected as follows. The center coordinates of the two target marks 34 existing on the extension of both ends of the dicing area 32b to be cut in the Y direction are (X ₄ , Y ₄ ) and (X ₅ , Y ₅ ), respectively. Then, the third deviation amount D ₃ obtained for the pattern deviation detection unit 36 located in the vicinity of the target mark 34 having (X ₄ , Y ₄ ) as the center coordinates is defined as D ₃ a, and (X ₅ , Y The third deviation D ₃ obtained for the pattern deviation detector 36 located in the vicinity of the target mark 34 having ₅ ) as the center coordinate is defined as D ₃ b. In this case, the corrected cutting position 52 can be a line passing through the coordinates (X ₄ + D ₃ a / 2, Y ₄ ) and the coordinates (X ₅ + D ₃ b / 2, Y ₅ ). Alternatively, the corrected cutting position 52 is a line that passes through coordinates (X ₄ + (D ₃ a + D ₃ b) / 2, Y ₄ ) and coordinates (X ₅ + (D ₃ a + D ₃ b) / 2, Y ₅ ). It can also be.

The through-hole land 37a is formed by a conductor pattern (pattern of the conductor layer 12a) on the upper surface 31a side of the wiring board 31, and the through-hole land 37b is a conductor pattern (of the conductor layer 12b on the lower surface 31b side of the wiring board 31). Pattern). For this reason, the amount of displacement of the planar position between the through-hole land 37a and the through-hole land 37b detected by the pattern displacement detection unit 36 (that is, the third displacement amount D ₃ ) This reflects the relative deviation between the conductor pattern on the upper surface 31a side (pattern of the conductor layer 12a) and the conductor pattern on the lower surface 31b side of the wiring board 31 (pattern of the conductor layer 12b). In the present embodiment, the cutting position (corresponding to the line 51) based on the target mark 34 is corrected using the _third shift amount D3 detected by the pattern shift detector 36 near the target mark 34, and corrected. The sealing body 41 (the wiring board 31 and the sealing resin 5a) is cut at the cut position (corresponding to the cutting position 52). For this reason, the cutting position (corresponding to the cutting position 52) of the sealing body 41 in step S7 (step S14) reflects the deviation between the conductor pattern on the upper surface 31a side and the conductor pattern on the lower surface 31b side of the wiring board 31. Therefore, the relative positional accuracy of the cutting position of the sealing body 41 with respect to the conductor pattern (pattern of the conductor layer 12a) on the upper surface 31a side of the wiring board 31 can be increased.

Further, as described above, the line 51 connecting the two center coordinates of the target mark 34 third half of displacement amount D ₃ (i.e. D _3/2) by the X direction (or Y direction) staggered corrected In the case of the cutting position 52, the positional accuracy of the cutting position 52 can be improved with respect to both the conductor pattern on the upper surface 31a side of the wiring board 31 and the conductor pattern on the lower surface 31b side of the wiring board 31.

When it is desired to further improve the position accuracy of the cutting position 52 with respect to the conductor pattern on the upper surface 31a side of the wiring board 31 (pattern of the conductor layer 12a), the line 51 connecting the center coordinates of the two target marks 34 is shifted to the third position. it may be a cutting position 52 after correction by shifting the amount D ₃ X direction (or Y direction). In this case, since the cutting position 52 is determined by correcting the line 51 with the entire amount of the third shift amount D ₃ , the corrected cutting position 52 is the shift amount from the conductor pattern on the lower surface 31 b side of the wiring board 31. However, the positional accuracy of the cutting position 52 with respect to the conductor pattern on the upper surface 31a side of the wiring board 31 can be further increased.

As described above, in the present embodiment, the displacement of the planar position between the through-hole land 37a on the upper surface 31a of the wiring board 31 and the through-hole land 37b on the lower surface 31b of the wiring board 31 with reference to the through-hole 38. (Third deviation amount D ₃ ) is examined, and the cutting position (line 51) based on the target mark 34 is corrected using the third deviation amount D ₃ , and the wiring substrate 31 is fixed at the corrected cutting position 52. Disconnect.

That is, the first shift amount _{D 1} of the plane position of the land 37a and the through-hole 38 through holes in the upper surface 31a of the wiring board 31 is detected in step S11, and the land 37b through hole in the lower surface 31b of the wiring board 31 a second shift amount D ₂ of the plane position of the through hole 38 is detected at step S12. Then, using the second shift amount D ₂ detected in step S12, the corrected cutting position based on the target mark 34 (line 51), the wiring board from the lower surface 31b side of the wiring board 31 in the corrected cutting position 52 31 and the sealing resin 5a are cut. More specifically, the plane positions of the first deviation amount D ₁ and the second shift amount D ₂ Metropolitan lands 37a through hole obtained from the through hole land 37b detected in step S12 detected in step S11 using a third shift amount D _3, to correct the cutting position based on the target mark 34 (line 51), the wiring board 31 from the lower surface 31b side of the wiring board 31 in the corrected cutting position 52 and the sealing resin 5a Disconnect.

In the present embodiment, a target mark 34 and a pattern deviation detection unit 36 are provided for each dicing area 32b (dicing line). Then, for each cutting operation, the target mark 34 provided for the dicing area 32b to be cut is used as a reference, and further detected by the pattern deviation detection unit 36 provided for the dicing area 32b to be cut. using the pattern shift amount (corresponding to the third shift amount D _3), to correct the cutting position on the basis that the target mark 34.

Unlike the present embodiment, when the sealing body 41 is cut along the line 51 determined based on the target mark 34 formed on the lower surface 31b of the wiring substrate 31, the conductor on the upper surface 31a side of the wiring substrate 31 The relative positional accuracy of the cutting position of the sealing body 41 with respect to the pattern, for example, the connection terminal 15 is lowered. In contrast, in the present embodiment, since cutting the sealing body 41 in the third shift amount D ₃ cutting position 52 after correction is corrected using, the upper surface 31a side of the wiring board 31 conductor pattern, e.g. The relative positional accuracy of the cutting position of the sealing body 41 with respect to the connection terminal 15 can be increased.

  For this reason, in this embodiment, the positional accuracy of the cutting position (dicing position) of the sealing body 41 (wiring board 31 and sealing resin 5a) with respect to the conductor pattern on the upper surface 31a side of the wiring board 31, for example, the connection terminal 15. Therefore, it is possible to prevent the connection terminal 15 and the bonding wire 4 from being exposed on the cut surface of the sealing body 41, that is, the side surface of the manufactured semiconductor device 1 (the side surface of the wiring substrate 3 and the sealing resin 5). can do. For this reason, the manufacturing yield of the semiconductor device can be improved. Moreover, since the position accuracy of the cutting position (dicing position) of the sealing body 41 (wiring board 31 and sealing resin 5a) with respect to the conductor pattern on the upper surface 31a side of the wiring board 31, for example, the connection terminal 15, can be improved. The margin of the dicing region 32b can be reduced, which is advantageous for downsizing the semiconductor device 1.

  Further, unlike the present embodiment, when the through hole 38 constituting the pattern deviation detection unit 36 is in a gap state in the wiring board 31, the wiring board 31 is formed when the sealing resin 5a is formed in step S4. There is a possibility that the resin material for forming the sealing resin 5 a leaks from the upper surface 3 a side to the lower surface 31 b side of the wiring substrate 31 through the through hole 38. This leads to adhesion of the resin to the lower surface 31b of the wiring board 31 and reduces the manufacturing yield of the semiconductor device. On the other hand, in the present embodiment, in the wiring board 31, an insulator (insulator material, here, the solder resist layer 14) is embedded in the through hole 38 constituting the pattern deviation detection unit 36. That is, in the present embodiment, the solder resist layer 14 is formed on the upper surface 31a and the lower surface 31b of the wiring board 31 so as to cover the through-hole lands 37a and 37b, and the through-holes constituting the pattern deviation detecting unit 36 are formed. A part of the solder resist layer 14 is embedded in the hole 38. For this reason, when the sealing resin 5a is formed in the molding process of step S4, the resin material for forming the sealing resin 5a is transferred from the upper surface 3a side of the wiring substrate 31 through the through hole 38 to the lower surface 31b side of the wiring substrate 31. It is possible to prevent leakage. Accordingly, it is possible to prevent the resin from adhering to the lower surface 31b of the wiring substrate 31 and to improve the manufacturing yield of the semiconductor device.

The first detection of the displacement amount D ₁ of the upper surface 31a side of the wiring board 31 in the step S11, the wire die bonding step (step of mounting the semiconductor chip 2 on the wiring board 31) or step S3 in the step S2 More preferably, it is performed during the bonding process. Thus, although using an image recognition device in step S2 and step S3, the image recognition apparatus, it is possible to use the first detection of the displacement amount D ₁ of the step S11 (to be shared), again the image recognition device prepared is not necessary to perform a first detection of displacement amount D ₁ of the step S11 to. For this reason, the number of manufacturing steps of the semiconductor device can be reduced and the throughput can be improved. Further, if the sealing resin 5a is formed on the upper surface 31a of the wiring board 31, it becomes difficult to confirm the positions of the through-hole lands 37a and the through-holes 38, so the first upper surface 31a side of the wiring board 31 in step S11. detection process of the deviation amount D ₁ is at least is preferably performed prior to the step of forming the sealing resin 5a in step S4.

Further, after performing the detection of the first deviation amount _{D 1} of the upper surface 31a side of the wiring board 31 in step S11 earlier, the second detection of the displacement amount _{D 2} of the lower surface 31b side of the wiring board 31 in Step S12 performed even or, after performing the second detection displacement amount _{D 2} of the lower surface 31b side of the wiring board 31 in step S12 earlier, the first shift amount D of the upper surface 31a side of the wiring board 31 in step S11 ₁ may be detected.

Further, the detection displacement amount _{D 2} second lower surface 31b side of the wiring board 31 in step S12, may be performed before cutting the wiring board 31 (the sealing body 41), in step S7, the target mark 34 the in recognizing the image recognition apparatus, it is also possible to detect a second displacement amount D ₂ of planar position between the lands 37b and the through hole 38 through hole by using the image recognition apparatus. In this case, the above steps S12 to S14 are performed in step S7. Accordingly, it is possible to use an image recognition apparatus for use in the dicing step of the step S7 to the second detection of the displacement amount D ₂ of step S12 (to be shared), the second step S12 to prepare for renewed image recognition device of it is not necessary to detect the displacement amount D _2, it is possible to improve the number of manufacturing steps reduced and the throughput of the semiconductor device.

Further, before the assembly of the semiconductor device according to the step S2 to S7, after the above steps S11, S12 in advance to the wiring substrate 31, a first shift amount _{D 1} and / or the second shift amount _{D 2} It is possible to perform the above-described step S7 (S14) using these data. Further, the process of producing a wiring board 31 (e.g. before forming the solder resist layer 14) by performing the corresponding step S11, S12, examines the first deviation amount D ₁ and / or the second shift amount D ₂ It may be left.

  FIGS. 29 and 30 are a top view and a bottom view of relevant parts showing a wiring board 31c which is a first modification of the wiring board 31, and FIGS. 31 and 32 show a second modification of the wiring board 31. FIG. FIGS. 29 and 30 correspond to FIGS. 20 and 21, respectively, and FIGS. 31 and 32 correspond to FIGS. 20 and 21, respectively. This corresponds to FIG. Accordingly, as in FIGS. 20 and 21, the solder resist layer 14 is not shown in FIGS. 29 to 32 (that is, the solder resist layer 14 is seen through).

  As shown in FIGS. 20 and 21, the wiring board 31 is provided with two target marks 34 and two pattern deviation detectors 36 for one dicing region 32b (dicing line). A pattern deviation detection unit 36 is arranged in the vicinity of each target mark 34. However, there is a pattern shift in the vicinity of each target mark 34, such as the wiring board 31c of the first modification shown in FIGS. 29 and 30 and the wiring board 31d of the second modification shown in FIGS. In addition to arranging the detection units 36 one by one, a pattern deviation detection unit 36a having the same configuration as the pattern deviation detection unit 36 may be provided in each dicing area 32b (dicing line). The configurations of the wiring board 31c of the first modification and the wiring board 31d of the second modification have substantially the same configuration as the wiring board 31 except that the pattern deviation detection unit 36a is provided.

  In the wiring board 31c shown in FIG. 29 and FIG. 30, it is the same as the wiring board 31 that one pattern deviation detector 36 is arranged in the vicinity of each target mark 34, but further, the pattern deviation detector 36a. Are provided near the center of each dicing region 32b (dicing line). Similarly to the pattern deviation detector 36, each pattern deviation detector 36 a includes through-hole lands 37 a formed on the upper surface 11 a of the base material layer 11 (upper surface 31 a of the wiring substrate 31) and the lower surface 11 b of the base material layer 11. The through hole lands 37 b formed on the (lower surface 31 b of the wiring substrate 31) and the through holes 38 formed in the base material layer 11 are configured. Similarly to the through hole 38 of the pattern deviation detection unit 36, the through hole 38 of the pattern deviation detection unit 36a is formed with a conductor layer 37c on the side wall, and a portion that is not filled with the conductor layer 37c in the through hole 38 is a solder. The resist layer 14 is filled (filled).

  Further, in the wiring board 31d shown in FIGS. 31 and 32, it is the same as the wiring board 31 that one pattern deviation detection unit 36 is arranged in the vicinity of each target mark 34. The part 36a is provided at each intersection of dicing regions 32b (dicing lines) extending in the X direction and the Y direction. Therefore, either the pattern deviation detection unit 36 or the pattern deviation detection unit 36a is provided at each of the four corners of each semiconductor device region 32a.

When the wiring boards 31c and 31d are used, the semiconductor device 1 can be manufactured in substantially the same manner as when the wiring board 31 is used. When manufacturing the semiconductor device 1 using the wiring boards 31c and 31d, the steps S11 to S13 can be performed not only on the pattern deviation detection unit 36 but also on the pattern deviation detection unit 36a. In this case, in step S7, the pattern shift amount detected the pattern shift detection unit 36 (corresponding to the third shift amount D ₃₎ Not only the pattern shift amount detected the pattern shift detection unit 36a ( the also used correspond) to the third shift amount D _3, it is possible to correct the cutting position based on the target mark 34 (corresponding to the line 51). Thereby, the precision of correction of the cutting position (dicing position) can be further increased. However, in order to correct the cutting position based on the target mark 34 (corresponding to the line 51), a third shift amount D ₃ detected the pattern shift detection section 36 provided closest to the target mark 34 Since it is most effective to use, the steps S11 to S13 do not have to be performed for the pattern deviation detection unit 36a located at a relatively far position from the target mark 34.

  When the semiconductor device 1 d corresponding to the semiconductor device 1 is manufactured using the wiring substrate 31 d shown in FIGS. 31 and 32, the manufactured semiconductor device 1 d has pattern deviation detection units 36, 36 at the four corners of the wiring substrate 3. The remaining part of 36a will be formed. FIG. 33 is a bottom view of the semiconductor device 1d manufactured using the wiring substrate 31d, and FIG. 34 is a cross-sectional view of the main part of the semiconductor device 1d. A cross-sectional view taken along line GG in FIG. 33 is the same as FIG. A sectional view taken along line HH in FIG. 33 substantially corresponds to FIG. Further, in order to facilitate understanding, in FIG. 33, the solder resist layer 14 is omitted (transparent) in the vicinity of the four corners of the wiring board 3.

  As shown in FIGS. 33 and 34, the semiconductor device 1d manufactured using the wiring board 31d has four corners on the side surface of the wiring board 3 (base material layer 11) chamfered. The conductor layer 55c, which is the remaining portion of the conductor layer 37c, is formed on the side wall (side surface) 54. The reason why the four corners (side walls 54) of the side surface of the wiring board 3 are chamfered in the semiconductor device 1d is that some of the through holes 38 remain at the four corners of the wiring board 3. In the semiconductor device 1d, conductor patterns 55a that are remaining portions of the through-hole lands 37a are formed in the vicinity of the four corners of the upper surface 3a of the wiring substrate 3 (the upper surface 11a of the base material layer 11), and the lower surface 3b of the wiring substrate 3 is formed. In the vicinity of the four corners of (the lower surface 11b of the base material layer 11), the conductor pattern 55b which is the remaining portion of the through-hole land 37b is formed. The conductor patterns 55a and 55b and the conductor layer 55c are covered with the solder resist layer 14. In such a configuration, pattern displacement detectors 36 and 36a are provided at each intersection of the dicing regions 32b (dicing lines) (that is, at the four corners of each semiconductor device region 32a) as in the wiring board 31d, and the through holes 38 are provided. This diameter can be obtained by making the diameter larger than the width of the dicing blade 43 (blade width). Accordingly, the semiconductor device 1d includes the conductor pattern 55a on the upper surface 3a of the wiring substrate 3 (the upper surface 11a of the base material layer 11) and the conductor on the side wall 54 of the wiring substrate 3 (the base material layer 11) at the four corners of the wiring substrate 3. The layer 55c and the conductor pattern 55b of the lower surface 3b of the wiring board 3 (the lower surface 11b of the base material layer 11) are integrally connected. An integral conductor layer 55 is formed by the conductor patterns 55a and 55b and the conductor layer 55c. The conductor layer 55 is composed of a copper plating layer or the like. Since the other structure of the semiconductor device 1d is almost the same as that of the semiconductor device 1, the description thereof is omitted here.

  In the semiconductor device 1d manufactured using the wiring board 31d of the second modified example, the conductor layer 55c is formed on the four corner side surfaces (the chamfered corners) of the wiring board 3, and the wiring board 3 The conductor pattern 55a on the upper surface 31a (upper surface 11a of the base material layer 11) of 31 is connected to the conductor pattern 55b on the lower surface 31b (lower surface 11b of the base material layer 11) of the wiring board 31. For this reason, the wiring board 3 constituting the semiconductor device 1d is resistant to the vertical expansion and contraction stress caused by heat, and the reliability of the semiconductor device 1d can be further improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is effective when applied to a method of manufacturing a semiconductor device in the form of a semiconductor package in which a semiconductor chip is mounted on a wiring board.

It is a top view of the semiconductor device which is one embodiment of the present invention. It is a bottom view of the semiconductor device which is one embodiment of the present invention. It is sectional drawing of the semiconductor device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor device which is one embodiment of this invention. It is a side view of the semiconductor device which is one embodiment of the present invention. It is a plane perspective view of the semiconductor device which is one embodiment of the present invention. It is a manufacturing process flowchart which shows the manufacturing process of the semiconductor device which is one embodiment of this invention. It is sectional drawing in the manufacturing process of the semiconductor device of one embodiment of this invention. FIG. 9 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 8; FIG. 10 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 9; FIG. 11 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 10; FIG. 12 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG. 13 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12; FIG. 14 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 13; It is a top view which shows the whole wiring board used for manufacture of the semiconductor device of one embodiment of this invention. It is a bottom view which shows the whole wiring board of FIG. FIG. 16 is a partially enlarged top view of the wiring board of FIG. 15. FIG. 16 is a partially enlarged bottom view of the wiring board of FIG. 15. It is sectional drawing of CC line of FIG. FIG. 18 is a top perspective view of the wiring board of FIG. 17. It is a lower surface perspective view of the wiring board of FIG. It is the elements on larger scale of the wiring board of FIG. It is sectional drawing of the EE line | wire of FIG. It is explanatory drawing which shows the detection method of a pattern deviation, and the method of correct | amending a dicing position by the detected pattern deviation. It is a principal part bottom view of a wiring board when pattern shift arises. It is a principal part top view of a wiring board when pattern shift arises. It is a principal part top view of the wiring board when a pattern shift | offset | difference arises. It is principal part sectional drawing of a wiring board when a pattern shift | offset | difference arises. It is a principal part top view which shows the wiring board of other embodiment of this invention. It is a principal part bottom view which shows the wiring board of FIG. It is a principal part top view which shows the wiring board of other embodiment of this invention. FIG. 32 is a bottom view of the main part showing the wiring board of FIG. 31. FIG. 33 is a bottom view of a semiconductor device manufactured using the wiring board shown in FIGS. 31 and 32. FIG. 33 is an essential part cross-sectional view of a semiconductor device manufactured using the wiring board shown in FIGS. 31 and 32.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,1d Semiconductor device 2 Semiconductor chip 2a Electrode 2b Front surface 2c Back surface 3 Wiring board 3a Upper surface 3b Lower surface 4 Bonding wire 5, 5a Sealing resin 6 Solder ball 8 Adhesive material 11 Base material layer 11a Upper surface 11b Lower surface 12, 12a, 12b, 12c Conductor layer 14 Solder resist layer 15 Connection terminal 16 Land 17 Opening 18 Opening 19a, 19b Opening 31 Wiring board 31a Upper surface 31b Lower surface 32a Semiconductor device region 32b Dicing region 33a, 33b Feed line 34 Target mark 35 Opening 36, 36a pattern shift detection unit 37a, 37b through hole land 37c conductor layer 38 through holes 41 sealing body 42 package fixing tape 43 dicing blade 51 along line 52 the cutting position 54 side walls 55a, 55b conductor pattern 55,55c conductor layer _{D 1} second Shift amount _{D 2} second shift amount _{D 3} third shift amount _{T 1} diameter _{T 2} diameter

Claims (6)

A semiconductor chip is mounted on a first main surface of a wiring board having a plurality of unit substrate regions from which each semiconductor device is manufactured, and sealed so as to cover the semiconductor chip on the first main surface of the wiring board. After forming the stop resin, the wiring substrate and the sealing resin are cut along the dicing region between the unit substrate regions from the second main surface side opposite to the first main surface of the wiring substrate. A method for manufacturing a semiconductor device comprising:
In the wiring board, a target mark for positioning the cutting position of the wiring board is formed on the second main surface for each of the dicing regions, and a first conductor pattern is formed in the vicinity of the target mark on the second main surface. Is formed, a second conductor pattern is formed at a position corresponding to the first conductor pattern on the first main surface, and the first opening is formed at a position overlapping the first conductor pattern and the second conductor pattern in a plane. Formed,
(A) detecting a first shift amount of a planar position between the second conductor pattern and the first opening on the first main surface of the wiring board; and (b) the second of the wiring board. Detecting a second shift amount of a planar position between the first conductor pattern and the first opening on the main surface;
Have
Using the second shift amount detected in the step (b), the cutting position based on the target mark is corrected, and the wiring board and the wiring board from the second main surface side of the wiring board at the corrected cutting position are corrected. A method for manufacturing a semiconductor device, comprising cutting the sealing resin. In the manufacturing method of the semiconductor device according to claim 1,
In the wiring board, a semiconductor device manufacturing method, wherein an insulator is embedded in the first opening. In the manufacturing method of the semiconductor device according to claim 1,
A solder resist layer is formed on the first main surface and the second main surface of the wiring board so as to cover the first conductor pattern and the second conductor pattern, and the solder opening is formed in the first opening. A method for manufacturing a semiconductor device, wherein a part of a resist layer is embedded. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the first conductor pattern, the second conductor pattern, and the first opening are disposed in the dicing region of the wiring board. In the manufacturing method of the semiconductor device according to claim 1,
In the wiring board, the first conductor pattern and the second conductor pattern are circular patterns, and the first opening is formed in the plane of the circular pattern. Manufacturing method. In the manufacturing method of the semiconductor device according to claim 1,
After the step (b), the first deviation of the second main surface obtained from the first deviation amount detected in the step (a) and the second deviation amount detected in the step (b). Using the third shift amount of the planar position of the conductor pattern and the second conductor pattern of the first main surface, the cutting position based on the target mark is corrected, and the wiring board at the corrected cutting position is corrected. A method of manufacturing a semiconductor device, comprising cutting the wiring board and the sealing resin from a second main surface side.

Images