JPH09172037A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of production steps of a semiconductor device with a semiconductor chip mounted on a sub-circuit board in order to change the layout pattern of bumps of the chip. SOLUTION: First connection electrodes protrudent to device holes 22 and second connection electrodes 25, etc., disposed to cover openings 23 are formed on the upper face of a sub-circuit board 21. Solder bumps 27 are formed on the exposed faces of the electrodes 25 through the openings 23 such that a flux is applied on these exposed faces directed upwards, solder balls are put thereon and reflow step is applied to form the solder bumps 27 wherein when the solder balls are once melted, the circuit board 21 blocks the molten solder from flowing away from the electrodes 25. Hence no exclusive solder resist film is needed to block the solder from flowing away.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art In a semiconductor device mounting technique called, for example, a flip chip method, bumps provided on a lower surface of a semiconductor chip are bonded to connection electrodes provided on an upper surface of a circuit board to thereby mount the semiconductor chip on the circuit board. It is implemented in. By the way, such a semiconductor device has the following problems because the number of bumps of the semiconductor chip increases as the integration progresses.
That is, assuming that the size of the semiconductor chip is constant, not only the size and pitch of the bumps decrease as the number of bumps increases, but also the size and pitch of the connecting electrodes of the circuit board decrease. When mounting on a circuit board, it becomes extremely difficult to align the bumps of the semiconductor chip with the connection electrodes of the circuit board,
Further, when performing an electrical test using the probe pins, there is a problem that it becomes extremely difficult to align the probe pins with the bumps. In particular, in the latter electrical test, if the size and pitch of the bumps are too small relative to the size and pitch of the probe pins, a short circuit occurs, making it impossible to perform the electrical test.

Therefore, in order to solve the above problems, a method of mounting a semiconductor chip via a sub-circuit board instead of directly mounting it on a circuit board (main circuit board) has been considered. Has been. FIGS. 6A and 6B show an example of such a conventional semiconductor device (one in which a semiconductor chip is mounted on a sub circuit board). A device hole 2 is provided in the center of the sub circuit board 1.
Are formed. In order to electrically connect between the plurality of first connection electrodes 3 and the plurality of second connection electrodes 4 provided so as to project into the device hole 2 on the lower surface of the sub-circuit board 1 and between both connection electrodes 3 and 4. The plurality of wiring lines 5 provided (see FIG.
A wiring pattern composed of (A) and (B) is formed. A solder resist film 6 is formed on the lower surface of the sub circuit board 1 except for the central portion of the second connection electrode 4 (see FIGS. 7A and 7B). Therefore, the center of the second connection electrode 4 is exposed through the opening 7 formed in the solder resist film 6. Solder bumps 8 are provided on the exposed surface exposed through the openings 7 of the second connection electrode 4. The second connection electrodes 4 and the solder bumps 8 are arranged in a matrix on the lower surface of the sub circuit board 1. The semiconductor chip 9 is mounted in the sub-circuit board 1 by being arranged in the device hole 2 and the bumps 10 provided around the lower surface of the semiconductor chip 9 being bonded to the first connection electrodes 3. In FIG. 6B, reference numeral 11 indicates a resin sealing material.

As described above, in this semiconductor device, since the plurality of second connection electrodes 4 are formed on the lower surface of the sub-circuit board 1 in a matrix, the second connection electrodes 4 (that is, the solder bumps 8) are formed. The size and pitch of the first connection electrode 3
It can be made larger than the size and pitch of (that is, the bumps 10 of the semiconductor chip 9). As a result, when the probe pin is brought into contact with the solder bump 8 when an electrical test is performed using the probe pin, the probe pin and the solder bump 8 can be easily aligned with each other, and a short circuit can be prevented. be able to. Also,
Although not shown, the semiconductor chip 9 can be mounted on the main circuit board via the sub circuit board 1 by bonding the solder bumps 8 to the connection electrodes provided on the upper surface of the main circuit board. The size and pitch of the connection electrodes of the main circuit board can be made larger than the size and pitch of the bumps 10 of the semiconductor chip 9. As a result, the semiconductor chip 9 is attached to the sub circuit board 1
When mounted on the main circuit board via the solder bumps 8, the solder bumps 8 can be easily aligned with the connection electrodes of the main circuit board.

By the way, in this semiconductor device, as described above, the solder resist film 6 is formed on the lower surface of the sub-circuit board 1 excluding the central portion of the second connection electrode 4. That is, the outer peripheral portion of the second connection electrode 4 is covered with the solder resist film 6. Next, the reason will be described. When forming the solder bumps 8, first, as shown in FIGS. 7A and 7B, the exposed surface exposed through the opening 7 of the second connection electrode 4 is set to the upper side. In this case, although not shown, a solder plating layer is formed by electrolytic plating on the surface of the wiring pattern including the second connection electrodes 4 before forming the solder resist film 6. Next, the second
A flux (not shown) is applied to the exposed surface exposed through the opening 7 of the connection electrode 4, and the solder ball 8a is placed thereon. Next, after the reflow process, the solder balls 8a are once melted, rolled up by surface tension, and then solidified, so that the solder balls 8a are exposed through the openings 7 of the solder resist film 6 as shown in FIG. 6B. Solder bumps 8 are formed on the exposed surfaces of the formed second connection electrodes 4. At this time, that is, when the solder ball 8a is once melted, the second
Since the outer peripheral portion of the connection electrode 4 is covered with the solder resist film 6, it is possible to prevent the melted solder from flowing out onto the routing wire 5 connected to the second connection electrode 4,
As a result, the solder bumps 8 having a desired shape are formed. This is the reason why the solder resist film 6 is formed on the lower surface of the sub circuit board 1 excluding the central portion of the second connection electrode 4.

[0006]

As described above, in the conventional semiconductor device, in order to form the solder bumps 8 having a desired shape, the sub-circuit board 1 except the central portion of the second connection electrode 4 is formed.
Since the solder resist film 6 is formed on the lower surface of, the solder resist film forming step is required, and there is a problem that the number of manufacturing steps increases. An object of the present invention is to reduce the number of manufacturing steps.

[0007]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a substrate; a plurality of first connection electrodes and a plurality of second connection electrodes arranged on the substrate; A wiring pattern composed of a plurality of wiring lines for conducting between the electrodes, a semiconductor chip bonded to the first connection electrode and mounted on the substrate, and solder provided on the second connection electrode. A semiconductor device including a bump, wherein an opening is formed in a portion of the substrate corresponding to the second connection electrode, and the solder bump is provided on an exposed surface exposed through the opening. It is a thing.
According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a plurality of first connection electrodes connected to respective electrodes of a semiconductor chip on a substrate and a plurality of second connection electrodes each covering an opening provided in the substrate. Forming a wiring pattern consisting of the connection electrode of (1) and a plurality of wiring lines for conducting between the both connection electrodes, and then mounting a semiconductor chip on the substrate by bonding to the first connection electrode, The solder bumps are formed in the openings corresponding to the connection electrodes.

According to the present invention, since the second connection electrode is exposed through the opening formed in the substrate and the solder bump is formed on the exposed surface in the opening, the second connecting electrode is melted by the substrate itself. The solder thus formed can be prevented from flowing out from the second connection electrode, so that the conventional solder resist film is not required and the number of manufacturing steps can be reduced.

[0009]

1 (A) and 1 (B) show the essential parts of a semiconductor device according to a first embodiment of the present invention. This semiconductor device includes a sub-circuit board 21 made of a film board made of polyimide, polyethylene terephthalate, or the like. A device hole 22 is formed in the center of the sub-circuit board 21, and an opening 23 composed of a plurality of circular holes is formed in a matrix around the device hole 22. The device hole 22 and the opening 23 are formed by punching. On the upper surface of the sub-circuit board 21, a plurality of first connecting electrodes 24 provided so as to project into the device hole 22 and a plurality of second connecting electrodes 25 provided so as to cover the opening 23 (see FIG. A wiring pattern is formed by (A) and (B)) and a plurality of routing lines 26 (see FIGS. 2A and 2B) provided for electrical connection between the connection electrodes 24 and 25. ing. Solder bumps 27 are formed on the exposed surface of the second connection electrode 25 facing the sub-circuit board 21 and exposed through the opening 23. In this case, the size and arrangement pitch of the solder bumps 27 (that is, the second connection electrodes 25) are larger than the size and arrangement pitch of the first connection electrodes 24. The semiconductor chip 28 is mounted in the sub-circuit board 21 by being arranged in the device hole 22 and having bumps 29 provided around the upper surface thereof bonded to the first connection electrodes 24. In FIG. 1B, reference numeral 30 indicates a resin sealing material.

Next, an example of a method of manufacturing this semiconductor device will be described. When the sub-circuit board 21 is made of a film substrate such as polyimide or polyethylene terephthalate, a long base film is conveyed by a roll-to-roll method. However, since the process is not directly related to the present invention, the description will be simplified. First, the device hole 22 and the opening 23 are formed in the sub circuit board 21. Next, a copper foil is laminated on one surface of the sub circuit board 21. Next, a resist film is formed on the entire surface of the copper foil. Next, by performing wet etching, the device hole 22 and the opening 23
Lightly etch the exposed surface of the copper foil exposed through. This is for facilitating attachment of solder plating, which will be performed in a later step, on the exposed surface of the copper foil exposed through the device hole 22 and the opening 23.

Next, a predetermined resist pattern is formed on the surface of the copper foil by exposing it using an exposure mask having a predetermined pattern and then developing it. Next, the device hole 22 and the opening 23 are covered with another resist. this is,
Of the copper foil exposed through the device hole 22 in the next etching step, the portion that will be the first connection electrode 24 and the portion exposed through the opening 23, that is, the portion that will be the second connection electrode 25 will be This is to prevent etching. Next, when the copper foil is wet-etched using the resist pattern as a mask, the first connection electrode 24 and the second
A wiring pattern including the connection electrodes 25 and the leading lines 26 therebetween is formed. Next, the resist is stripped. Next, a solder plating layer is formed by electrolytic plating on the entire surface of the wiring pattern including the exposed surface of the second connection electrode 25 exposed through the opening 23. Then, inner lead bonding is performed to bond the bumps 29 of the semiconductor chip 28 to the first connection electrodes 24.
Next, the portion of the semiconductor chip 28 is sealed with the resin sealant 30.

Next, as shown in FIGS. 2A and 2B, the exposed surface exposed through the opening 23 of the second connection electrode 25 is set to the upper side. Next, a flux (not shown) is applied to the exposed surface of the second connection electrode 25 exposed through the opening 23, and the solder ball 27a having a diameter slightly larger than the diameter of the opening 23 is applied onto the flux. To place. Next, when the reflow process is performed, the solder balls 27a are once melted, rounded by the surface tension, and then solidified.
As shown in (B), the solder bumps 27 are formed on the exposed surfaces of the second connection electrodes 25 exposed through the openings 23 of the sub circuit board 21. At this time, that is, when the solder ball 27a is once melted, since the outer peripheral portion of the second connection electrode 25 is covered with the sub-circuit board 21, the melted solder is connected to the second connection electrode 25 by the lead wire 26. It is possible to prevent the solder bumps 27 from flowing upward, and thereby the solder bumps 27 having a desired shape are formed. In this case, the solder melted by the sub circuit board 21 itself is the second
Can be prevented from flowing out from above the connection electrode 25, so that the conventional solder resist film becomes unnecessary, and the number of manufacturing steps can be reduced.

In this semiconductor device, since the openings 23 of the sub-circuit board 21 made of a film substrate are formed by punching, it is possible to improve the arrangement position accuracy and shape accuracy of the openings 23. As a result, when the thickness of the sub circuit board 21 is 0.3 to 0.4 mm, the arrangement pitch of the openings 23 is 0.8 to 1.0 mm and the diameter of the openings 23 is 0.4 to 0. 0.5 mm, diameter 0.5
By using the solder balls 27a having a size of up to 0.6 mm, it is possible to form the solder bumps 27 having good arrangement position accuracy and shape accuracy. In addition, the thickness of the sub circuit board 21 is 0.3.
In the case of ˜0.6 mm, the arrangement pitch of the openings 23 is 1.2 to 1.4 mm, and the diameter of the openings 23 is 0.6 to
When the solder balls 27a having a diameter of 0.7 mm and a diameter of 0.7 to 0.8 mm are used, the solder bumps 27 having good arrangement position accuracy and shape accuracy can be formed.

In the above embodiment, as shown in FIG. 1B, the semiconductor chip 28 is arranged in the device hole 22 and the bump 29 is bonded to the first connection electrode 24. , But is not limited to this. For example, as in the second embodiment shown in FIG. 3, the first connection electrode 24 is formed in the central portion of the upper surface of the sub-circuit board 21 made of a film substrate having no device hole, and is formed around the lower surface of the semiconductor chip 28. The semiconductor chip 28 may be mounted on the central portion of the upper surface of the sub circuit board 21 by bonding the provided bumps 29 on the first connection electrodes 24. Further, as in the third embodiment shown in FIG. 4 or the fourth embodiment shown in FIG. 5, a protective film 31 made of the same material as the resin sealing material 30 is formed on the upper surface of the sub circuit board 21 including the wiring pattern by using a resin. It may be formed simultaneously with the formation of the sealant 30.

[0015]

As described above, according to the present invention, the second connection electrode is exposed through the opening formed in the substrate, and the solder bump is formed on the exposed surface in the opening. Therefore, it is possible to prevent the solder melted by the substrate itself from flowing out from the second connection electrode, and thus the conventional solder resist film becomes unnecessary, and the number of manufacturing steps can be reduced.

[Brief description of the drawings]

FIG. 1A is a bottom view of a semiconductor device according to a first embodiment of the present invention, and FIG. 1B is a sectional view taken along line BB thereof.

FIG. 2A is a partial plan view for explaining the formation of the solder bumps shown in FIG. 1, and FIG. 2B is a sectional view taken along the line BB.

FIG. 3 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 5 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 6A is a bottom view of a conventional semiconductor device, and FIG. 6B is a sectional view taken along line BB thereof.

7A is a partial plan view shown for explaining the formation of the solder bumps shown in FIG. 6, and FIG. 7B is a sectional view taken along the line BB.

[Explanation of symbols]

 21 Sub-Circuit Board 22 Device Hole 23 Opening 24 First Connection Electrode 25 Second Connection Electrode 26 Routing Line 27 Bump 28 Semiconductor Chip

Claims (8)

[Claims] 1. A wiring pattern comprising a substrate, a plurality of first connection electrodes arranged on the substrate, a plurality of second connection electrodes, and a plurality of routing lines for conducting the connection between the both connection electrodes. A semiconductor chip bonded to the first connection electrode and mounted on the substrate, and a solder bump provided on the second connection electrode, the semiconductor device comprising: 2. A semiconductor device, wherein an opening is formed in a portion corresponding to the second connection electrode, and the solder bump is provided on an exposed surface exposed through the opening. 2. The invention according to claim 1, wherein a device hole is formed in the substrate, the first connection electrode is formed so as to project into the device hole, and the semiconductor chip is formed in the first connection electrode. A semiconductor device characterized by being bonded. 3. The invention according to claim 1, wherein the first
Connection electrode is formed on the upper surface of the substrate, and the semiconductor chip is bonded on the first connection electrode. 4. The invention according to claim 1, wherein the wiring pattern is formed on an upper surface of the substrate, the semiconductor chip is sealed with a resin sealing material, and the wiring pattern includes the wiring pattern. A semiconductor device, wherein a protective film made of the same material as the resin sealing material is formed on the upper surface of the substrate. 5. A plurality of first connection electrodes connected to each electrode of the semiconductor chip on the substrate, a plurality of second connection electrodes each covering an opening provided in the substrate, and a space between the both connection electrodes. A wiring pattern consisting of a plurality of routing lines for conduction is formed, and then a semiconductor chip is mounted on the substrate by bonding to the first connection electrode, and the semiconductor chip is mounted in each opening corresponding to the second connection electrode. A method for manufacturing a semiconductor device, which comprises forming a solder bump. 6. The invention according to claim 5, wherein a device hole is formed in the substrate, the first connection electrode is formed so as to project into the device hole, and the semiconductor chip is formed as the first connection electrode. A method for manufacturing a semiconductor device, which comprises bonding. 7. The invention according to claim 5, wherein the first
Forming a connection electrode on the upper surface of the substrate, and bonding the semiconductor chip on the first connection electrode. 8. The invention according to claim 5, wherein the wiring pattern is formed on the upper surface of the substrate,
A semiconductor device, wherein the semiconductor chip is sealed with a resin sealing material, and a protective film made of the same material as the resin sealing material is formed on an upper surface of the substrate including the wiring pattern.