WO2019192137A1 - 阵列基板、覆晶薄膜、显示装置及对位方法 - Google Patents

阵列基板、覆晶薄膜、显示装置及对位方法 Download PDF

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Publication number
WO2019192137A1
WO2019192137A1 PCT/CN2018/102687 CN2018102687W WO2019192137A1 WO 2019192137 A1 WO2019192137 A1 WO 2019192137A1 CN 2018102687 W CN2018102687 W CN 2018102687W WO 2019192137 A1 WO2019192137 A1 WO 2019192137A1
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Prior art keywords
alignment
pin
mark
array substrate
alignment mark
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PCT/CN2018/102687
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English (en)
French (fr)
Inventor
刘仁杰
王向前
陈玲艳
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昆山国显光电有限公司
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Application filed by 昆山国显光电有限公司 filed Critical 昆山国显光电有限公司
Priority to JP2020501522A priority Critical patent/JP7058319B2/ja
Priority to EP18913777.1A priority patent/EP3640980A4/en
Priority to KR1020207000274A priority patent/KR20200008655A/ko
Priority to US16/265,630 priority patent/US10964644B2/en
Publication of WO2019192137A1 publication Critical patent/WO2019192137A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/8113—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/81132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/8513—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/147—Structural association of two or more printed circuits at least one of the printed circuits being bent or folded, e.g. by using a flexible printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10128—Display

Definitions

  • the present application relates to the field of display technologies, and in particular, to an array substrate, a flip chip, a display device, and a alignment method.
  • the flexible display device refers to a display device in which the display panel is bendable and deformable.
  • flexible display devices have the advantages of thinness, lightness, high contrast, fast response, wide viewing angle, high brightness, full color, etc. in mobile phones, personal digital assistants (PDAs), digital cameras.
  • PDAs personal digital assistants
  • car display, notebook computers, wall-mounted TVs and military fields have a very broad application prospects.
  • the pins/terminals/electrodes on the Chip On Film (COF) in the flexible display device should be aligned with the pins on the screen.
  • COF Chip On Film
  • the embodiments of the present application provide an array substrate, a flip chip, a display device, and a alignment method for solving the problem that the pins on the array substrate and the pins on the COF cannot be accurately aligned in the prior art. .
  • the present application provides an array substrate including a first pin for corresponding connection with a second pin on a flip chip; a first alignment mark located at the first pin
  • the alignment preset range is used for aligning with the second alignment mark on the flip chip; the first offset mark is obtained by the first alignment mark and the second alignment mark, and the pair is located at the first pin
  • the bit preset range is used to indicate the alignment deviation between the first pin and the second pin.
  • the first pin comprises a plurality
  • the second pin comprises a plurality, the first offset mark being adjacent to the first pin of the plurality of first pins that is closest to the first parity mark.
  • straight lines of the plurality of second pins or the plurality of second pins cross each other.
  • the first offset mark includes a first alignment scale
  • the first alignment scale includes a lateral alignment scale and/or a longitudinal alignment scale.
  • the first offset mark includes a first alignment label
  • the first alignment label includes a first lateral alignment label and a first longitudinal alignment label corresponding to the first lateral alignment label.
  • the present application further provides a flip chip, including a second pin for corresponding connection with a first pin on an array substrate, and a second alignment mark for alignment of the second pin a range for aligning with the first align mark on the array substrate; a second offset mark obtained by the first align mark and the second align mark, located at a preset range of the second pin Used to indicate the alignment deviation between the first pin and the second pin.
  • the first pin includes a plurality of
  • the second pin includes a plurality
  • the second offset mark is adjacent to the second pin of the plurality of second pins that is closest to the second parity mark.
  • straight lines of the plurality of first pins or the plurality of first pins cross each other.
  • the second offset mark includes a second alignment scale
  • the second alignment scale includes a lateral alignment scale and/or a longitudinal alignment scale.
  • the second offset mark includes a second alignment mark
  • the second alignment mark includes a second lateral alignment label and a second vertical alignment label corresponding to the second lateral alignment label.
  • the present application further provides a display device comprising the array substrate mentioned in any of the above embodiments, further comprising a flip chip, the flip chip comprising a second pin, a second alignment mark, and The second offset marker.
  • the present application further provides a display device, including the flip-chip film mentioned in any of the above embodiments, further comprising an array substrate, wherein the array substrate comprises a first pin, a first alignment mark, and a first An offset marker.
  • the present application further provides a method for aligning, the method comprising: connecting a first pin on a first device to a second pin on a second device; The pair of bit marks are aligned with the second bit mark on the second device; the first offset mark is used to indicate a registration offset of the first pin and the second pin, wherein the first offset mark is according to the first pair The bit mark and the second bit mark are obtained; the first device and the second device are aligned according to the registration deviation.
  • the first device is one of an array substrate and a flip chip
  • the second device is the other of the array substrate and the flip chip.
  • the array substrate, the flip chip, the display device, and the alignment method provided by the embodiments of the present application in addition to the alignment mark for aligning the pins on the array substrate and the pins on the flip chip, An offset flag for indicating the alignment deviation of the pins on the array substrate and the pins on the flip chip is set, so that after the alignment is performed by the alignment mark, the offset mark can be used to determine the alignment deviation.
  • the offset mark is used for precise alignment, so that even if the oblique pin is affected by thermal expansion during the process, the offset mark can be combined with the offset mark for accurate alignment.
  • FIG. 1 is a schematic diagram of an array substrate according to an embodiment of the present application.
  • Figure 2 is a partial enlarged view of Figure 1;
  • FIG. 3 is a schematic view of a flip chip according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of an array substrate provided by another embodiment of the present application.
  • Figure 5 is a partial enlarged view of Figure 4.
  • FIG. 6 is a schematic diagram of an array substrate according to still another embodiment of the present application.
  • FIG. 7 is a schematic view of a flip chip provided by another embodiment of the present application.
  • FIG. 8 is a schematic view of a flip chip provided by another embodiment of the present application.
  • Figure 9 is a partial enlarged view of Figure 8.
  • FIG. 10 is a schematic flowchart diagram of a aligning method according to still another embodiment of the present application.
  • the array substrate provided by the present application includes: a first pin for corresponding connection with a second pin on the flip chip; and a first alignment mark located at a matching range of the first pin for use in The second alignment mark on the flip chip is aligned; the first offset mark is obtained by the first alignment mark and the second alignment mark, and is located at a matching preset range of the first pin for indicating The deviation of the alignment between one pin and the second pin.
  • the flip chip provided by the present application comprises: a second pin for corresponding connection with a first pin on the array substrate; and a second alignment mark located at a matching range of the second pin for use in The first alignment mark on the array substrate is aligned; the second offset mark is obtained by the first alignment mark and the second alignment mark, and is located in a matching preset range of the second pin, and is used to indicate the first The deviation of the pin from the second pin.
  • the first offset mark is a first alignment scale.
  • 1 is a schematic view of an array substrate according to an embodiment of the present invention
  • FIG. 2 is a partially enlarged schematic view of FIG. 1
  • FIG. 3 is a schematic diagram of a preferred flip chip according to an embodiment of the present application. Description will be made below with reference to Figs. 1 to 3 . It should be noted that the number and angles of the pins in the figures are for convenience only and are not intended to limit the number and angle of the pins of the present application.
  • the array substrate 100 may include a plurality of pins 11, an alignment mark 12, and a first alignment scale 30.
  • the flip chip 200 may include a plurality of leads 21 and an alignment mark 22.
  • the array substrate 100 includes a display area and a non-display area.
  • the non-display area includes a bonding area, and a plurality of pins 11 are disposed in the bonding area.
  • the plurality of pins 11 are used for one-to-one correspondence with the plurality of pins 21 on the flip chip 200.
  • the plurality of pins 21 are used for one-to-one correspondence with the plurality of pins 11 on the array substrate 100.
  • the alignment mark 12 is disposed on at least one side of the plurality of pins 11, and the alignment mark 12 is used for aligning the alignment mark 22 on the flip chip 200.
  • the alignment mark 22 is disposed on the plurality of pins. At least one side of the 21, the alignment mark 22 is used to align with the alignment mark 12 on the array substrate 100.
  • the first alignment scale 30 is disposed on at least one side of the plurality of pins 11, and the first alignment scale 30 is used to indicate the alignment deviation of the plurality of pins 11 and the plurality of pins 21.
  • the alignment mark 12 and the alignment mark 22 are first aligned, and the alignment mark 12 and the alignment mark 22 are coincident.
  • the alignment offset of the pin 11 and the pin 21 in the lateral direction or the longitudinal direction is determined by the first alignment scale 30, and the array substrate 100 is moved according to the alignment deviation and the first alignment scale 30. Or the flip chip 200 is precisely aligned.
  • the first alignment scale 30 is adjacent to the outermost pin 11 of the plurality of pins 11, that is, the first alignment scale 30 and the plurality of pins 11 The closest pin 11 of the first alignment scale 30 is adjacent. As shown in FIG. 2, the first alignment scale 30 is adjacent to the leftmost pin 11.
  • the first alignment scale 30 includes a lateral alignment scale and/or a longitudinal alignment scale.
  • the plurality of pins 11 are obliquely disposed, in other words, the plurality of pins 11 are not perpendicular to the longitudinal direction or the lateral direction and are not parallel, that is, a plurality of pins 11 or a plurality of pins 11 lines intersect each other.
  • the inclination angle of the plurality of pins 11 with respect to the lateral direction or the longitudinal direction is 30 degrees to 75 degrees, and preferably, the inclination angle is 45 degrees, 30 degrees, or 60 degrees.
  • the pins 11 can be arranged in parallel with each other.
  • the pin 21 has a similar setting to the pin 11, and will not be described herein again in this embodiment.
  • At least one of the plurality of pins 11 on the left and right sides is inclined with respect to at least one of the pins 11 at the center position and is inclined in the opposite direction.
  • at least one of the pins 11 at the center position is parallel to the longitudinal direction.
  • at least one of the pins 11 on the left side is inclined to the left by a first angle with respect to at least one of the pins 11 of the center position, and at least one of the pins 11 of the right side is opposite to the center position.
  • the pin 11 is inclined to the right by a second angle.
  • the first angle or the second angle may be any value from 30 degrees to 75 degrees.
  • the first angle or the second angle is 45 degrees and 30 degrees. Or 60 degrees.
  • the pin 21 has a similar setting with respect to the pin 11. For the specific setting of the pin 21, the embodiment of the present application will not be described herein.
  • the shape of the alignment mark 12 may be a circle, a cross, a triangle, a trapezoid, or a chevron.
  • the registration mark 22 is identical or matched to the shape of the alignment mark 12.
  • the shape of the alignment mark 22 corresponding to the alignment mark 12 may be a circle, a cross, a triangle, a trapezoid or a chevron or the like.
  • the cross mark 22 is taken as an example.
  • the shape in which the alignment mark 12 is paired with the alignment mark 22 is taken as an example.
  • the alignment mark 12 located on either side of the plurality of pins 11 is set to at least one.
  • the central axes of all of the alignment marks 12 on either side of the plurality of pins 11 are on the same straight line.
  • the alignment marks 12 are disposed on both sides of the plurality of pins 11 , and the alignment marks 12 on both sides of the plurality of pins 11 are symmetrical.
  • the alignment marks 22 are disposed on both sides of the plurality of pins 21, and the alignment marks 22 on both sides of the plurality of pins 21 are symmetrical.
  • the pin 21 has a similar setting with respect to the pin 11. For the specific setting of the pin 21, the embodiment of the present application will not be described herein.
  • the area where the alignment mark 12 is located is set to be transparent, and the area where the first offset mark is located is set to be transparent.
  • FIG. 4 is a schematic view of an array substrate according to another embodiment of the present application; and FIG. 5 is a partially enlarged schematic view of FIG.
  • the array substrate 100' shown in FIG. 4 is different from the above array substrate 100 in that the first offset mark is a first alignment mark.
  • the array substrate 100' shown in FIG. 4 may include a plurality of pins 11, an alignment mark 12, and a first alignment mark.
  • the first alignment label includes a plurality of one-to-one correspondences of the first lateral alignment label 51 and the first longitudinal alignment label 52, for example, the first lateral alignment label 51 and the first vertical direction.
  • the registration number 52 includes one-to-one correspondence: A000, A001 to A009.
  • the offset mark being an embodiment of the alignment scale
  • the offset of the pin in the lateral direction is determined according to the first lateral alignment mark 51, Then, instead of calculating the distance that needs to be moved in the longitudinal direction, it is possible to directly move to the corresponding first longitudinal alignment label 52, for example, the lateral offset to A001, and the longitudinal direction corresponding to the movement to A001.
  • the first lateral alignment mark 51 is adjacent to the outermost pin 11 of the plurality of pins 11. As shown in FIG. 4, the first lateral alignment mark 51 is adjacent to the leftmost pin 11.
  • the present application provides a display device including the above array substrate 100 and flip chip 200, or array substrate 100' and flip chip 200.
  • Embodiments of the present application provide a flip chip including at least one second pin, a second alignment mark, and a second offset mark, wherein at least one second pin is used for at least one first on the array substrate a pin corresponding connection; a second alignment mark is disposed on at least one side of the at least one second pin, and a second alignment mark is used for aligning with the first alignment mark on the array substrate; The offset mark is obtained by the first alignment mark and the second alignment mark, the second offset mark is disposed on at least one side of the at least one second pin, and the second offset mark is used to indicate the at least one A misalignment of a pin with the at least one second pin.
  • the second offset mark is a second alignment scale.
  • FIG. 6 is a schematic diagram of an array substrate according to still another embodiment of the present application.
  • FIG. 7 is a schematic diagram of a flip chip provided by still another embodiment of the present application.
  • the array substrate 100" shown in FIG. 6 is different from the array substrate 100 shown in FIG. 1 in that the array substrate 100" shown in FIG. 6 does not include the first alignment scale 30, and the flip chip 200 shown in FIG.
  • the difference from the flip chip 200 shown in FIG. 3 is that the flip chip 200' shown in FIG. 7 includes the second alignment scale 40. That is, in the embodiment shown in FIGS. 6 and 7, with respect to the embodiment shown in FIGS. 1 and 3, the alignment scale is provided on the flip chip instead of the array substrate.
  • the second alignment scale 40 is disposed on at least one side of the plurality of pins 21 for indicating the alignment deviation of the plurality of pins 11 and the plurality of pins 21.
  • the second alignment scale 40 is adjacent to the outermost pin 21 of the plurality of leads 21.
  • the second alignment scale 40 includes a lateral alignment scale and/or a longitudinal alignment scale.
  • the specific setting of the second alignment scale 40 is similar to that of the first alignment scale 30 described above, and the embodiments of the present application are not described in detail herein.
  • the area where the alignment mark 22 is located is set to transmit light
  • the area where the second offset mark 40 is located is set to transmit light
  • FIG. 8 is a schematic view of a flip chip provided by another embodiment of the present application; and FIG. 9 is a partially enlarged view of FIG.
  • the flip chip 200" shown in Fig. 8 is different from the above flip chip 200' in that the second offset mark is a second alignment mark.
  • the flip chip 200" as shown in Fig. 8 may include: Pin 21, alignment mark 22, and second alignment label.
  • the second alignment label includes a plurality of one-to-one correspondences of the second lateral alignment label 61 and the second longitudinal alignment label 62, for example, the second lateral alignment label 61 and the second longitudinal direction.
  • the alignment mark 62 includes one-to-one correspondence: B000, B001 to B009.
  • the offset mark being an embodiment of the alignment scale
  • the offset of the pin in the lateral direction is determined according to the second lateral alignment mark 61.
  • the second lateral alignment mark 61 is adjacent to the outermost pin 21 of the plurality of pins 21. As shown in FIG. 4, the second lateral alignment mark 61 is adjacent to the leftmost pin 21.
  • Another display device provided by the present application includes the above array substrate 100' and flip chip 200', or array substrate 100' and flip chip 200".
  • the present application provides a method for aligning an array substrate and a flip chip, comprising: providing at least one first pin on the first device, the at least one first pin being used for at least one of the second devices a second pin correspondingly connected; a first alignment mark is disposed on the first device, the first alignment mark is used for aligning with a second alignment mark disposed on the second device; Obtaining a first offset mark by the first alignment mark and the second alignment mark and setting the first offset mark on the first device, the first offset mark being used to indicate Deviating a deviation of the at least one first pin from the at least one second pin; aligning the first device with the second device according to the alignment deviation; the first device is an array In one of the substrate and the flip chip, the second device is the other of the array substrate and the flip chip.
  • the first alignment mark is set on the first device, including:
  • the first alignment mark is disposed on at least one side of the at least one first pin.
  • setting the first offset flag on the first device includes:
  • the first offset mark is disposed on at least one side of the first pin.
  • FIG. 10 is a schematic flowchart diagram of a aligning method according to still another embodiment of the present application. As shown in FIG. 10, the alignment method provided by the embodiment of the present application includes:
  • Step S10 correspondingly connecting the first pin on the first device with the second pin on the second device.
  • Step S20 align the first alignment mark on the first device with the second alignment mark on the second device.
  • Step S30 indicating a registration deviation of the first pin and the second pin by using the first offset mark, wherein the first offset mark is derived according to the first alignment mark and the second alignment mark.
  • Step S40 Align the first device with the second device according to the registration deviation.
  • the alignment method provided by the embodiment of the present application achieves accurate alignment of the first device and the second device by means of pins, alignment marks and offset marks.
  • the alignment method of the present application is described below with reference to the array substrate 100 and the flip chip 200 provided in the above embodiments of the present application.
  • the method includes: arranging at least one pin 11 on the array substrate 100, and at least one pin 11 is used for At least one pin 21 on the flip chip 200 is correspondingly connected; the alignment mark 12 is disposed on at least one side of the at least one pin 11, and the alignment mark 12 is used for being disposed on the flip chip 200 Aligning the alignment mark 22; obtaining the first offset mark by the alignment mark 12 and the alignment mark 22, and setting the first offset mark on at least one side of the pin 11, the first offset mark The alignment deviation of the at least one pin 11 and the at least one pin 21 is indicated, and the array substrate 100 is aligned with the flip chip 200 according to the alignment deviation.
  • the array substrate 100 and the flip chip 200 are taken as an example here. It can be understood by those skilled in the art that the above alignment method is also applicable to the array substrate and the flip chip in other embodiments described in the present application, for example, an array.
  • the array substrate, the flip chip, the alignment method thereof and the display device provided by the embodiments of the present application are provided with the alignment mark for aligning the pins on the array substrate and the pins on the flip chip.
  • An offset flag for indicating the alignment deviation of the pins on the array substrate and the pins on the flip chip is also provided, so that after the alignment is performed by the alignment mark, the offset mark can be used to determine the alignment deviation Then, the offset mark is used for accurate alignment, so that even if the oblique pin is affected by thermal expansion during the process, and the alignment mode of the alignment mark is no longer effective, the offset mark can be accurately combined with the offset mark. Bit.

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Abstract

本申请实施例提供一种阵列基板、覆晶薄膜、显示装置及对位方法，所述阵列基板包括第一引脚，用于与覆晶薄膜上的第二引脚对应连接；第一对位标记，位于第一引脚的对位预设范围，用于与覆晶薄膜上的第二对位标记进行对位；第一偏移标记，通过第一对位标记及第二对位标记获得，位于第一引脚的对位预设范围，用于指示第一引脚与第二引脚的对位偏差。通过本申请，能够实现阵列基板和覆晶薄膜的精准对位。

Description

阵列基板、覆晶薄膜、显示装置及对位方法
本申请要求2018年04月02日提交的申请号为No.201810283325.3的中国申请的优先权，通过引用将其全部内容并入本文。
技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板、覆晶薄膜、显示装置及对位方法。
发明背景
柔性显示装置是指显示面板可弯曲变形的显示装置。柔性显示装置作为新一代的显示器件，因其具有薄而轻、高对比度、快速响应、宽视角、高亮度、全彩色等优点，在手机、个人数字助理(Personal Digital Assistant,PDA)、数码相机、车载显示、笔记本电脑、壁挂电视以及军事领域等具有十分广泛的应用前景。
柔性显示装置中的覆晶薄膜(Chip On Film,COF)上的引脚/端子/电极需与屏体上的引脚进行对位。但是，由于集成度的提升以及温度、湿度等环境因素影响，现有COF和屏体的对位精准性不高。
发明内容
有鉴于此，本申请实施例提供一种阵列基板、覆晶薄膜、显示装置及对位方法，用以解决现有技术中阵列基板上的引脚与COF上的引脚无法精准对位的问题。
为了达到上述目的，第一方面，本申请提供一种阵列基板，包括第一引脚，用于与覆晶薄膜上的第二引脚对应连接；第一对位标记，位于第一引脚的对位预设范围，用于与覆晶薄膜上的第二对位标记进行对位；第一偏移标记，通过第一对位标记及第二对位标记获得，位于第一引脚的对位预设范围，用于指示第一引脚与第二引脚的对位偏差。
进一步地，第一引脚包括多个，第二引脚包括多个，第一偏移标记与多个第一引脚中的距离第一对位标记最近的第一引脚相邻。
进一步地，多个第二引脚或多个第二引脚所在直线相互交叉。
进一步地，第一偏移标记包括第一对位刻度，第一对位刻度包括横向对位刻度和/或纵向对位刻度。
进一步地，第一偏移标记包括第一对位标号，第一对位标号包括第一横向对位标号以及与第一横向对位标号对应的第一纵向对位标号。
第二方面，本申请还提供一种覆晶薄膜，包括第二引脚，用于与阵列基板上的第一引脚对应连接；第二对位标记，位于第二引脚的对位预设范围，用于与阵列基板上的第一对位标记进行对位；第二偏移标记，通过第一对位标记及第二对位标记获得，位于第二引脚的对位预设范围，用于指示第一引脚与第二引脚的对位偏差。
进一步地，第一引脚包括多个，第二引脚包括多个，第二偏移标记与多个第二引脚中的距离第二对位标记最近的第二引脚相邻。
进一步地，多个第一引脚或多个第一引脚所在直线相互交叉。
进一步地，第二偏移标记包括第二对位刻度，第二对位刻度包括横向对位刻度和/或纵向对位刻度。
进一步地，第二偏移标记包括第二对位标号，第二对位标号包括第二横向对位标号以及与第二横向对位标号对应的第二纵向对位标号。
第三方面，本申请还提供一种显示装置，该显示装置包括上述任一实施例所提及的阵列基板，还包括覆晶薄膜，覆晶薄膜包括第二引脚、第二对位标记和第二偏移标记。
第四方面，本申请还提供一种显示装置，该显示装置包括上述任一实施例所提及的覆晶薄膜，还包括阵列基板，阵列基板包括第一引脚、第一对位标记和第一偏移标记。
第五方面，本申请还提供一种对位方法，该对位方法包括将第一装置上的第一引脚与第二装置上的第二引脚进行对应连接；将第一装置上的第一对位标记与第二装置上的第二对位标记进行对位；利用第一偏移标记指示第一引脚与第二引脚的对位偏差，其中第一偏移标记根据第一对位标记及第二对位标记得出；根据对位偏差对位第一装置与第二装置。
进一步地，第一装置为阵列基板与覆晶薄膜中的一者，第二装置为阵列基板与覆晶薄膜中的另一者。
本申请实施例提供的阵列基板、覆晶薄膜、显示装置及对位方法，除了设置了用于使得阵列基板上的引脚和覆晶薄膜上的引脚对位的对位标记之外，还设置了用于指示阵列基板上的引脚和覆晶薄膜上的引脚的对位偏差的偏移标记，这样，在利用对位标记进行对位后，可利用偏移标记确定对位偏差，进而利用偏移标记进行精准对位，使得即使斜形的引脚在制程过程中受热膨胀影响，仍然可以结合偏移标记进行精准对位。
附图简要说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例 或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一实施例提供的阵列基板的示意图；
图2为图1部分放大示意图；
图3为本申请一实施例提供的覆晶薄膜的示意图；
图4本申请另一实施例提供的阵列基板的示意图；
图5为图4的部分放大示意图；
图6为本申请再一实施例提供的阵列基板的示意图；
图7为本申请再一实施例提供的覆晶薄膜的示意图；
图8为本申请又一实施例提供的覆晶薄膜的示意图；
图9为图8的部分放大示意图；
图10为本申请再一实施例提供的对位方法的流程示意图。
实施本发明的方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请提供的阵列基板，包括：第一引脚，用于与覆晶薄膜上的第二引脚对应连接；第一对位标记，位于第一引脚的对位预设范围，用于与覆晶薄膜上的第二对位标记进行对位；第一偏移标记，通过第一对位标记及第二对位标记获得，位于第一引脚的对位预设范围，用于指示第一引脚与第二引脚的对位偏差。
本申请提供的覆晶薄膜，包括：第二引脚，用于与阵列基板上的第一引脚对应连接；第二对位标记，位于第二引脚的对位预设范围，用于与阵列基板上的第一对位标记进行对位；第二偏移标记，通过第一对位标记及第二对位标记获得，位于第二引脚的对位预设范围，用于指示第一引脚与第二引脚的对位偏差。
应当理解，对位预设范围可根据实际情况自行设定，本申请对此不进行统一限定。
在本申请的一实施方式中，上述第一偏移标记为第一对位刻度。图1为本申请一实施例提供的阵列基板的示意图，图2为图1部分放大示意图，图3为本申请一实施例提供的优选覆晶薄膜的示意图。以下结合图1至图3进行说明。需要说明的是，图中的引脚的数量和角度仅是为了示意方便，并非用于限定本申请的 引脚的数量和角度。
如图1、图2所示，阵列基板100可以包括：多个引脚11、对位标记12以及第一对位刻度30。如图3所示，覆晶薄膜200可以包括：多个引脚21以及对位标记22。
阵列基板100包括显示区以及非显示区，非显示区包括邦定区，多个引脚11设置于邦定区。多个引脚11用于与覆晶薄膜200上的多个引脚21一一对应连接，同样的，多个引脚21用于与阵列基板100上的多个引脚11一一对应连接。对位标记12设置于多个引脚11的至少一侧，对位标记12用于与覆晶薄膜200上的对位标记22进行对位，同样的，对位标记22设置于多个引脚21的至少一侧，对位标记22用于与阵列基板100上的对位标记12进行对位。
第一对位刻度30设置于多个引脚11的至少一侧，第一对位刻度30用于指示多个引脚11与多个引脚21的对位偏差。
在阵列基板100的多个引脚11与覆晶薄膜200的多个引脚21进行对位时，首先将对位标记12与对位标记22对位，对位标记12与对位标记22重合或配对而完成对位后，利用第一对位刻度30确定引脚11与引脚21在横向方向或纵向方向上的对位偏差，根据对位偏差以及第一对位刻度30移动阵列基板100或覆晶薄膜200进行精准对位。
在本申请的一实施方式中，第一对位刻度30与多个引脚11中的位于最外侧的引脚11相邻，也就是说，第一对位刻度30与多个引脚11中的距离第一对位刻度30最近的引脚11相邻。如图2所示，第一对位刻度30与最左侧的引脚11相邻。
在本申请的一实施方式中，如图2所示，第一对位刻度30包括横向对位刻度和/或纵向对位刻度。
在对位标记12与对位标记22对位后，当最外侧的引脚21相对于最外侧的引脚11在横向方向上的偏移量为L时，则，在进行精准对位时，纵向方向上的移动距离D＝L*tanA，此时，利用第一对位刻度30在纵向方向上移动距离D，即可完成引脚11和引脚21的精准对位，其中，A为最外侧的引脚11相对于横向方向的倾斜角度。
在本申请的一实施方式中，多个引脚11倾斜设置，换言之，多个引脚11与纵向方向或横向方向不垂直且不平行，也就是说，多个引脚11或者多个引脚11所在直线相互交叉。具体的，多个引脚11相对于横向方向或纵向方向的倾斜角度为30度至75度，较佳的，倾斜角度为45度、30度、或60度。具体的，各引脚11之间可以相互平行设置。引脚21对应于引脚11具有相似设置，本申请实施例在此不再赘述。
在本申请的一实施方式中，多个引脚11中位于左右两侧的至少一个引脚11 相对于位于中心位置的至少一个引脚11倾斜且倾斜方向相反。具体的，中心位置的至少一个引脚11与纵向方向相平行。示例性的，如图1所示，左侧的至少一个引脚11相对于中心位置的至少一个引脚11向左倾斜第一角度，右侧的至少一个引脚11相对于中心位置的至少一个引脚11向右倾斜第二角度，具体的，第一角度或第二角度可以为30度至75度中的任意数值，较佳的，第一角度或第二角度为45度、30度、或60度。引脚21对应于引脚11具有相似设置，对于引脚21的具体设置，本申请实施例在此不再赘述。
在本申请的一实施方式中，对位标记12的形状可以为圆形、十字形、三角形、梯形或凸字形等。对位标记22与对位标记12的形状相同或相配对。对位标记22对应于对位标记12的形状可以为圆形、十字形、三角形、梯形或凸字形等。图3中以对位标记22为十字形为例。图1中以对位标记12为与对位标记22相配对的形状为例。
在本申请的一实施方式中，位于多个引脚11任一侧的对位标记12设置为至少一个。较佳的，位于多个引脚11任一侧的全部对位标记12的中心轴线在同一直线上。较佳的，如图1所示，多个引脚11的两侧均设置有对位标记12，多个引脚11两侧的对位标记12相对称，同样的，如图3所示，多个引脚21的两侧均设置有对位标记22，多个引脚21两侧的对位标记22相对称。引脚21对应于引脚11具有相似设置，对于引脚21的具体设置，本申请实施例在此不再赘述。
具体的，对位标记12所在的区域设为透光，第一偏移标记所在的区域设为透光。
图4为本申请另一实施例提供的阵列基板的示意图；图5为图4的部分放大示意图。图4所示的阵列基板100′与上述阵列基板100的不同之处在于，第一偏移标记为第一对位标号。如图4所示的阵列基板100′可以包括：多个引脚11、对位标记12以及第一对位标号。如图4、图5所示，第一对位标号包括多个一一对应的第一横向对位标号51和第一纵向对位标号52，例如，第一横向对位标号51和第一纵向对位标号52包括一一对应的：A000、A001至A009。第一纵向对位标号52的设置位置由第一横向对位标号51的设置位置和A确定，相邻纵向对位标号之间的间距＝相邻横向对位标号之间的间距*tanA，其中，A为与第一横向对位标号51相邻的引脚11相对于横向方向的倾斜角度。这样，相对于偏移标记是对位刻度的实施方式，在对位标记12与对位标记22重合或配对后，根据第一横向对位标号51确定了引脚在横向方向上的偏移，之后，不用计算在纵向方向上需要移动的距离，直接移动至对应的第一纵向对位标号52即可，例如，横向偏移至A001，纵向方向对应移动至A001即可。
在本申请的一实施方式中，第一横向对位标号51与多个引脚11中的位于最外侧的引脚11相邻。如图4所示，第一横向对位标号51与最左侧的引脚11相邻。
本申请提供一种显示装置，其包括上述阵列基板100与覆晶薄膜200，或者，阵列基板100′与覆晶薄膜200。
本申请实施例提供一种覆晶薄膜，包括至少一个第二引脚、第二对位标记以及第二偏移标记，其中，至少一个第二引脚用于与阵列基板上的至少一个第一引脚对应连接；第二对位标记设置于所述至少一个第二引脚的至少一侧，第二对位标记用于与所述阵列基板上的第一对位标记进行对位；第二偏移标记通过第一对位标记和第二对位标记获得，第二偏移标记设置于所述至少一个第二引脚的至少一侧，第二偏移标记用于指示所述至少一个第一引脚与所述至少一个第二引脚的对位偏差。
在本申请的一实施方式中，上述第二偏移标记为第二对位刻度。图6为本申请再一实施例提供的阵列基板的示意图。图7为本申请再一实施例提供的覆晶薄膜的示意图。图6所示的阵列基板100″与上述图1所示的阵列基板100的区别在于，图6所示的阵列基板100″不包括第一对位刻度30，图7所示的覆晶薄膜200′与图3所示的覆晶薄膜200的区别在于，图7所示的覆晶薄膜200′包括第二对位刻度40。即，图6、图7所示的实施例相对于图1、图3所示的实施例，对位刻度设置于覆晶薄膜上而非阵列基板上。
第二对位刻度40设置于多个引脚21的至少一侧，第二对位刻度40用于指示多个引脚11与多个引脚21的对位偏差。
在本申请的一实施方式中，第二对位刻度40与多个引脚21中的位于最外侧的引脚21相邻。
在本申请的一实施方式中，第二对位刻度40包括横向对位刻度和/或纵向对位刻度。
第二对位刻度40的具体设置与上述第一对位刻度30相似，本申请实施例在此不再详述。
具体的，对位标记22所在的区域设为透光，第二偏移标记40所在的区域设为透光。
图8为本申请又一实施例提供的覆晶薄膜的示意图；图9为图8的部分放大示意图。图8所示的覆晶薄膜200″与上述覆晶薄膜200′的不同之处在于，第二偏移标记为第二对位标号。如图8所示的覆晶薄膜200″可以包括：多个引脚21、对位标记22以及第二对位标号。如图8、图9所示，第二对位标号包括多个一一对应的第二横向对位标号61和第二纵向对位标号62，例如，第二横向对位标号61和第二纵向对位标号62包括一一对应的：B000、B001至B009。第二纵向对位标号62的设置位置由第二横向对位标号61的设置位置和A确定，相邻纵向对位标号之间的间距＝相邻横向对位标号之间的间距*tanA，其中，A为与第二横向对位标号61相邻的引脚21相对于横向方向的倾斜角度。这样，相对于偏移标记 是对位刻度的实施方式，在对位标记12与对位标记22重合或配对后，根据第二横向对位标号61确定了引脚在横向方向上的偏移，之后，不用计算在纵向方向上需要移动的距离，直接移动至对应的第二纵向对位标号62即可，例如，横向偏移至B001，纵向方向对应移动至B001即可。
在本申请的一实施方式中，第二横向对位标号61与多个引脚21中的位于最外侧的引脚21相邻。如图4所示，第二横向对位标号61与最左侧的引脚21相邻。
本申请提供的另一种显示装置，其包括上述阵列基板100′与覆晶薄膜200′，或者，阵列基板100′与覆晶薄膜200″。
本申请提供一种阵列基板与覆晶薄膜的对位方法，包括：于第一装置上设置至少一个第一引脚，所述至少一个第一引脚用于与设置于第二装置上的至少一个第二引脚对应连接；于所述第一装置上设置第一对位标记，所述第一对位标记用于与设置于所述第二装置上的第二对位标记进行对位；通过所述第一对位标记及所述第二对位标记获得第一偏移标记并于所述第一装置上设置所述第一偏移标记，所述第一偏移标记用于指示所述至少一个第一引脚与所述至少一个第二引脚的对位偏差；根据所述对位偏差将所述第一装置与所述第二装置进行对位；所述第一装置为阵列基板与覆晶薄膜中的一者，所述第二装置为所述阵列基板与所述覆晶薄膜中的另一者。
在本申请的一实施方式中，于所述第一装置上设置第一对位标记，包括：
将所述第一对位标记设置于所述至少一个第一引脚的至少一侧。
在本申请的一实施方式中，于所述第一装置上设置所述第一偏移标记，包括：
将所述第一偏移标记设置于所述第一引脚的至少一侧。
图10为本申请再一实施例提供的对位方法的流程示意图。如图10所示，本申请实施例提供的对位方法包括：
步骤S10：将第一装置上的第一引脚与第二装置上的第二引脚进行对应连接。
步骤S20：将第一装置上的第一对位标记与第二装置上的第二对位标记进行对位。
步骤S30：利用第一偏移标记指示第一引脚与第二引脚的对位偏差，其中，第一偏移标记根据第一对位标记及第二对位标记得出。
步骤S40：根据对位偏差对位第一装置与第二装置。
也就是说，本申请实施例提供的对位方法，借助于引脚、对位标记以及偏移标记实现了第一装置和第二装置的精准对位。
以下结合本申请上述实施例提供的阵列基板100与覆晶薄膜200说明本申请的对位方法，包括：于所述阵列基板100上设置至少一个引脚11，至少一个引脚11用于与设于覆晶薄膜200上的至少一个引脚21对应连接；将对位标记12设置于所述至少一个引脚11的至少一侧，对位标记12用于与设于所述覆晶薄膜200 上的对位标记22进行对位；通过所述对位标记12及对位标记22获得第一偏移标记，将第一偏移标记设置于引脚11的至少一侧，第一偏移标记用于指示至少一个引脚11与至少一个引脚21的对位偏差，根据所述对位偏差所述阵列基板100与覆晶薄膜200进行对位。此处以阵列基板100和覆晶薄膜200为例进行说明，本领域技术人员可以理解的是，上述对位方法同样适用于本申请描述的其他实施方式中的阵列基板与覆晶薄膜，例如，阵列基板100′和覆晶薄膜200，或者，阵列基板100′与覆晶薄膜200′，或者，阵列基板100′与覆晶薄膜200″。
本申请实施例提供的阵列基板、覆晶薄膜及其对位方法及显示装置，除了设置了用于使得阵列基板上的引脚和覆晶薄膜上的引脚对位的对位标记之外，还设置了用于指示阵列基板上的引脚和覆晶薄膜上的引脚的对位偏差的偏移标记，这样，在利用对位标记进行对位后，可利用偏移标记确定对位偏差，进而利用偏移标记进行精准对位，使得即使斜形的引脚在制程过程中受热膨胀影响，单纯依靠对位标记的对位方式不再有效的情况下，可以结合偏移标记进行精准对位。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (14)

  1. 一种阵列基板，其中，包括：
    第一引脚，用于与覆晶薄膜上的第二引脚对应连接；
    第一对位标记，位于所述第一引脚的对位预设范围，用于与所述覆晶薄膜上的第二对位标记进行对位；
    第一偏移标记，通过所述第一对位标记及所述第二对位标记获得，位于所述第一引脚的对位预设范围，用于指示所述第一引脚与所述第二引脚的对位偏差。
  2. 根据权利要求1所述的阵列基板，其中，所述第一引脚包括多个，所述第二引脚包括多个，所述第一偏移标记与所述多个第一引脚中的距离所述第一对位标记最近的第一引脚相邻。
  3. 根据权利要求2所述的阵列基板，其中，所述多个第二引脚或所述多个第二引脚所在直线相互交叉。
  4. 根据权利要求1所述的阵列基板，其中，所述第一偏移标记包括第一对位刻度，所述第一对位刻度包括横向对位刻度和/或纵向对位刻度。
  5. 根据权利要求1所述的阵列基板，其中，所述第一偏移标记包括第一对位标号，所述第一对位标号包括第一横向对位标号以及与所述第一横向对位标号对应的第一纵向对位标号。
  6. 一种覆晶薄膜，其中，包括：
    第二引脚，用于与阵列基板上的第一引脚对应连接；
    第二对位标记，位于所述第二引脚的对位预设范围，用于与所述阵列基板上的第一对位标记进行对位；
    第二偏移标记，通过所述第一对位标记及所述第二对位标记获得，位于所述第二引脚的对位预设范围，用于指示所述第一引脚与所述第二引脚的对位偏差。
  7. 根据权利要求6所述的覆晶薄膜，其中，所述第一引脚包括多个，所述第二引脚包括多个，所述第二偏移标记与所述多个第二引脚中的距离所述第二对位标记最近的第二引脚相邻。
  8. 根据权利要求7所述的覆晶薄膜，其中，所述多个第一引脚或所述多个第一引脚所在直线相互交叉。
  9. 根据权利要求1所述的覆晶薄膜，其中，所述第二偏移标记包括第二对位刻度，所述第二对位刻度包括横向对位刻度和/或纵向对位刻度。
  10. 根据权利要求1所述的覆晶薄膜，其中，所述第二偏移标记包括第二对位标号，所述第二对位标号包括第二横向对位标号以及与所述第二横向对位标号对应的第二纵向对位标号。
  11. 一种显示装置，其中，包括如权利要求1至5任一所述的阵列基板，还包括覆晶薄膜，所述覆晶薄膜包括第二引脚、第二对位标记和第二偏移标记。
  12. 一种显示装置，其中，包括如权利要求6至10任一所述的覆晶薄膜，还包括阵列基板，所述阵列基板包括第一引脚、第一对位标记和第一偏移标记。
  13. 一种对位方法，其中，包括：
    将第一装置上的第一引脚与第二装置上的第二引脚进行对应连接；
    将所述第一装置上的第一对位标记与所述第二装置上的第二对位标记进行对位；
    利用第一偏移标记指示所述第一引脚与所述第二引脚的对位偏差，其中所述第一偏移标记根据所述第一对位标记及所述第二对位标记得出；
    根据所述对位偏差对位所述第一装置与所述第二装置。
  14. 根据权利要求13所述的对位方法，其中，所述第一装置为阵列基板与覆晶薄膜中的一者，所述第二装置为所述阵列基板与所述覆晶薄膜中的另一者。
PCT/CN2018/102687 2018-04-02 2018-08-28 阵列基板、覆晶薄膜、显示装置及对位方法 WO2019192137A1 (zh)

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