CN108428734A - 包括在有源鳍之间的突出绝缘部分的半导体器件 - Google Patents

包括在有源鳍之间的突出绝缘部分的半导体器件 Download PDF

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CN108428734A
CN108428734A CN201810224652.1A CN201810224652A CN108428734A CN 108428734 A CN108428734 A CN 108428734A CN 201810224652 A CN201810224652 A CN 201810224652A CN 108428734 A CN108428734 A CN 108428734A
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raceway groove
area
active fin
insulating layer
semiconductor devices
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CN108428734B (zh
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前田茂伸
姜熙秀
沈相必
洪秀宪
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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  • Electrodes Of Semiconductors (AREA)

Abstract

一种半导体器件可以包括：场绝缘层，其包括具有在第一和第二正交方向上延伸的平面主表面的第一区域以及垂直地设置在主表面上的第二区域，第二区域的顶表面离主表面具有特定距离；第一多沟道有源鳍和第二多沟道有源鳍，其在场绝缘层上延伸，第一多沟道有源鳍和第二多沟道有源鳍由场绝缘层的相对于第一多沟道有源鳍和第二多沟道有源鳍正交地延伸的第二区域分离；设置在第一多沟道有源鳍上的第一栅极以及设置在第二多沟道有源鳍上的第二栅极；以及设置在场绝缘层的第二区域与第一栅极之间的第一外延源/漏区以及设置在场绝缘层的第二区域与第二栅极之间的第二外延源/漏区。

Description

包括在有源鳍之间的突出绝缘部分的半导体器件
本申请是申请日为2013年11月29日且发明名称为“包括在有源鳍之间的突出绝缘部分的半导体器件”的中国发明专利申请201310628274.0的分案申请。
技术领域
本发明构思涉及半导体领域，更具体地，涉及包括多沟道有源鳍的半导体器件。
背景技术
已经提供了包括在基板上的鳍形或纳米线形多沟道有源图案(或硅本体)和在多沟道有源图案的表面上的栅极的多栅极晶体管结构。
由于多栅极晶体管可以采用三维沟道，所以可以比其他方法更容易地实现微缩(scaling)。此外，控制电流的能力也可以改善而不必增加多栅极晶体管中的栅极的长度。此外，可以更有效地解决短沟道效应，在短沟道效应中，沟道区的电势受到漏电压的影响。
发明内容
根据发明构思的实施方式可以提供包括在有源鳍之间的突出绝缘部分的半导体器件。按照这些实施方式，半导体器件可以包括场绝缘层，该场绝缘层包括在第一和第二正交方向延伸的平面主表面和相对于第一和第二正交方向从主表面突出特定距离的突出部分。第一和第二多沟道有源鳍可以在场绝缘层上延伸并可以通过突出部分彼此分离。导电层可以从突出部分的最上表面延伸以横跨位于第一和第二多沟道有源鳍之间的突出部分。
附图说明
通过参考附图详细描述优选的实施方式，本发明构思的上述及其他特征和优点将变得更加明显，附图中：
图1和图2是根据本发明构思的一些实施方式的半导体器件的布局图和透视图；
图3是示出在根据图1和2示出的本发明构思的一些实施方式的半导体器件中的多沟道有源图案和场绝缘层的局部透视图；
图4是沿图1和图2的线A-A所取的截面图；
图5是沿图1和图2的线B-B所取的截面图；
图6是示出图1和图2的区域C的透视图；
图7是根据本发明构思的一些实施方式的半导体器件对比常规布置的截面视图；
图8A是根据本发明构思的一些实施方式的半导体器件的截面图；
图8B是根据本发明构思的一些实施方式的半导体器件的截面图；
图8C是根据本发明构思的一些实施方式的半导体器件的截面图；
图8D是根据本发明构思的一些实施方式的半导体器件的截面图；
图9A是根据本发明构思的一些实施方式的半导体器件的透视图，图9B是沿图9A的线B-B所取的截面图；
图10A是根据本发明构思的一些实施方式的半导体器件的透视图；
图10B是示出图10A所示的半导体器件的多沟道有源图案和场绝缘层的局部透视图；
图11是根据本发明构思的一些实施方式的半导体器件的截面图；
图12是根据本发明构思的一些实施方式的半导体器件的截面图；
图13是根据本发明构思的一些实施方式的半导体器件的截面图；
图14A是根据本发明构思的一些实施方式的半导体器件的框图；
图14B是根据本发明构思的一些实施方式的半导体器件的框图；
图15A是根据本发明构思的一些实施方式的半导体器件的透视图；
图15B是根据本发明构思的一些实施方式的半导体器件的截面图；
图16至24示出根据图1-6的半导体器件的形成方法；
图25A和25B示出形成图8A的半导体器件的方法所提供的中间结构；
图26是包括根据本发明构思的一些实施方式的半导体器件的电子系统的框图；以及
图27A和27B示出示范半导体系统，其中可以采用根据本发明构思的一些实施方式的半导体器件。
具体实施方式
现在将在下文参考附图更充分地描述本发明构思，在附图中示出了本发明构思的示范实施方式。通过以下将参考附图更具体地描述的示范实施方式，本发明构思的优点和特征以及实现它们的方法将会明显。然而，应当指出，本发明构思不限于以下示范实施方式，而可以以各种形式实施。因此，提供示范实施方式仅为了公开本发明构思和让本领域技术人员知道本发明构思的类别。在附图中，本发明构思的实施方式不限于在此提供的特定示例，并为了清晰而被夸大。
在此使用的术语仅仅是为了描述特定实施方式的目的，而非旨在限制本发明。如在此所用的，单数术语“一”和“该”旨在也包括复数术语，除非上下文清楚地另有指示。如在此所用的，术语“和/或”包括一个或多个相关所列项目的任何及所有组合。将理解，当一元件被称为“连接到”或“耦接到”另一元件时，它可以直接连接到或耦接到另一元件，或者可以存在居间元件。
类似地，将理解，当一元件诸如层、区域或基板被称为“在”另一元件“上”时，它可以直接在另一元件上，或者可以存在居间元件。相反，术语“直接”意味着没有居间元件。将进一步理解，术语“包括”和/或“包含”当在此使用时，指定存在所述特征、整体、步骤、操作、元件和/或组件，但是不排除一个或多个其他特征、整体、步骤、操作、元件、组件和/或其组的存在或添加。
还将理解，虽然术语第一、第二、第三等等可以在此使用来描述各种元件，但这些元件不应被这些术语限制。这些术语仅用于区分一个元件与另一元件。因此，在一些实施方式中的第一元件在其他实施方式中可以被称为第二元件而不背离本发明的教导。在此说明和示出的本发明构思的多个方面的示范实施方式包括它们的互补对应物。相同的参考数字或相同的参考标记在说明书中始终表示相同的元件。
图1和图2分别是根据本发明构思的一些实施方式的半导体器件的布局图和透视图，图3是示出图1和图2所示的半导体器件中的多沟道有源图案和场绝缘层的局部透视图。具体地，图3示出图2所示的半导体器件的构造，除了正常栅极(在此有时被称为有源栅极)和虚拟栅极。图4是沿图1和图2的线A-A所取的截面图，图5是沿图1和图2的线B-B所取的截面图，图6是示出图1和图2的区域C的透视图，图7示出根据图1-6的半导体器件与常规布置的对比。
首先参考图1至图6，半导体器件1可以包括多个多沟道有源图案F1至F3(在此有时被称为“鳍”)、多个正常栅极147_1至147_5、场绝缘层110、多个虚拟栅极247_1和247_2以及多个源极/漏极161a和162a。
多个多沟道有源图案F1至F3可以在第二方向Y1延伸。每个多沟道有源图案F1到F3可以是基板101的一部分并且可以包括从基板101生长的外延层。在示出的实施方式中，以在纵向彼此首尾相连地布置的三个多沟道有源图案F1至F3作为示例，但本发明构思的方面不限于此。
在示出的实施方式中，以长方体形状的多沟道有源图案F1至F3作为示例，但本发明构思的方面不限于此。即，多沟道有源图案F1至F3可以被切角。具体地，多沟道有源图案F1至F3的拐角可以被圆化。由于多沟道有源图案F1到F3沿第二方向Y1在纵向延伸，所以它们可以包括沿第二方向Y1形成的长边和沿第一方向X1形成的短边。即使多沟道有源图案F1到F3的拐角被圆化，本领域技术人员也可以将长边和短边彼此区分。多沟道有源图案F1到F3可以是鳍形或纳米线形。在示出的实施方式中，以鳍形多沟道有源图案F1到F3作为示例。
多沟道有源图案F1到F3定义为包括用于多栅极晶体管中的有源图案。即，当多沟道有源图案F1到F3是鳍形时，沟道可以沿鳍的三个表面形成(在操作期间)，或者沟道可以形成在鳍的两个相反表面上。当多沟道有源图案F1到F3是纳米线形时，沟道可以形成在纳米线周围。场绝缘层110可以形成在基板101上且可以围绕多个多沟道有源图案F1到F3的一部分。场绝缘层可以形成为包括在彼此正交的两个方向(例如，X1和Y1)延伸的主表面109。
具体地，场绝缘层110可以包括具有不同高度的第一区(突出部分)111和第二区112。第二区112的高度可以是H0，第一区111的高度可以使得第一区从主表面109突出特定距离H1。具体地，例如，第一区111可以形成为将多沟道有源图案F1到F3的短边分离，第二区112可以形成为接触多沟道有源图案F1到F3的长边。第一区111可以形成在虚设栅极247_1和247_2的下方，第二区112可以形成在正常栅极147_1到147_5的下方。换句话说，场绝缘层110的一部分(即，第二区112)可以设置在相对的多沟道有源图案之间(例如，F1与F2之间或者F1与F3之间)。第一区111可以形成为在第一方向X1延伸，第二区112可以在第二方向Y1延伸。
此外，如图3所示，突出部分111可以被切口以围绕凹陷入其中的多沟道有源图案F1到F3的端部。即，第一区111可以包括第一部分111a和第二部分111b。第一部分111a和第二部分111b可以具有不同宽度。具体地，第二部分111b的宽度可以大于第一部分111a的宽度。结果，第二部分111b可以围绕多沟道有源图案F1至F3的每个端部。这样，可以防止将要形成在其上的场绝缘层110以及虚设栅极247_1和247_2不对准。如图3中进一步示出的，突出部分111相对于在X1和Y1两方向上的主表面109突出特定距离H1。场绝缘层110可以是氧化物层、氮化物层、氮氧化合物层或者其组合。
多个正常栅极147_1至147_5可以形成在相应的多沟道有源图案F1至F3上以交叉(cross)相应的多沟道有源图案F1至F3。例如，第一至第三正常栅极147_1、147_2和147_3可以形成在第一多沟道有源图案F1上，第四正常栅极147_4可以形成在第二多沟道有源图案F2上，第五正常栅极147_5可以形成在第三多沟道有源图案F3上。正常栅极147_1至147_5可以在第一方向X1延伸。
多个虚设栅极247_1和247_2可以形成在相应的场绝缘层110(即，场绝缘层110的第一区111)上以在X1方向横跨(cross over)突出部分111。例如，第一虚设栅极247_1可以形成在图2的左侧所示的第一区111上，第二虚设栅极247_2可以形成在图2的右侧所示的第一区111上。具体地，每个虚设栅极247_1和247_2可以一个接一个地形成在相应的第一区111上。没有形成两个或更多的虚设栅极247_1和247_2，但虚设栅极247_1和247_2是一个接一个地形成的，由此减小了布局尺寸。将理解，虚设栅极可以在X1方向延伸，例如，横跨另一鳍，以形成诸如传输晶体管(pass transistor)的有源栅极的一部分。
参考图4和5，每个正常栅极(例如，147_1)可以包括金属层MG1和MG2。如图4和5所示，正常栅极147_1可以配置为使得两个金属层MG1和MG2堆叠。第一金属层MG1可以控制功函数，第二金属层MG2可以填充由第一金属层MG1形成的空间。例如，第一金属层MG1可以包括TiN、TaN、TiC和TaC中的至少一个。此外，第二金属层MG2可以包括W或Al。正常栅极147_1可以通过例如置换工艺或后栅极工艺形成，但本发明构思的方面不限于此。
每个虚设栅极(例如，247_1)可以具有类似于正常栅极147_1的构造。如所示出的，虚设栅极247_1可以配置为使得两个金属层MG1和MG2堆叠。例如，第一金属层MG1可以控制功函数，第二金属层MG2可以填充由第一金属层MG1形成的空间。
栅绝缘层145可以形成在多沟道有源图案F1与正常栅极147_1之间。如图4所示，栅绝缘层145可以形成在多沟道有源图案F1的顶表面和侧表面上。此外，栅绝缘层145可以设置在正常栅极147_1与场绝缘层(即，第二区112)之间。栅绝缘层145可以包括具有比硅氧化物层高的介电常数的高k材料。例如，栅绝缘层145可以包括HfO2、ZrO2或Ta2O5。
再次参考图1至图6，多个源极/漏极161a和162a可以设置在多个正常栅极147_1至147_5之间以及正常栅极(例如147_1和147_4)与虚设栅极(例如，247_1)之间。在示出的实施方式中，通过掺杂杂质到多沟道有源图案F1至F3来形成源极/漏极161a和162a，但本发明构思的方面不限于此。
间隔物151可以包括氮化物层和氮氧化物层中的至少之一。间隔物151可以形成在多个多沟道有源图案F1至F3、多个正常栅极147_1至147_5以及多个虚设栅极247_1和247_2的侧壁上。
基板101可以包括从Si、Ge、SiGe、GaP、GaAs、SiC、SiGeC、InAs和InP构成的组中选择的一种或多种半导体材料。备选地，基板101可以是绝缘体上硅(SOI)基板。
参考图2和图5，如上所述，场绝缘层110的第一区111和第二区112具有不同的高度。第一区111的高度可以是H0+H1，第二区112的高度可以是H0。
至少一部分场绝缘层110的顶表面(即，第一区111的顶表面)高于正常栅极147_1至147_5的底表面。正常栅极147_1至147_5沿场绝缘层110的顶表面(即，第二区112的顶表面)和多沟道有源图案F1至F3的顶表面及侧表面形成。在正常栅极147_1至147_5中，术语“底表面”可以指正常栅极147_1至147_5的底表面的最低部分。在图2中，底表面可以相应于接触第二区112的顶表面的部分。
换句话说，第一区111的顶表面可以平行于(或在与其相同的水平处)或者高于源极/漏极161a和162a的顶表面。换句话说，第一区111的顶表面可以平行于或高于多沟道有源图案F1至F3的顶表面。在示出的实施方式中，第一区111的顶表面比多沟道有源图案F1至F3的顶表面高H2。
换句话说，虚设栅极247_1和247_2的高度不同于正常栅极147_1至147_5的高度。虚设栅极247_1和247_2的顶表面可以平行于正常栅极147_1至147_5的顶表面。例如，当虚设栅极247_1和247_2以及正常栅极147_1至147_5通过平坦化而形成时，其顶表面可以彼此平行。因此，当第一区111的顶表面高于多沟道有源图案F1至F3的顶表面时，虚设栅极247_1和247_2形成在第一区111上，正常栅极147_1至147_5形成在多沟道有源图案F1至F3上。因此，在截面图中，虚设栅极247_1和247_2的高度低于正常栅极147_1至147_5的高度。
在根据本发明构思的一些情况下的半导体器件在图7的左侧示出，常规半导体器件在图7的右侧示出，用于彼此比较。
在常规半导体器件中，例如，场绝缘层110不被分为第一区111和第二区112而是具有不变的高度。因此，在常规半导体器件中，场绝缘层110在第一多沟道有源图案F1与第二多沟道有源图案F2之间具有高度H0。此外，在常规半导体器件中，虚设栅极1247_1也设置在第一多沟道有源图案F1与第二多沟道有源图案F2之间的空间中。因此，形成在虚设栅极1247_1与第一多沟道有源图案F1之间的寄生电容C11以及形成在虚设栅极1247_1与第二多沟道有源图案F2之间的寄生电容C12相对大。寄生电容C11和C12可以不利地影响常规半导体器件的操作特性。例如，寄生电容C11和C12可以增加半导体器件的操作中的延迟时间。此外，由于在虚设栅极1247与第一多沟道有源图案F1之间以及在虚设栅极1247_1与第二多沟道有源图案F2之间存在相当大的接触面积，所以漏电流的量会是大的。
作为对比，在根据本发明构思的一些实施方式中的半导体器件中，由于第一区111的顶表面平行于(或在与其相同的水平处)或高于多沟道有源图案F1和F2的顶表面，所以虚设栅极247_1的最低部分不设置在第一多沟道有源图案F1与第二多沟道有源图案F2之间的空间中。因此，(形成在虚设栅极247_1与第一多沟道有源图案F1之间的)寄生电容C1以及(形成在虚设栅极247_1与第二多沟道有源图案F2之间的)寄生电容C2是相对小的。此外，由于在虚设栅极247_1与第一多沟道有源图案F1之间或者在虚设栅极247_1与第二多沟道有源图案F2之间存在小的接触面积，所以漏电流的量会是小的。
图8A是根据本发明构思的实施方式的半导体器件的截面图，图8B是根据本发明构思的实施方式的半导体器件的截面图。参考图8A，凹陷125可以形成在多个正常栅极147_1至147_5之间以及在位于正常栅极147_1至147_5与虚设栅极247_1和247_2之间的多个多沟道有源图案F1至F3中。
源极/漏极161和162形成在凹陷125中。源极/漏极161和162的每个可以包括外延层。即，源极/漏极161和162可以通过外延生长形成。此外，源极/漏极161和162可以是相对于多沟道有源图案F1至F3突出的提升源极/漏极。
如图8A所示，部分的源极/漏极161和162可以交叠间隔物145和245。即，该部分的源极/漏极161和162可以在间隔物145和245的下部分下方缩进，如标记167。
在半导体器件是PMOS晶体管的情形下，源极/漏极161和162可以包括压应力材料。例如，压应力材料可以是具有比硅(Si)大的晶格常数的材料，例如SiGe。压应力材料可以通过施加压应力到多沟道有源图案(例如F1)而改善沟道区的载流子(空穴)的迁移率。
然而，在半导体器件是NMOS晶体管的情形下，源极/漏极161和162可以包括与基板101相同的材料或者包括张应力材料。例如，当基板101包括Si时，源极/漏极161和162可以包括Si或具有比Si小的晶格常数的材料(例如SiC)。
场绝缘层111的顶表面可以平行于多沟道有源图案F1的顶表面。
图8B示出虚设栅极247_1和场绝缘层111未对准。根据图8B，当虚设栅极247_1和场绝缘层111未对准时，部分的虚设栅极247_1可以交叠多沟道有源图案F1的顶表面。
图8C是根据本发明构思的实施方式的半导体器件的截面图。
参考图8C，部分的提升源极/漏极162可以交叠间隔物245。半导体部分166可以位于提升源极/漏极162的交叠间隔物245的区域与间隔物245之间。
半导体部分166是因其被掩模119a覆盖而未被蚀刻的区域(例如参考图25B所描述的)。当在后面的步骤中形成提升源极/漏极162时半导体部分166可以有助于特定形状的外延生长。
图8D是根据本发明构思的实施方式的半导体器件的截面图。参考图8D，在根据本发明构思的实施方式的半导体器件中，源极/漏极161和162可以是提升源极/漏极。源极/漏极161和162的顶表面可以比多沟道有源图案F1至F3的顶表面高H5。此外，源极/漏极161和162以及正常栅极147可以通过间隔物151彼此绝缘。
设置在多个正常栅极147_1至147_5之间的源极/漏极161的高度以及设置在正常栅极147_1至147_5与虚设栅极247_1和247_2之间的源极/漏极162的高度彼此相等。将理解，术语“源极/漏极161和源极/漏极162的高度彼此相等”定义为包括工艺误差。
在根据本发明构思的实施方式的半导体器件中，如图8D所示，至少一部分场绝缘层110的顶表面(例如第一区111的顶表面)可以平行于或高于提升源极/漏极161和162的顶表面。在示出的实施方式中，至少一部分场绝缘层110的顶表面(例如第一区111的顶表面)可以比提升源极/漏极161和162的顶表面高H3。因此，形成在虚设栅极247_1和247_2与提升源极/漏极162之间的寄生电容C3和C4会是小的。此外，由于在每个虚设栅极247_1和247_2与提升源极/漏极162之间存在小的接触面积，所以漏电流的量可以是小的。
虚设栅极247_1和247_2的高度与正常栅极147_1至147_5的高度彼此不同。虚设栅极247_1和247_2的高度可以小于正常栅极147_1至147_5的高度。
图9A是根据本发明构思的一些实施方式的半导体器件的透视图，图9B是沿图9A的线B-B截取的截面图。参考图9A和9B，场绝缘层110可以包括具有不同高度的第一区111和第二区112。第二区112的高度可以是H0，第一区111的高度可以是H0+H4。第一区111的高度H0+H4可以小于图2所示的第一区111的高度H0+H1。
虚设栅极247_1和247_2的高度与正常栅极147_1至147_5的高度可以彼此不同。虚设栅极247_1和247_2的高度可以大于正常栅极147_1至147_5的高度。
图9A和9B所示的半导体器件的寄生电容可以大于图7所示的半导体器件的寄生电容(图7的C1、C2)。然而，图9A和9B所示的半导体器件的寄生电容仍可以小于与常规方法相关的寄生电容(图7的C11、C12)。源极/漏极161a和162a可以是提升源极/漏极。
图10A是根据本发明构思的一些实施方式的半导体器件的透视图，图10B是示出图10A所示的半导体器件的多沟道有源图案和场绝缘层的局部透视图。参考图10A和10B，多个多沟道有源图案F1至F3、F11至F13、F21至F23和F31至F33如图所示布置在X1和Y1方向。即，多沟道有源图案F1至F3、F11至F13、F21至F23和F31至F33布置为使得其长边彼此面对。具体地，第一多沟道有源图案F1和多沟道有源图案F11、F21和F31布置为在横向方向彼此并排。第二多沟道有源图案F2和多沟道有源图案F12、F22和F32布置为在横向方向彼此并排。第三多沟道有源图案F3和多沟道有源图案F13、F23和F33布置为在横向方向彼此并排。
场绝缘层110可以包括具有不同高度的第一区111和第二区112。第一区111形成为接触多沟道有源图案F1至F3、F11至F13、F21至F23和F31至F33的短边，第二区112形成为接触多沟道有源图案F1至F3、F11至F13、F21至F23和F31至F33的长边。
场绝缘层110的第一区111可以成形为鱼骨形天线。具体地，鱼骨形天线包括相应于穿过整个鱼骨形天线的主骨架的传输线和相应于从主骨架分支到两侧的骨架的多个偶极天线。换句话说，鱼骨形天线构造为使得多个偶极天线沿传输线的纵向且相对于在鱼骨形天线的纵向延伸的传输线以规则间隔布置。
因此，场绝缘层110可以包括在第一方向X1延伸的第一部分111a(中心轴区域)和分支到第一部分111a的两侧的多个第二部分111b(伸出区域)。第一部分111a可以包括在突出部分111的相反两侧的相对凹口，该相对凹口配置为允许在任一侧上的鳍凹入到凹口内。
多个第二部分111b(伸出区域)可以形成为围绕多个多沟道有源图案F1至F3、F11至F13、F21至F23和F31至F33的端部。
多个正常栅极147_1至147_5可以形成在相应的多沟道有源图案F1至F3、F11至F13、F21至F23和F31至F33上以交叉相应的多沟道有源图案F1至F3、F11至F13、F21至F23和F31至F33。例如，第一至第三正常栅极147_1、147_2和147_3可以形成在多沟道有源图案F1、F11、F21和F31上，第四正常栅极147_4可以形成在多沟道有源图案F2、F12、F22和F32上，第五正常栅极147_5可以形成在多沟道有源图案F3、F13、F23和F33上。
多个虚设栅极247_1和247_2可以形成在相应的场绝缘层110(即，第一区111)上。
图11是根据本发明构思的一些实施方式的半导体器件的截面图。参考图11，可以使用绝缘体上硅(SOI)基板。即，单晶硅形成在埋入氧化物层102上，多个多沟道有源图案F1至F3可以利用单晶硅形成。埋入氧化物层102和场绝缘层110可以设置为彼此接触。使用SOI基板还可以减少半导体器件的操作中的延迟时间。源极/漏极161a和162a可以是提升源极/漏极。
图12是根据本发明构思的一些实施方式的半导体器件的截面图。参考图12，正常栅极147_1和虚设栅极247_1可以利用前栅极工艺形成，而不利用后栅极工艺。在示出的实施方式中，正常栅极147_1和虚设栅极247_1由Si或SiGe制成，而不是金属，但本发明构思的方面不限于此。源极/漏极161a和162a可以是提升源极/漏极。
图13是根据本发明构思的一些实施方式的半导体器件的截面图。参考图13，多个接触191和192可以具有相同的高度。将理解，术语“多个接触191和192具有相同的高度”定义为包括工艺误差。
多个源极/漏极161和162可以是提升源极/漏极。设置在多个正常栅极147_1至147_5之间的源极/漏极161的高度和设置在正常栅极147_1至147_5与虚设栅极247_1和247_2之间的源极/漏极162的高度彼此相等。因此，形成在源极/漏极161上的接触191和形成在源极/漏极162上的接触192可以具有基本上相同的高度。
图14A是根据本发明构思的一些实施方式的半导体器件的框图，图14B是根据本发明构思的一些实施方式的半导体器件的框图。参考图14A，多栅极晶体管411可以设置在逻辑区410中，多栅极晶体管421可以设置在SRAM区420中。
参考图14B，不同的多栅极晶体管412和422可以设置在逻辑区410中。不同的多栅极晶体管也可以设置在SRAM区中。多栅极晶体管411可以是根据本发明构思的一些实施方式的图1-13所示的任何半导体器件，多栅极晶体管412也可以是根据本发明构思的实施方式的图1-13所示的任何半导体器件。例如，多栅极晶体管411可以是图5所示的半导体器件，多栅极晶体管412可以是图9A和9B所示的半导体器件，多栅极晶体管411可以是图8A至8D所示的每个半导体器件，多栅极晶体管412可以是图12所示的半导体器件。
在图14A中，逻辑区410和SRAM区420是示例，但本发明构思的方面不限于此。例如，本发明构思也可以被应用到逻辑区410和用于另一类型的存储器(例如，DRAM、MRAM、RRAM或PRAM)的区域。
图15A是根据本发明构思的一些实施方式的半导体器件的透视图。参考图15A，多个虚设栅极247_1a、247_1b、247_2a和247_2b可以设置在每个多沟道有源图案F1至F3之间。在示出的实施方式中，每两个虚设栅极247_1a和247_1b以及247_2a和247_2b作为示例，但本发明构思的方面不限于此。
每个虚设栅极247_1a、247_1b、247_2a和247_2b可以形成在彼此分离的每个场绝缘层111上，但本发明构思的方面不限于此。例如，虚设栅极247_1a和247_1b可以形成在场绝缘层111上，虚设栅极247_2a和247_2b可以形成在另一场绝缘层111上。
图15B是根据本发明构思的一些实施方式的半导体器件的截面图。参考图15B，半导体器件可以包括第一区I和第二区II。根据本发明构思的实施方式的图1-13所示的任意半导体器件可以形成在第一区I上。在示出的本发明构思的实施方式中，在图15B中以半导体器件为例说明。
在第二区II上，多个虚设栅极2247_1和3247_1可以设置在第一多沟道有源图案F1与第二多沟道有源图案F2之间。在示出的实施方式中，以两个虚设栅极2247_1和3247_1为例，但本发明构思的方面不限于此。虚设栅极2247_1和3247_1形成在场绝缘层3111上。间隔物2151和3151可以分别形成在虚设栅极2247_1和3247_1的侧壁上。具体地，部分的虚设栅极2247_1或部分的间隔物2151可以交叠场绝缘层3111的一侧。此外，部分的虚设栅极3247_1或部分的间隔物3151可以交叠场绝缘层3111的另一侧。源极/漏极3161和3162可以设置在虚设栅极2247_1和3247_1与正常栅极147_1之间。源极/漏极3161和3162可以是提升源极/漏极。
这里，第一区I和第二区II不限于特定区域。第二区II可以是相对宽的空间，第一区I可以是小于第二区II的空间。
在下文，参考图16至24描述图1-5示出的半导体器件的形成方法。图17和18是沿图16的线A-A和B-B所取的截面图，图20和21是沿图19的线A-A和B-B所取的截面图，图23和24是沿图22的线A-A和B-B所取的截面图。
参考图16至18，多沟道有源图案F1至F3形成在基板101上。多个多沟道有源图案F1至F3可以在第二方向Y1延伸。多沟道有源图案F1至F3可以是基板101的一部分并且可以包括从基板101生长的外延层。多沟道有源图案F1至F3可以是长方体的形状。多沟道有源图案F1至F3可以包括沿第二方向Y1形成的长边和沿第一方向X1形成的短边。这里，多沟道有源图案F1至F3可以是鳍形或纳米线形。在示出的实施方式中，以鳍形多沟道有源图案F1至F3作为示例。
参考图19至21，绝缘层115形成在基板101上。绝缘层115是将在蚀刻工艺中变为场绝缘层110的潜在层(potential layer)。绝缘层115可以形成为围绕多个多沟道有源图案F1至F3。如所示，绝缘层115可以填充在纵向并排布置的第一至第三多沟道有源图案F1至F3之间的空间，并可以形成为接触第一至第三多沟道有源图案F1至F3的侧壁。具体地，绝缘层115的顶表面可以平行于或高于多沟道有源图案F1至F3的顶表面。
参考图22至24，掩模119形成在多个多沟道有源图案F1至F3和绝缘层115上，绝缘层115利用掩模119被图案化，由此完成场绝缘层110。完成的场绝缘层110包括具有不同高度的第一区111和第二区112，第一区111接触多沟道有源图案F1至F3的短边，第二区112接触多沟道有源图案F1至F3的长边。
第一区111的顶表面可以平行于或高于多沟道有源图案F1至F3的顶表面。此外，第一区111可以形成为围绕多沟道有源图案F1至F3的端部。
参考图2至5，多个正常栅极147_1至147_5以及多个虚设栅极247_1和247_2形成在基板101上。然后，源极/漏极161a和162a形成在正常栅极147_1至147_5的相反两侧。正常栅极147_1至147_5形成为交叉多沟道有源图案F1至F3，虚设栅极247_1和247_2形成在场绝缘层110的第一区111上。第一区111的顶表面可以高于第一正常栅极147_1至147_5的底表面。第一区111的顶表面可以高于源极/漏极161a和162a的顶表面。
图25A和25B示出形成根据图8C所示的实施方式的半导体器件的方法。参考图25A，绝缘层115形成在基板101上。绝缘层115的顶表面位于与多个多沟道有源图案F1和F2的顶表面基本上相同的水平处。
参考图25B，掩模119a形成在多个多沟道有源图案F1和F2以及绝缘层115上，绝缘层115利用掩模119a被图案化，由此完成场绝缘层110。当绝缘层115利用掩模119a被图案化时，多沟道有源图案F1和F2的未被掩模119a覆盖的部分顶表面被蚀刻。然而，多沟道有源图案F1和F2的被掩模119a覆盖的部分顶表面不被蚀刻。结果，形成半导体部分166。再次参考图8C，形成正常栅极147_1、虚设栅极247_1和提升源极/漏极162。
图26是包括根据本发明构思的一些实施方式的半导体器件的电子系统的框图。参考图26，电子系统1100可以包括控制器1110、输入/输出设备(I/O)1120、存储器件1130、接口1140和总线1150。控制器1110、I/O 1120、存储器件1130和/或接口1140可以通过总线1150彼此连接。总线1150相应于数据通过其移动的路径。
控制器1110可以包括微处理器、数字信号处理器、微控制器、和具有类似于这些元件的功能的逻辑元件中的至少一个。I/O 1120可以包括键区、键盘、显示装置等等。存储器件1130可以储存数据和/或代码。接口1140可以执行传输数据到通信网络或从通信网络接收数据的功能。接口1140可以是有线的或无线的。例如，接口1140可以包括天线或有线/无线收发机等等。电子系统1100可以还包括高速DRAM和/或SRAM作为操作存储器，用于改善控制器1110的操作。根据本发明构思的实施方式的鳍型FET可以合并到图26的存储器件1130或提供为I/O 1120或其他部分的一部分。
电子系统1100可以是个人数字助理(PDA)、便携式计算机、网络平板、无线电话、移动式电话、数字音乐播放器、存储卡或能够在无线环境中传输和/或接收信息的任何类型的电子设备。
图27A和27B示出示范系统，其中可以应用根据本发明构思的一些实施方式的半导体器件。图27A示出其中根据本发明构思的实施方式被应用到平板的半导体器件的示例，图27B示出其中根据本发明构思的实施方式的半导体器件被应用到笔记本计算机的示例。根据本发明构思的一些实施方式的半导体器件的至少一个可以包括在平板PC、笔记本计算机等等之中。
虽然已经参考其示范实施方式具体示出并描述了本发明构思，但是本领域普通技术人员将理解，可以在其中进行形式和细节的变化而不背离权利要求所定义的本发明构思的精神和范围。因此，期望本实施方式在所有方面都被认为是说明性的和非限制性的，参考权利要求而不是前述描述来指示本发明构思的范围。
本申请要求于2012年11月30在韩国知识产权局提交的韩国专利申请No.10-2012-0138132号的优先权和所有由此产生的权益，其内容通过引用整体合并在此。

Claims (14)

1.一种半导体器件，包括：
场绝缘层，其包括具有在第一和第二正交方向上延伸的平面主表面的第一区域以及垂直地设置在所述主表面上的第二区域，所述第二区域的顶表面离所述主表面具有特定距离；
第一多沟道有源鳍和第二多沟道有源鳍，其在所述场绝缘层上延伸，所述第一多沟道有源鳍和所述第二多沟道有源鳍由所述场绝缘层的相对于所述第一多沟道有源鳍和所述第二多沟道有源鳍正交地延伸的所述第二区域分离；
设置在所述第一多沟道有源鳍上的第一栅极以及设置在所述第二多沟道有源鳍上的第二栅极；以及
设置在所述场绝缘层的所述第二区域与所述第一栅极之间的第一外延源/漏区以及设置在所述场绝缘层的所述第二区域与所述第二栅极之间的第二外延源/漏区。
2.如权利要求1所述的半导体器件，其中所述第一外延源/漏区和所述场绝缘层的所述第二区域由所述第一多沟道有源鳍的一部分分离，并且所述第二外延源/漏区和所述场绝缘层的所述第二区域由所述第二多沟道有源鳍的一部分分离。
3.如权利要求1所述的半导体器件，其中所述特定距离等于在相应栅极之下的所述第一多沟道有源鳍和所述第二多沟道有源鳍的最上表面的高度。
4.如权利要求1所述的半导体器件，还包括第一间隔物和第二间隔物，所述第一间隔物设置在所述第一外延源/漏区与所述场绝缘层的所述第二区域之间，并且所述第二间隔物设置在所述第二外延源/漏区与所述场绝缘层的所述第二区域之间。
5.如权利要求4所述的半导体器件，其中所述第一间隔物和所述第二间隔物分别直接接触所述第一外延源/漏区和所述第二外延源/漏区。
6.如权利要求4所述的半导体器件，其中所述第一外延源/漏区和所述场绝缘层的所述第二区域由所述第一多沟道有源鳍的一部分分离，并且所述第二外延源/漏区和所述场绝缘层的所述第二区域由所述第二多沟道有源鳍的一部分分离，以及其中所述第一间隔物设置在所述第一多沟道有源鳍的所述部分上，并且所述第二间隔物设置在所述第二多沟道有源鳍的所述部分上。
7.一种半导体器件，包括：
场绝缘层，其包括具有在第一和第二正交方向上延伸的平面主表面的第一区域；
设置在所述场绝缘层上的虚设绝缘图案；
第一多沟道有源鳍和第二多沟道有源鳍，其在所述场绝缘层上延伸，所述第一多沟道有源鳍和所述第二多沟道有源鳍由相对于所述第一多沟道有源鳍和所述第二多沟道有源鳍正交地延伸的所述虚设绝缘图案分离；
设置在所述第一多沟道有源鳍上的第一栅极和设置在所述第二多沟道有源鳍上的第二栅极；以及
设置在所述虚设绝缘图案与所述第一栅极之间的第一外延源/漏区以及设置在所述虚设绝缘图案与所述第二栅极之间的第二外延源/漏区。
8.如权利要求7所述的半导体器件，其中所述虚设绝缘图案包括虚设栅极。
9.如权利要求7所述的半导体器件，其中所述场绝缘层还包括在所述虚设栅极与所述第一区域之间的第二区域，并且所述第二区域离所述主表面具有特定距离。
10.如权利要求8所述的半导体器件，其中所述第一外延源/漏区和所述场绝缘层的所述第二区域由所述第一多沟道有源鳍的一部分分离，并且所述第二外延源/漏区和所述场绝缘层的所述第二区域由所述第二多沟道有源鳍的一部分分离。
11.如权利要求9所述的半导体器件，其中所述特定距离等于在相应栅极之下的所述第一多沟道有源鳍和所述第二多沟道有源鳍的最上表面的高度。
12.如权利要求7所述的半导体器件，还包括设置在所述第一外延源/漏区与所述虚设绝缘图案之间的第一间隔物以及设置在所述第二外延源/漏区与所述虚设绝缘图案之间的第二间隔物。
13.如权利要求12所述的半导体器件，其中所述第一间隔物和所述第二间隔物分别直接接触所述第一外延源/漏区和所述第二外延源/漏区。
14.如权利要求12所述的半导体器件，其中所述第一外延源/漏区和所述场绝缘层的所述第二区域由所述第一多沟道有源鳍的一部分分离，并且所述第二外延源/漏区和所述场绝缘层的所述第二区域由所述第二多沟道有源鳍的一部分分离，以及其中所述第一间隔物设置在所述第一多沟道有源鳍的所述部分上，并且所述第二间隔物设置在所述第二多沟道有源鳍的所述部分上。
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US20140353769A1 (en) 2014-12-04
TWI603473B (zh) 2017-10-21
CN108428734B (zh) 2022-01-25
US9627483B2 (en) 2017-04-18
US11955517B2 (en) 2024-04-09
US8836046B2 (en) 2014-09-16
CN103855219B (zh) 2018-04-17
US20140346602A1 (en) 2014-11-27
US10319814B2 (en) 2019-06-11
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US9419077B2 (en) 2016-08-16
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US20170194432A1 (en) 2017-07-06
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