TWI603473B - 在主動鰭之間包括突出絕緣部分的半導體裝置 - Google Patents

在主動鰭之間包括突出絕緣部分的半導體裝置 Download PDF

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TWI603473B
TWI603473B TW102143625A TW102143625A TWI603473B TW I603473 B TWI603473 B TW I603473B TW 102143625 A TW102143625 A TW 102143625A TW 102143625 A TW102143625 A TW 102143625A TW I603473 B TWI603473 B TW I603473B
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protruding portion
semiconductor device
channel active
conductive layer
insulating layer
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TW102143625A
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TW201421695A (zh
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前田茂伸
姜熙秀
沈相必
洪秀憲
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三星電子股份有限公司
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Description

在主動鰭之間包括突出絕緣部分的半導體裝置 【相關申請案之交叉參考】
本申請案主張於2012年11月30日在韓國智慧財產局申請之韓國專利申請案第10-2012-0138132號的優先權，且依據35 U.S.C.119由所述優先權賦予所有的權利，所述申請案之全部內容以引用之方式併入本文中。
本發明概念是有關於半導體之領域，且特別是有關於包括多通道主動鰭之半導體裝置。
已提供多閘極電晶體結構，其包括基板上之鰭狀或奈米線狀多通道主動圖案(或矽本體)及多通道主動圖案之表面上的閘極。
多閘極電晶體可利用三維通道，因此可比其他做法更容易達成微縮。另外，亦可改良控制電流之能力，而不需要增加多 閘極電晶體中之閘極的長度。此外，可更有效地處理通道區之電位受汲極電壓影響之短通道效應。
根據本發明概念之實施例可提供在主動鰭之間包括突出絕緣部分的半導體裝置。依據此等實施例，半導體裝置可包括：場絕緣層，所述場絕緣層包括在第一及第二正交方向上延伸的平坦主表面及相對於所述第一及第二正交方向自所述主表面突出一特定距離之突出部分。第一及第二多通道主動鰭可在所述場絕緣層上延伸，且可藉由所述突出部分而彼此分離。導電層可自所述突出部分之最上表面延伸，以橫越所述第一及第二多通道主動鰭之間的所述突出部分。
1‧‧‧半導體裝置
101‧‧‧基板
102‧‧‧埋入式氧化物層
109‧‧‧主表面
110‧‧‧場絕緣層
111‧‧‧第一區、突出部分
111a‧‧‧第一部分
111b‧‧‧第二部分
112‧‧‧第二區
115‧‧‧絕緣層
119、119a‧‧‧罩幕
125‧‧‧凹陷
145、245‧‧‧閘極絕緣層
147_1‧‧‧第一正常閘極
147_2‧‧‧第二正常閘極
147_3‧‧‧第三正常閘極
147_4‧‧‧第四正常閘極
147_5‧‧‧第五正常閘極
151‧‧‧間隙壁
161、161a‧‧‧源極/汲極
162、162a‧‧‧源極/汲極
166‧‧‧半導體部分
167‧‧‧標記
191、192‧‧‧接觸窗
247_1、247_2‧‧‧虛設閘極
247_1a、247_1b、247_2a、247_2b‧‧‧虛設閘極
410‧‧‧邏輯區域
411、412、421、422‧‧‧多閘極電晶體
420‧‧‧SRAM區域
1100‧‧‧電子系統
1110‧‧‧控制器
1120‧‧‧輸入/輸出裝置(I/O)
1130‧‧‧記憶體裝置
1140‧‧‧介面
1150‧‧‧匯流排
1247_1‧‧‧虛設閘極
2151‧‧‧間隙壁
2247_1‧‧‧虛設閘極
3111‧‧‧場絕緣層
3151‧‧‧間隙壁
3162‧‧‧源極/汲極
3247_1‧‧‧虛設閘極
C‧‧‧區
C1、C2、C3、C4、C11、C12‧‧‧寄生電容
F1、F2、F3、F11、F12、F13、F21、F22、F23、F31、F32、F33‧‧‧多通道主動圖案
H0‧‧‧高度
H1、H2、H3、H4、H5‧‧‧特定距離
MG1‧‧‧第一金屬層
MG2‧‧‧第二金屬層
I‧‧‧第一區
II‧‧‧第二區
A、B‧‧‧線
X1、Y1、Z1‧‧‧方向
本發明概念之以上及其他特徵及優點將藉由參考所附圖式詳細描述其較佳實施例而變得更顯而易見，其中：
圖1及圖2為根據本發明概念之一些實施例之半導體裝置的佈局視圖及透視圖。
圖3為說明根據圖1及圖2中所說明的本發明概念之一些實施例之半導體裝置中的多通道主動圖案及場絕緣層之部分透視圖。
圖4為沿著圖1及圖2之線A-A截取之截面圖。
圖5為沿著圖1及圖2之線B-B截取之截面圖。
圖6為說明圖1及圖2之區C的透視圖。
圖7為與習知排列相比較之根據本發明概念之一些實施例之半導體裝置的截面圖。
圖8A為根據本發明概念之一些實施例之半導體裝置的截面圖。
圖8B為根據本發明概念之一些實施例之半導體裝置的截面圖。
圖8C為根據本發明概念之一些實施例之半導體裝置的截面圖。
圖8D為根據本發明概念之一些實施例之半導體裝置的截面圖。
圖9A為根據本發明概念之一些實施例之半導體裝置的透視圖，而圖9B為沿著圖9A之線B-B截取的截面圖。
圖10A為根據本發明概念之一些實施例之半導體裝置的透視圖。
圖10B為說明圖10A中所示之半導體裝置之多通道主動圖案及場絕緣層的部分透視圖。
圖11為根據本發明概念之一些實施例之半導體裝置的截面圖。
圖12為根據本發明概念之一些實施例之半導體裝置的截面圖。
圖13為根據本發明概念之一些實施例之半導體裝置的截面圖。
圖14A為根據本發明概念之一些實施例之半導體裝置的方塊圖。
圖14B為根據本發明概念之一些實施例之半導體裝置的方塊圖。
圖15A為根據本發明概念之一些實施例之半導體裝置的透視圖。
圖15B為根據本發明概念之一些實施例之半導體裝置的截面圖。
圖16至圖24說明形成根據圖1至圖6之半導體裝置之方法。
圖25A及圖25B說明經由根據圖8A之形成半導體裝置之方法而提供的中間結構。
圖26為包括根據本發明概念之一些實施例之半導體裝置的電子系統之方塊圖。
圖27A及圖27B說明可使用根據本發明概念之一些實施例之半導體裝置的例示性半導體系統。
將在下文中參考隨附圖式充分描述本發明概念，在隨附圖式中繪示本發明概念之例示性實施例。本發明概念之優點及特徵以及達成所述優點及特徵之方法將自以下例示性實施例顯而易見，將參考隨附圖式更詳細地描述以下例示性實施例。然而，應注意本發明概念不限於以下例示性實施例，且可以各種形式實施。因此，僅提供例示性實施例以揭示本發明概念，且使得熟習此項技術者知曉本發明概念之類別。在圖式中，本發明概念之實施例不限於本文中所提供的特定示例，且出於清楚起見被誇大了。
本文所使用之術語僅出於描述特定實施例之目的且並不 意欲限制本發明。如本文中所使用，單數術語「一」及「所述」意欲亦包括複數形式，除非上下文另外清楚地指示。如本文中所使用，術語「及/或」包括相關聯之所列項目中之一或多者的任何及所有組合。應理解，當元件被稱為「連接」或「耦接」至另一元件時，所述元件可直接連接或耦接至另一元件或可存在介入元件。
類似地，應理解，當諸如層、區或基板之元件被稱作「在」另一元件「上」時，所述元件可直接在另一元件上或可存在介入元件。相比之下，術語「直接」意謂不存在介入元件。應進一步理解，術語「包括」在本文中使用時指定所陳述之特徵、整體、步驟、操作、元件及/或組件之存在，但不排除一或多個其他特徵、整體、步驟、操作、元件、組件及/或其群組之存在或添加。
亦應理解，儘管本文中可使用術語第一、第二、第三等等來描述各種元件，但此等元件不應由此等術語來限制。此等術語僅用於將一元件與另一元件區分開。因此，一些實施例中之第一元件可在其他實施例中被稱作第二元件，而不脫離本發明之教示。本文中所解釋及說明之本發明概念之態樣的例示性實施例包括其互補對應物。在整篇說明書中，相同參考標號或相同參考標示表示相同元件。
圖1及圖2分別為根據本發明概念之一些實施例之半導體裝置的佈局視圖及透視圖，圖3為說明圖1及圖2中所示的半導體裝置中之多通道主動圖案及場絕緣層之部分透視圖。具體言之，圖3說明圖2中所示之除了正常閘極(在本文中有時被稱作主動閘極)及虛設閘極以外的半導體裝置的配置。圖4為沿著圖1 及圖2之線A-A截取之截面圖，圖5為沿著圖1及圖2之線B-B截取之截面圖，圖6為說明圖1及圖2之區C的透視圖，而圖7說明與習知排列相比較根據圖1至圖6之半導體裝置。
首先參看圖1至圖6，半導體裝置1可包括多個多通道主動圖案F1至F3(在本文中有時被稱作「鰭」)、多個正常閘極147_1至147_5、場絕緣層110、多個虛設閘極247_1及247_2，及多個源極/汲極161a及162a。
多個多通道主動圖案F1至F3可在第二方向Y1上延伸。多通道主動圖案F1至F3中的每一者可為基板101之部分，且可包括自基板101生長之磊晶層。在所說明實施例中，例示了在縱向方向上彼此端對端地排列之三個多通道主動圖案F1至F3，但本發明概念之態樣不限於此。
在所說明實施例中，例示了具有矩形平行六面體之形狀的多通道主動圖案F1至F3，但本發明概念之態樣不限於此。亦即，多通道主動圖案F1至F3可被切成斜面。具體言之，多通道主動圖案F1至F3之角可經修圓。因為多通道主動圖案F1至F3在沿著第二方向Y1之縱向方向上延伸，所以多通道主動圖案F1至F3可包括沿著第二方向Y1之長邊及沿著第一方向X1形成之短邊。即使多通道主動圖案F1至F3之角經修圓，長邊及短邊仍可由熟習此項技術者彼此區別。多通道主動圖案F1至F3可為鰭狀或奈米線狀的。在所說明實施例中，例示了鰭狀多通道主動圖案F1至F3。
多通道主動圖案F1至F3經定義成包括用於多閘極電晶體中之主動圖案。亦即，當多通道主動圖案F1至F3為鰭狀時， 通道可沿著鰭之三個表面形成(在操作期間)，或通道可形成於鰭之兩個的對置表面上。當多通道主動圖案F1至F3為奈米線狀時，通道可圍繞奈米線而形成。場絕緣層110可形成於基板101上，且可環繞多個多通道主動圖案F1至F3之部分。場絕緣層110可形成為包括在與彼此正交之兩個方向(例如，X1及Y1)上延伸的主表面109。
詳細來說，場絕緣層110可包括具有不同高度之第一區(突出部分)111及第二區112。第二區112之高度可為H0，而第一區111之高度可使得第一區自主表面109突出達一特定距離H1。詳細來說，例如，第一區111可形成為使多通道主動圖案F1至F3之短邊分離，而第二區112可形成為接觸多通道主動圖案F1至F3之長邊。第一區111可形成於虛設閘極247_1及247_2之下，而第二區112可形成於正常閘極147_1至147_5之下。換言之，場絕緣層110之部分(亦即，第二區112)可置於對置的多通道主動圖案之間(例如，在F1與F2之間或在F2與F3之間)。第一區111可形成為在第一方向X1上延伸，而第二區112可在第二方向Y1上及在所述第一方向X1上延伸。
另外，如圖3中所示，突出部分(第一區)111可開凹口，以環繞凹入於其中之多通道主動圖案F1至F3之端部。亦即，第一區111可包括第一部分111a及第二部分111b。第一部分111a及第二部分111b可具有不同寬度。詳細來說，第二部分111b之寬度可大於第一部分111a之寬度。因此，第二部分111b可環繞多通道主動圖案F1至F3之端部中的每一者。以此方式，有可能防止場絕緣層110及待形成於其上之虛設閘極247_1及247_2未對 準。如圖3中進一步所示，突出部分(第一區)111在X1及Y1方向兩者上相對於主表面109突出特定距離H1。場絕緣層110可為氧化物層、氮化物層、氮氧化物層或其組合。
多個正常閘極147_1至147_5可形成於對應多通道主動圖案F1至F3上以越過對應的多通道主動圖案F1至F3。舉例而言，第一至第三正常閘極147_1、147_2及147_3可形成於第一多通道主動圖案F1上，第四正常閘極147_4可形成於第二多通道主動圖案F2上，而第五正常閘極147_5可形成於第三多通道主動圖案F3上。正常閘極147_1至147_5可在第一方向X1上延伸。
多個虛設閘極247_1及247_2可形成於對應場絕緣層110(亦即，場絕緣層110之第一區111)上以在X1方向上橫越突出部分(第一區)111。舉例而言，第一虛設閘極247_1可形成於圖2之左側所示之第一區111上，而第二虛設閘極247_2可形成於圖2之右側所示之第一區111上。詳言之，虛設閘極247_1及247_2中之每一者可逐個形成於對應第一區111上。虛設閘極247_1及247_2中之兩者或兩者以上未經形成，但虛設閘極247_1及247_2逐個形成，藉此減小佈局大小。應理解，虛設閘極可在(例如)X1方向上延伸以橫越另一鰭，以形成主動閘極之部分，諸如傳送電晶體(pass transistor)。
參看圖4及圖5，每一正常閘極(例如，147_1)可包括金屬層MG1及MG2。如圖4及圖5中所示，正常閘極147_1可經配置以使得兩個金屬層MG1及MG2堆疊。第一金屬層MG1可控制功函數，而第二金屬層MG2可填充由第一金屬層MG1形成之空間。舉例而言，第一金屬層MG1可包括TiN、TaN、TiC及TaC 中之至少一者。另外，第二金屬層MG2可包括W或A1。正常閘極147_1可由(例如)替換製程(replacement process)或後閘極製程(gate last process)形成，但本發明概念之態樣不限於此。
每一虛設閘極(例如，247_1)的配置可具有類似於正常閘極147_1之配置。如圖所示，虛設閘極247_1可經配置以使得兩個金屬層MG1及MG2堆疊。舉例而言，第一金屬層MG1可控制功函數，而第二金屬層MG2可填充由第一金屬層MG1形成之空間。
閘極絕緣層145可形成於多通道主動圖案F1與正常閘極147_1之間。如圖4中所示，閘極絕緣層145可形成於多通道主動圖案F1之頂表面及側表面上。另外，閘極絕緣層145可置於正常閘極147_1與場絕緣層(亦即，第二區112)之間。閘極絕緣層145可包括具有高於氧化矽層之介電常數之高k材料。舉例而言，閘極絕緣層145可包括HfO2、ZrO2或Ta2O5。
再次參看圖1至圖6，多個源極/汲極161a及162a可置於多個正常閘極147_1至147_5之間及正常閘極(例如，147_1及147_4)與虛設閘極(例如，247_1)之間。在所說明實施例中，源極/汲極161a及162a藉由對多通道主動圖案F1至F3摻雜雜質而形成，但本發明概念之態樣不限於此。
間隙壁151可包括氮化物層及氮氧化物層中之至少一者。間隙壁151可形成於多個多通道主動圖案F1至F3、多個正常閘極147_1至147_5及多個虛設閘極247_1及247_2之側壁上。
基板101可包括選自由Si、Ge、SiGe、GaP、GaAs、SiC、SiGeC、InAs及InP組成之群組的一種或一種以上之半導體材料。 或者，基板101可為絕緣體上矽(SOI)基板。
參看圖2及圖5，如上文所描述，場絕緣層110之第一區111及第二區112具有不同高度。第一區111之高度可為H0+H1，而第二區112之高度可為H0。
場絕緣層110之至少一部分的頂表面(亦即，第一區111之頂表面)高於正常閘極147_1至147_5之底表面。正常閘極147_1至147_5沿著場絕緣層110之頂表面(亦即，第二區112之頂表面)及多通道主動圖案F1至F3之頂表面及側表面形成。在正常閘極147_1至147_5中，術語「底表面」可意謂正常閘極147_1至147_5之底表面的最低部分。在圖2中，底表面可對應於接觸第二區112之頂表面的部分。
換言之，第一區111之頂表面可平行於(或齊平於)或高於源極/汲極161a及162a之頂表面。換言之，第一區111之頂表面可平行於或高於多通道主動圖案F1至F3之頂表面。在所說明實施例中，第一區111之頂表面比多通道主動圖案F1至F3之頂表面高H2。
換言之，虛設閘極247_1及247_2之高度不同於正常閘極147_1至147_5之高度。虛設閘極247_1及247_2之頂表面可平行於正常閘極147_1至147_5之頂表面。舉例而言，當虛設閘極247_1及247_2以及正常閘極147_1至147_5經由平坦化而形成時，其頂表面可彼此平行。因此，當第一區111之頂表面高於多通道主動圖案F1至F3之頂表面時，虛設閘極247_1及247_2形成於第一區111上，而正常閘極147_1至147_5形成於多通道主動圖案F1至F3上。因此，在截面圖中，虛設閘極247_1及247_2 之高度低於正常閘極147_1至147_5之高度。
出於彼此比較之目的，在根據本發明概念之一些環境下的半導體裝置繪示於圖7之左側，而習知半導體裝置繪示於圖7之右側。
在習知半導體裝置中，例如，場絕緣層110未劃分成第一區111及第二區112，且具有恆定高度。因此，在習知半導體裝置中，在第一多通道主動圖案F1與第二多通道主動圖案F2之間的場絕緣層1111具有高度H0。另外，在習知半導體裝置中，虛設閘極1247_1亦置於第一多通道主動圖案F1與第二多通道主動圖案F2之間的空間中。因此，虛設閘極1247_1與第一多通道主動圖案F1之間所形成的寄生電容C11及虛設閘極1247_1與第二多通道主動圖案F2之間所形成的寄生電容C12較大。寄生電容C11及C12可不利地影響習知半導體裝置之操作特性。舉例而言，寄生電容C11及C12可增加操作半導體裝置時的延遲時間。另外，因為虛設閘極1247與第一多通道主動圖案F1之間及虛設閘極1247_1與第二多通道主動圖案F2之間的接觸區域相當大，所以漏電流量可以是很大的。
相較之下，在根據本發明概念之一些實施例中的半導體裝置中，因為第一區111之頂表面平行於(或齊平於)或高於多通道主動圖案F1及F2之頂表面，所以虛設閘極247_1之最低部分未置於第一多通道主動圖案F1與第二多通道主動圖案F2之間的空間中。因此，寄生電容C1(形成於虛設閘極247_1與第一多通道主動圖案F1之間)及寄生電容C2(形成於虛設閘極247_1與第二多通道主動圖案F2之間)相對小。另外，因為虛設閘極247 與第一多通道主動圖案F1之間或虛設閘極247_1與第二多通道主動圖案F2之間的接觸區域極小，所以漏電流量可以是小的。
圖8A為根據本發明概念之一些實施例之半導體裝置的截面圖，而圖8B為根據本發明概念之實施例之半導體裝置的截面圖。參看圖8A，凹陷125可形成於多個正常閘極147_1至147_5之間，且形成於正常閘極147_1至147_5與虛設閘極247_1及247_2之間的多個多通道主動圖案F1至F3中。
源極/汲極161及162形成於凹陷125中。源極/汲極161及162中之每一者可包括磊晶層。亦即，源極/汲極161及162可由磊晶生長形成。另外，源極/汲極161及162可為相對於多通道主動圖案F1至F3突出之抬高的源極/汲極。
如圖8A中所示，源極/汲極161及162之部分可與間隙壁151及251重疊。亦即，源極/汲極161及162之部分可夾在間隙壁145及245之下部部分之下，如標記167。
在半導體裝置為PMOS電晶體之狀況下，源極/汲極161及162可包括壓縮應力材料。舉例而言，壓縮應力材料可為具有大於矽(Si)之晶格常數的材料，例如SiGe。壓縮應力材料可藉由將壓縮應力施加於多通道主動圖案(例如，F1)來改良通道區之載子(電洞)的遷移率。
然而，在半導體裝置為NMOS電晶體之狀況下，源極/汲極161及162可包括與基板101相同之材料或拉伸材料。舉例而言，當基板101包括Si時，源極/汲極161及162可包括Si或具有小於Si之晶格常數的材料(例如，SiC)。
突出部分(第一區)111之頂表面可平行於多通道主動圖 案F1之頂表面。
圖8B說明虛設閘極247_1及突出部分(第一區)111未對準。根據圖8B，當虛設閘極247_1及突出部分(第一區)111未對準時，虛設閘極247_1之部分可與多通道主動圖案F1之頂表面重疊。
圖8C為根據本發明概念之實施例之半導體裝置的截面圖。
參看圖8C，抬高的源極/汲極162之部分可與間隙壁245重疊。半導體部分166可定位於抬高的源極/汲極162之與間隙壁251重疊的區與間隙壁245之間。
半導體部分166為由於其被罩幕119a覆蓋而未經蝕刻之區(例如參看圖25B所描述)。半導體部分166當抬高的源極/汲極162在稍後步驟中形成時可有助於特定形狀的磊晶生長。
圖8D為根據本發明概念之實施例之半導體裝置的截面圖。參看圖8D，在根據本發明概念之實施例之半導體裝置中，源極/汲極161及162可為抬高的源極/汲極。源極/汲極161及162之頂表面可比多通道主動圖案F1至F3之頂表面高H5。另外，源極/汲極161及162及正常閘極147_1可藉由間隙壁151而彼此絕緣。
置於多個正常閘極147_1至147_5之間的源極/汲極161的高度及置於正常閘極147_1至147_5與虛設閘極247_1及247_2之間的源極/汲極162之高度彼此相等。應理解，術語「源極/汲極161及源極/汲極162之高度彼此相等」經定義包括製程誤差。
在根據本發明概念之實施例之半導體裝置中，如圖8D中 所示，場絕緣層110之至少部分的頂表面(例如，第一區111之頂表面)可平行於或高於抬高的源極/汲極161及162之頂表面。在所說明實施例中，場絕緣層110之至少部分的頂表面(例如，第一區111之頂表面)比抬高的源極/汲極161及162之頂表面高H3。因此，虛設閘極247_1及247_2與抬高的源極/汲極162之間所形成的寄生電容C3及C4可以是小的。另外，因為虛設閘極247_1及247_2中之每一者與抬高的源極/汲極162之間的接觸區域極小，所以漏電流量可以是小的。
虛設閘極247_1及247_2之高度及正常閘極147_1至147_5之高度彼此不同。虛設閘極247_1及247_2之高度可小於正常閘極147_1至147_5之高度。
圖9A為根據本發明概念之一些實施例之半導體裝置的透視圖，而圖9B為沿著圖9A之線B-B截取的截面圖。參看圖9A及圖9B，場絕緣層110可包括具有不同高度之第一區111及第二區112。第二區112之高度可為H0，而第一區111之高度可為H0+H4。第一區111之高度H0+H4可小於圖2中所示之第一區111的高度H0+H1。
虛設閘極247_1及247_2之高度及正常閘極147_1至147_5之高度可彼此不同。虛設閘極247_1及247_2之高度可大於正常閘極147_1至147_5之高度。
圖9A及圖9B中所示之半導體裝置的寄生電容可大於圖7中所示之半導體裝置的寄生電容(圖7之C1、C2)。然而，圖9A及圖9B中所示之半導體裝置的寄生電容仍可小於與習知做法相關聯之寄生電容(圖7之C11、C12)。源極/汲極161a及162a 可為抬高的源極/汲極。
圖10A為根據本發明概念之一些實施例之半導體裝置的透視圖，圖10B為說明圖10A中所示之半導體裝置之多通道主動圖案及場絕緣層的部分透視圖。參看圖10A及圖10B，多個多通道主動圖案F1至F3、F11至F13、F21至F23及F31至F33如圖所示排列於X1及Y1方向上。亦即，多通道主動圖案F1至F3、F11至F13、F21至F23及F31至F33經排列以使得其長邊面朝彼此。詳細來說，第一多通道主動圖案F1及多通道主動圖案F11、F21及F31在橫向方向上彼此並列地排列。第二多通道主動圖案F2及多通道主動圖案F12、F22及F32在橫向方向上彼此並列地排列。第三多通道主動圖案F3及多通道主動圖案F13、F23及F33在橫向方向上彼此並列地排列。
場絕緣層110可包括具有不同高度之第一區111及第二區112。第一區111經形成以接觸多通道主動圖案F1至F3、F11至F13、F21至F23及F31至F33之短邊，而第二區112經形成以接觸多通道主動圖案F1至F3、F11至F13、F21至F23及F31至F33之長邊。
場絕緣層110之第一區111可具有魚骨天線之形狀。詳細來說，魚骨天線包括對應於穿過整個魚骨天線之主骨的傳輸線及對應於自主骨向任一側分叉之骨的多個偶極。換言之，魚骨天線經構建以使得多個偶極沿著傳輸線之縱向方向且相對於在魚骨天線之縱向方向上延伸的傳輸線以規則間隔排列。
因此，場絕緣層110可包括在第一方向X1上延伸之第一部分111a(中心軸線區)及向第一部分111a之任一側分叉的多個 第二部分111b(突出區)。第一部分111a可包括在突出部分111之對置側上的對置的凹口，所述對置的凹口經配置以允許任一側上之鰭凹入於凹口內。
多個第二部分111b(突出區)可形成為環繞多個多通道主動圖案F1至F3、F11至F13、F21至F23及F31至F33之端部。
多個正常閘極147_1至147_5可形成於對應多通道主動圖案F1至F3、F11至F13、F21至F23及F31至F33上以越過對應多通道主動圖案F1至F3、F11至F13、F21至F23及F31至F33。舉例而言，第一至第三正常閘極147_1、147_2及147_3可形成於多通道主動圖案F1、F11、F21及F31上，第四正常閘極147_4可形成於多通道主動圖案F2、F12、F22及F32上，而第五正常閘極147_5可形成於多通道主動圖案F3、F13、F23及F33上。
多個虛設閘極247_1及247_2可形成於對應場絕緣層110(亦即，第一區111)上。
圖11為根據本發明概念之一些實施例之半導體裝置的截面圖。參看圖11，可使用絕緣體上矽(SOI)基板。亦即，單晶矽形成於埋入式氧化物層102上，且多個多通道主動圖案F1至F3可使用單晶矽來形成。埋入式氧化物層102及第一區111可經置而彼此接觸。使用SOI基板可進一步減小操作半導體裝置時的延遲時間。源極/汲極161a及162a可為抬高的源極/汲極。
圖12為根據本發明概念之一些實施例之半導體裝置的截面圖。參看圖12，正常閘極147_1及虛設閘極247_1可使用前閘極(gate-first)製程而不使用後閘極(gate-last)製程形成。在所說明實施例中，正常閘極147_1及虛設閘極247_1由Si或SiGe 製成，而不是金屬製成，但本發明概念之態樣不限於此。源極/汲極161a及162a可為抬高的源極/汲極。
圖13為根據本發明概念之一些實施例之半導體裝置的截面圖。參看圖13，多個接觸窗191及192可具有相同高度。應理解，術語「多個接觸窗191及192具有相同高度」經定義包括製程誤差。
多個源極/汲極161及162可為抬高的源極/汲極。置於多個正常閘極147_1至147_5之間的源極/汲極161的高度及置於正常閘極147_1至147_5與虛設閘極247_1及247_2之間的源極/汲極162之高度彼此相等。因此，形成於源極/汲極161上之接觸窗191及形成於源極/汲極162上之接觸窗192可具有實質上相同的高度。
圖14A為根據本發明概念之一些實施例之半導體裝置的方塊圖，而圖14B為根據本發明概念之一些實施例之半導體裝置的方塊圖。參看圖14A，多閘極電晶體411可置於邏輯區域410中，而多閘極電晶體421可置於SRAM區域420中。
參看圖14B，不同多閘極電晶體412及422可置於邏輯區域410中。不同多閘極電晶體亦可置於SRAM區域中。多閘極電晶體411可為根據本發明概念之一些實施例之圖1至圖13中所示的半導體裝置中之任一者，而多閘極電晶體412亦可為根據本發明概念之實施例之圖1至圖13中所示的半導體裝置中之任一者。舉例而言，多閘極電晶體411可為圖5中所示之半導體裝置，多閘極電晶體412可為圖9A及圖9B中所示之半導體裝置，多閘極電晶體411可為圖8A至圖8D中所示之半導體裝置中的任一 者，而多閘極電晶體412可為圖12中所示之半導體裝置。
在圖14A中，邏輯區域410及SRAM區域420為示例，但本發明概念之態樣不限於此。舉例而言，本發明概念亦可應用於邏輯區域410及另一類型之記憶體(例如，DRAM、MRAM、RRAM或PRAM)的區域。
圖15A為根據本發明概念之一些實施例之半導體裝置的透視圖。參看圖15A，多個虛設閘極247_1a、247_1b、247_2a及247_2b可置於多通道主動圖案F1至F3中之每一者之間。在所說明實施例中，每兩個虛設閘極247_1a及247_1b以及247_2a及247_2b為示例，但本發明概念之態樣不限於此。
虛設閘極247_1a、247_1b、247_2a及247_2b中之每一者可形成於彼此分離的突出部分(第一區)111中之每一者上，但本發明概念之態樣不限於此。舉例而言，虛設閘極247_1a及247_1b可形成於一個突出部分(第一區)111上，而虛設閘極247_2a及247_2b可形成於另一突出部分(第一區)111上。
圖15B為根據本發明概念之一些實施例之半導體裝置的截面圖。參看圖15B，半導體裝置可包括第一區I及第二區II。根據本發明概念之實施例之圖1至圖13中所示的半導體裝置中的任一者可形成於第一區I上。在本發明概念之所說明實施例中，在圖15B中例示了半導體裝置。
在第二區II上，多個虛設閘極2247_1及3247_1可置於第一多通道主動圖案F1與第二多通道主動圖案F2之間。在所說明實施例中，例示了兩個虛設閘極2247_1及3247_1，但本發明概念之態樣不限於此。虛設閘極2247_1及3247_1形成於場絕緣層 3111上。間隙壁2151及3151可分別形成於虛設閘極2247_1及3247_1之側壁上。詳細來說，虛設閘極2247_1之部分或間隙壁2151之部分可與場絕緣層3111之一側重疊。另外，虛設閘極3247_1之部分或間隙壁3151之部分可與場絕緣層3111之另一側重疊。源極/汲極3162可置於虛設閘極2247_1及3247_1與正常閘極147_1之間。源極/汲極3162可為抬高的源極/汲極。
此處，第一區I及第二區II不限於特定的區。第二區II可為相對寬的空間，且第一區I可為小於第二區II的空間。
下文中，參看圖16至圖24描述形成圖1至圖5中所說明之半導體裝置的方法。圖17及圖18為沿著圖16之線A-A及B-B截取之截面圖，圖20及圖21為沿著圖19之線A-A及B-B截取之截面圖，且圖23及圖24為沿著圖22之線A-A及B-B截取之截面圖。
參看圖16至圖18，於基板101上形成多通道主動圖案F1至F3。多個多通道主動圖案F1至F3可在第二方向Y1上延伸。多通道主動圖案F1至F3可為基板101之部分，且可包括自基板101生長之磊晶層。多通道主動圖案F1至F3可具有矩形平行六面體之形狀。多通道主動圖案F1至F3可包括沿著第二方向Y1形成之長邊及沿著第一方向X1形成之短邊。此處，多通道主動圖案F1至F3可為鰭狀或奈米線狀的。在所說明實施例中，例示了鰭狀多通道主動圖案F1至F3。
參看圖19至圖21，於基板101上形成絕緣層115。絕緣層115為在蝕刻製程期間將變為場絕緣層110之潛層(potential layer)。絕緣層115可形成為環繞多個多通道主動圖案F1至F3。 如圖所示，絕緣層115可填充在縱向方向上彼此並列地排列之第一至第三多通道主動圖案F1至F3之間的空間，且可形成為接觸第一至第三多通道主動圖案F1至F3之側壁。詳言之，絕緣層115之頂表面可平行於或高於多通道主動圖案F1至F3之頂表面。
參看圖22至圖24，於多個多通道主動圖案F1至F3及絕緣層115上形成罩幕119，且使用罩幕119圖案化絕緣層115，藉此完成場絕緣層110。完成之場絕緣層110包括具有不同高度之第一區111及第二區112，且第一區111接觸多通道主動圖案F1至F3之短邊，且第二區112接觸多通道主動圖案F1至F3之長邊。
第一區111之頂表面可平行於或高於多通道主動圖案F1至F3之頂表面。另外，第一區111可形成為環繞多通道主動圖案F1至F3之端部。
參看圖2至圖5，於基板101上形成多個正常閘極147_1至147_5及多個虛設閘極247_1及247_2。接下來，於正常閘極147_1至147_5之對置側處形成源極/汲極161a及162a。正常閘極147_1至147_5形成為越過多通道主動圖案F1至F3，且虛設閘極247_1及247_2形成於場絕緣層110之第一區111上。第一區111之頂表面可高於第一正常閘極147_1至147_5之底表面。第一區111之頂表面可高於源極/汲極161a及162a之頂表面。
圖25A及圖25B說明形成根據圖8C中所示之實施例之半導體裝置的方法。參看圖25A，於基板101上形成絕緣層115。絕緣層115之頂表面實質上齊平於多個多通道主動圖案F1及F2之頂表面。
參看圖25B，於多個多通道主動圖案F1及F2及絕緣層 115上形成罩幕119a，且使用罩幕119a圖案化絕緣層115，藉此完成場絕緣層110。當絕緣層115使用罩幕119a圖案化時，蝕刻多通道主動圖案F1及F2之頂表面的未被罩幕119a覆蓋的部分。然而，多通道主動圖案F1及F2之頂表面的未被罩幕119a覆蓋的部分並未被蝕刻。結果，形成半導體部分166。再次參看圖8C，形成正常閘極147_1、虛設閘極247_1及抬高的源極/汲極162。
圖26為包括根據本發明概念之一些實施例之半導體裝置的電子系統之方塊圖。參看圖26，電子系統1100可包括控制器1110、輸入/輸出裝置(I/O)1120、記憶體裝置1130、介面1140及匯流排1150。控制器1110、I/O 1120、記憶體裝置1130及/或介面1140可經由匯流排1150彼此連接。匯流排1150對應於資料移動所經之路徑。
控制器1110可包括微處理器、數位信號處理器、微控制器及能夠具有類似於此等元件之功能的功能之邏輯元件中之至少一者。I/O 1120可包括小鍵盤、鍵盤、顯示裝置等等。記憶體裝置1130可儲存資料及/或程式碼。介面1140可執行將資料傳輸至通信網路或自通信網路接收資料之功能。介面1140可為有線的或無線的。舉例而言，介面1140可包括天線或有線/無線收發器等等。電子系統1100可進一步包括高速DRAM及/或SRAM作為用於改良控制器1110之操作的操作記憶體。根據本發明概念之實施例之鰭狀場效電晶體可併入至記憶體裝置1130中或提供做為I/O 1120之部分或圖26之其他部分。
電子系統1100可為個人數位助理(PDA)、攜帶型電腦、聯網平板電腦(web tablet)、無線電話、行動電話、數位音樂播放 器、記憶卡或能夠在無線環境下傳輸及/或接收資訊的任何類型之電子裝置。
圖27A及圖27B說明可應用根據本發明概念之一些實施例之半導體裝置的例示性系統。圖27A說明根據本發明概念之實施例之半導體裝置應用於平板電腦的示例，且圖27B說明根據本發明概念之實施例之半導體裝置應用於筆記型電腦的示例。根據本發明概念之一些實施例之半導體裝置中的至少一者可包括於平板PC、筆記型電腦或其類似者中。
雖然本發明概念已參考其例示性實施例來特定地繪示及描述，但一般熟習此項技術者應理解可在其中進行形式及細節方面之各種變化而不脫離由所附申請專利範圍所定義之本發明概念之精神及範疇。因此，需要本實施例在所有方面被視為說明性的且非限制性的，參考所附申請專利範圍而非參考前述描述以指示本發明概念之範疇。
110‧‧‧場絕緣層
111‧‧‧第一區、突出部分
112‧‧‧第二區
147_1‧‧‧第一正常閘極
147_2‧‧‧第二正常閘極
147_3‧‧‧第三正常閘極
147_4‧‧‧第四正常閘極
147_5‧‧‧第五正常閘極
247_1、247_2‧‧‧虛設閘極
A-A、B-B‧‧‧線
C‧‧‧區
F1、F2、F3‧‧‧多通道主動圖案
H0‧‧‧高度
H1‧‧‧特定距離

Claims (39)

  1. 一種半導體裝置，包括：場絕緣層，其包括在第一及第二正交方向上延伸的平坦主表面及相對於所述第一及第二正交方向自所述平坦主表面突出一特定距離之突出部分；第一及第二多通道主動鰭，其在所述場絕緣層上延伸，藉由所述突出部分而彼此分離；以及導電層，其自所述突出部分之最上表面延伸，以橫越所述第一及第二多通道主動鰭之間的所述突出部分。
  2. 如申請專利範圍第1項所述的半導體裝置，其中所述特定距離大於在所述第一及第二多通道主動鰭上之各別閘極下方的所述第一及第二多通道主動鰭之最上表面的高度。
  3. 如申請專利範圍第2項所述的半導體裝置，更包括：第一源極/汲極，在所述第一多通道主動鰭中，所述第一源極/汲極直接鄰近於包括最上表面之所述突出部分，所述第一多通道主動鰭在所述突出部分之所述最上表面之下。
  4. 如申請專利範圍第1項所述的半導體裝置，其中所述特定距離等於在所述第一及第二多通道主動鰭上之各別閘極下方的所述第一及第二多通道主動鰭之最上表面的高度。
  5. 如申請專利範圍第4項所述的半導體裝置，更包括：第一源極/汲極，在所述第一多通道主動鰭中，所述第一源極/汲極直接鄰近於包括最上表面之所述突出部分，所述第一多通道主動鰭在所述突出部分之所述最上表面之上。
  6. 如申請專利範圍第1項所述的半導體裝置，更包括：側壁間隙壁，在所述導電層上；以及非平坦閘極絕緣層，在所述突出部分之所述最上表面與所述導電層之間。
  7. 如申請專利範圍第1項所述的半導體裝置，其中所述導電層被包括於虛設閘極中。
  8. 如申請專利範圍第1項所述的半導體裝置，其中所述導電層被包括於主動閘極中。
  9. 一種半導體裝置，包括：場絕緣層，其包括在第一及第二正交方向上延伸的平坦主表面及相對於所述第一及第二正交方向自所述平坦主表面突出一特定距離之突出部分；第一及第二多通道主動鰭，其在所述場絕緣層上延伸，藉由所述突出部分而彼此分離；導電層，其自所述突出部分之最上表面延伸，以橫越所述第一及第二多通道主動鰭之間的所述突出部分；非平坦絕緣層，其在所述導電層與所述突出部分之間；以及主動閘極，其橫越所述第一多通道主動鰭。
  10. 如申請專利範圍第9項所述的半導體裝置，其中所述導電層包括於虛設閘極中，所述虛設閘極位於所述導電層橫越所述突出部分之處。
  11. 如申請專利範圍第9項所述的半導體裝置，其中所述特定距離大於在所述主動閘極及所述導電層下方的所述第一及第二多通道主動鰭之最上表面的高度。
  12. 如申請專利範圍第11項所述的半導體裝置，更包括：第一源極/汲極，在所述第一多通道主動鰭中，所述第一源極/汲極直接鄰近於包括最上表面之所述突出部分，所述第一多通道主動鰭在所述突出部分之所述最上表面之下。
  13. 如申請專利範圍第9項所述的半導體裝置，其中所述特定距離等於在所述主動閘極及所述導電層下方的所述第一及第二多通道主動鰭之最上表面的高度。
  14. 如申請專利範圍第13項所述的半導體裝置，更包括：第一源極/汲極，在所述第一多通道主動鰭中，所述第一源極/汲極直接鄰近於包括最上表面之所述突出部分之，所述第一多通道主動鰭在所述突出部分之所述最上表面之上。
  15. 一種半導體裝置，包括：絕緣層，其包括主表面及自所述主表面突出之突出部分；第一及第二多通道主動鰭，其直接鄰近於彼此且藉由所述突出部分而彼此分離；鰭狀場效電晶體，在所述第一多通道主動鰭上；導電層，其自所述突出部分之最上表面延伸，以橫越所述第一及第二多通道主動鰭之間的所述突出部分；鰭狀場效電晶體側壁間隙壁，被包括於所述鰭狀場效電晶體中，所述鰭狀場效電晶體側壁間隙壁具有第一高度；以及導電層側壁間隙壁，在所述導電層上，所述導電層側壁間隙壁具有小於所述第一高度之第二高度。
  16. 如申請專利範圍第15項所述的半導體裝置，其中所述導電層被包括於虛設閘極結構中。
  17. 如申請專利範圍第15項所述的半導體裝置，其中所述導電層被包括於主動閘極結構中。
  18. 如申請專利範圍第15項所述的半導體裝置，其中所述鰭狀場效電晶體側壁間隙壁之基部(base)在所述導電層側壁間隙壁之基部(base)之下。
  19. 如申請專利範圍第15項所述的半導體裝置，更包括：磊晶源極/汲極區，在所述第一多通道主動鰭中；以及所述第一多通道主動鰭之部分，其在所述磊晶源極/汲極區外部，在所述磊晶源極/汲極區與在所述導電層下方之所述絕緣層的所述突出部分之間。
  20. 如申請專利範圍第19項所述的半導體裝置，其中所述磊晶源極/汲極區自對準所述導電層側壁間隙壁之最上部分。
  21. 如申請專利範圍第19項所述的半導體裝置，其中所述第一多通道主動鰭之所述部分至所述磊晶源極/汲極區之界面比所述導電層側壁間隙壁之最外部分更靠近於所述突出部分。
  22. 如申請專利範圍第19項所述的半導體裝置，更包括：單獨絕緣層，在所述導電層與所述突出部分之間，所述單獨絕緣層接觸所述第一多通道主動鰭區的所述部分。
  23. 一種半導體裝置，包括：絕緣層，其包括主表面及自所述主表面突出之突出部分；第一及第二多通道主動鰭，其直接鄰近於彼此且藉由所述突出部分而彼此分離；鰭狀場效電晶體，在所述第一多通道主動鰭上；導電層，其自所述突出部分之最上表面延伸，以橫越所述第 一及第二多通道主動鰭之間的所述突出部分；磊晶源極/汲極區，在所述第一多通道主動鰭中；以及導電層側壁間隙壁，在所述導電層上，所述導電層側壁間隙壁包括與所述磊晶源極/汲極區重疊的所述導電層側壁間隙壁之基部(base)。
  24. 如申請專利範圍第23項所述的半導體裝置，更包括：所述第一多通道主動鰭之部分，其在所述磊晶源極/汲極區外部，在所述磊晶源極/汲極區與在所述導電層下方之所述絕緣層的所述突出部分之間。
  25. 如申請專利範圍第24項所述的半導體裝置，其中所述第一多通道主動鰭之所述部分至所述磊晶源極/汲極區之界面比所述導電層側壁間隙壁之最外部分更靠近於所述突出部分。
  26. 如申請專利範圍第24項所述的半導體裝置，其中所述第一多通道主動鰭之所述部分至所述磊晶源極/汲極區之界面與所述導電層側壁間隙壁之最外部分對準。
  27. 如申請專利範圍第24項所述的半導體裝置，其中所述第一多通道主動鰭之所述部分接觸所述導電層與所述突出部分之間的單獨絕緣層。
  28. 如申請專利範圍第23項所述的半導體裝置，其中所述導電層被包括於虛設閘極結構中。
  29. 如申請專利範圍第23項所述的半導體裝置，其中所述導電層被包括於正常閘極結構中。
  30. 如申請專利範圍第23項所述的半導體裝置，其中所述突出部分之所述最上表面高於在所述鰭狀場效電晶體下方之所述第 一多通道主動鰭的最上表面。
  31. 如申請專利範圍第23項所述的半導體裝置，其中所述突出部分之所述最上表面與在所述鰭狀場效電晶體下方之所述第一多通道主動鰭的最上表面共平面。
  32. 一種半導體裝置，包括：場絕緣層，其包括平坦主表面及自所述平坦主表面突出一特定距離之突出部分；第一及第二多通道主動鰭，其在第一方向上在所述場絕緣層上延伸，藉由所述突出部分而彼此分離；以及導電層，其自所述突出部分之最上表面延伸，以橫越所述第一及第二多通道主動鰭之間的所述突出部分，其中所述突出部分在所述突出部分與所述第一及第二多通道主動鰭相交之對置位置處開凹口以形成第一凹口及第二凹口。
  33. 如申請專利範圍第32項所述的半導體裝置，其中所述第一及第二多通道主動鰭分別在所述對置位置處延伸至所述第一凹口及所述第二凹口中。
  34. 如申請專利範圍第32項所述的半導體裝置，其中所述突出部分之寬度在所述對置位置外部比在所述對置位置內部大。
  35. 如申請專利範圍第32項所述的半導體裝置，其中所述導電層包括虛設閘極結構。
  36. 如申請專利範圍第32項所述的半導體裝置，其中所述導電層包括主動閘極結構。
  37. 一種半導體裝置，包括：場絕緣層，其包括在第一及第二正交方向上延伸的平坦主表 面及相對於所述第一及第二正交方向自所述平坦主表面突出一特定距離之突出部分；第一及第二多通道主動鰭，其在所述場絕緣層上延伸，藉由所述突出部分而彼此分離；以及導電層，其自所述突出部分之最上表面延伸，以橫越所述第一及第二多通道主動鰭之間的所述突出部分，其中所述特定距離高於所述第一及第二多通道主動鰭中之鄰近源極/汲極區的最低邊界。
  38. 一種半導體裝置，包括：場絕緣層，其包括在第一及第二正交方向上延伸的平坦主表面及相對於所述第一及第二正交方向自所述平坦主表面突出一特定距離之突出部分；第一及第二多通道主動鰭，其在所述場絕緣層上延伸，藉由所述突出部分而彼此分離；導電層，其自所述突出部分之最上表面延伸，以橫越所述第一及第二多通道主動鰭之間的所述突出部分；以及閘極結構，在所述導電層上，其中所述閘極結構之高度小於鄰近主動閘極之高度。
  39. 一種半導體裝置，包括：場絕緣層，其包括在第一及第二正交方向上延伸的平坦主表面及相對於所述第一及第二正交方向自所述平坦主表面突出一特定距離之突出部分；第一及第二多通道主動鰭，其在所述場絕緣層上端對端地延伸，藉由位於所述主動鰭之各別端之間的所述突出部分而彼此分 離；以及導電閘極層，其自所述突出部分之上表面延伸，以橫越所述主動鰭之所述各別端之間的所述突出部分。
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