CN107615445B - 绝缘体上硅晶圆的制造方法 - Google Patents

绝缘体上硅晶圆的制造方法 Download PDF

Info

Publication number
CN107615445B
CN107615445B CN201680028359.7A CN201680028359A CN107615445B CN 107615445 B CN107615445 B CN 107615445B CN 201680028359 A CN201680028359 A CN 201680028359A CN 107615445 B CN107615445 B CN 107615445B
Authority
CN
China
Prior art keywords
wafer
silicon
heat treatment
soi
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201680028359.7A
Other languages
English (en)
Chinese (zh)
Other versions
CN107615445A (zh
Inventor
横川功
阿贺浩司
小林德弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Publication of CN107615445A publication Critical patent/CN107615445A/zh
Application granted granted Critical
Publication of CN107615445B publication Critical patent/CN107615445B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Element Separation (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
CN201680028359.7A 2015-06-15 2016-03-08 绝缘体上硅晶圆的制造方法 Active CN107615445B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2015120424A JP6380245B2 (ja) 2015-06-15 2015-06-15 Ｓｏｉウェーハの製造方法
JP2015-120424 2015-06-15
PCT/JP2016/001235 WO2016203677A1 (ja) 2015-06-15 2016-03-08 Ｓｏｉウェーハの製造方法

Publications (2)

Publication Number Publication Date
CN107615445A CN107615445A (zh) 2018-01-19
CN107615445B true CN107615445B (zh) 2020-10-30

Family

ID=57545735

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201680028359.7A Active CN107615445B (zh) 2015-06-15 2016-03-08 绝缘体上硅晶圆的制造方法

Country Status (8)

Country Link
US (1) US10204824B2 (enExample)
EP (1) EP3309820B1 (enExample)
JP (1) JP6380245B2 (enExample)
KR (1) KR102327330B1 (enExample)
CN (1) CN107615445B (enExample)
SG (1) SG11201709420PA (enExample)
TW (1) TWI685019B (enExample)
WO (1) WO2016203677A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6473970B2 (ja) * 2015-10-28 2019-02-27 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
CN109037031B (zh) * 2018-07-11 2021-11-19 华东师范大学 一种掺镍氧化铜薄膜晶体管及制备方法
CN110739285A (zh) * 2019-10-30 2020-01-31 北京工业大学 硅基金属中间层化合物半导体晶圆的结构及制备方法
KR20220156947A (ko) * 2020-04-02 2022-11-28 도쿄엘렉트론가부시키가이샤 기판 처리 방법 및 기판 처리 장치
KR102456461B1 (ko) 2020-11-26 2022-10-19 현대제철 주식회사 딥러닝을 이용한 철강 미세 조직 분석 방법 및 시스템
CN112582332A (zh) * 2020-12-08 2021-03-30 上海新昇半导体科技有限公司 一种绝缘体上硅结构及其方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1502135A (zh) * 2001-04-06 2004-06-02 ��Խ�뵼����ʽ���� Soi晶片及其制造方法
CN1868054A (zh) * 2003-10-14 2006-11-22 特拉希特技术公司 制备和组装基材的方法
CN101084577A (zh) * 2004-12-28 2007-12-05 特拉希特技术公司 修整通过组装两晶片构成的结构的方法
CN101689478A (zh) * 2007-06-21 2010-03-31 信越半导体股份有限公司 Soi芯片的制造方法
CN103299395A (zh) * 2010-12-20 2013-09-11 信越半导体股份有限公司 Soi晶片的制造方法
CN104025254A (zh) * 2012-01-06 2014-09-03 信越半导体株式会社 贴合soi晶片的制造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JPH11307472A (ja) 1998-04-23 1999-11-05 Shin Etsu Handotai Co Ltd 水素イオン剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP2000124092A (ja) * 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP4123861B2 (ja) * 2002-08-06 2008-07-23 株式会社Ｓｕｍｃｏ 半導体基板の製造方法
JP4603865B2 (ja) * 2004-12-01 2010-12-22 信越化学工業株式会社 酸化膜付きシリコン基板の製造方法及び酸化膜付きシリコン基板
JP2007317988A (ja) * 2006-05-29 2007-12-06 Shin Etsu Handotai Co Ltd 貼り合わせウエーハの製造方法
JP2008028070A (ja) 2006-07-20 2008-02-07 Sumco Corp 貼り合わせウェーハの製造方法
JP5135935B2 (ja) * 2007-07-27 2013-02-06 信越半導体株式会社 貼り合わせウエーハの製造方法
JP5531642B2 (ja) * 2010-01-22 2014-06-25 信越半導体株式会社 貼り合わせウェーハの製造方法
JP5704039B2 (ja) * 2011-10-06 2015-04-22 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
JP5673572B2 (ja) * 2012-01-24 2015-02-18 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1502135A (zh) * 2001-04-06 2004-06-02 ��Խ�뵼����ʽ���� Soi晶片及其制造方法
CN1868054A (zh) * 2003-10-14 2006-11-22 特拉希特技术公司 制备和组装基材的方法
CN101084577A (zh) * 2004-12-28 2007-12-05 特拉希特技术公司 修整通过组装两晶片构成的结构的方法
CN101689478A (zh) * 2007-06-21 2010-03-31 信越半导体股份有限公司 Soi芯片的制造方法
CN103299395A (zh) * 2010-12-20 2013-09-11 信越半导体股份有限公司 Soi晶片的制造方法
CN104025254A (zh) * 2012-01-06 2014-09-03 信越半导体株式会社 贴合soi晶片的制造方法

Also Published As

Publication number Publication date
EP3309820A1 (en) 2018-04-18
KR102327330B1 (ko) 2021-11-17
CN107615445A (zh) 2018-01-19
EP3309820A4 (en) 2019-01-23
SG11201709420PA (en) 2017-12-28
JP2017005201A (ja) 2017-01-05
US20180144975A1 (en) 2018-05-24
EP3309820B1 (en) 2020-01-29
TW201643938A (zh) 2016-12-16
KR20180016394A (ko) 2018-02-14
TWI685019B (zh) 2020-02-11
JP6380245B2 (ja) 2018-08-29
US10204824B2 (en) 2019-02-12
WO2016203677A1 (ja) 2016-12-22

Similar Documents

Publication Publication Date Title
CN107615445B (zh) 绝缘体上硅晶圆的制造方法
JP4509488B2 (ja) 貼り合わせ基板の製造方法
US20130089968A1 (en) Method for finishing silicon on insulator substrates
TWI357101B (en) Method for producing bonded wafer
JP6036732B2 (ja) 貼り合わせウェーハの製造方法
EP2256787B1 (en) Process for producing soi wafer
US9496130B2 (en) Reclaiming processing method for delaminated wafer
US20140235032A1 (en) Method for producing transparent soi wafer
WO2013102968A1 (ja) 貼り合わせｓｏｉウェーハの製造方法
KR20090081335A (ko) 접합 웨이퍼의 제조 방법
KR101066315B1 (ko) 접합 웨이퍼의 제조 방법
WO2005024925A1 (ja) Ｓｏｉウェーハの作製方法
JP4285244B2 (ja) Ｓｏｉウェーハの作製方法
KR102095383B1 (ko) 접합 웨이퍼의 제조방법
WO2006109614A1 (ja) Ｓｏｉウェーハの製造方法およびこの方法により製造されたｓｏｉウェーハ
WO2016059748A1 (ja) 貼り合わせウェーハの製造方法
TW202347607A (zh) 用於製作雙重絕緣體上半導體結構之方法
CN118613903A (zh) 用于制造双绝缘体上半导体结构的方法
JP7251419B2 (ja) 貼り合わせｓｏｉウェーハの製造方法
JP2008072049A (ja) 貼り合わせウェーハの製造方法
KR20160052551A (ko) 접합 웨이퍼의 제조방법
JP2006013179A (ja) Ｓｏｉウェーハの製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant