CN107615445B - 绝缘体上硅晶圆的制造方法 - Google Patents

绝缘体上硅晶圆的制造方法 Download PDF

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Publication number
CN107615445B
CN107615445B CN201680028359.7A CN201680028359A CN107615445B CN 107615445 B CN107615445 B CN 107615445B CN 201680028359 A CN201680028359 A CN 201680028359A CN 107615445 B CN107615445 B CN 107615445B
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wafer
silicon
heat treatment
oxide film
soi
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Chinese (zh)
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CN107615445A (zh
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横川功
阿贺浩司
小林德弘
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Shin Etsu Handotai Co Ltd
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Shin Etsu Handotai Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1924—Preparing SOI wafers with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Element Separation (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
CN201680028359.7A 2015-06-15 2016-03-08 绝缘体上硅晶圆的制造方法 Active CN107615445B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2015-120424 2015-06-15
JP2015120424A JP6380245B2 (ja) 2015-06-15 2015-06-15 Ｓｏｉウェーハの製造方法
PCT/JP2016/001235 WO2016203677A1 (ja) 2015-06-15 2016-03-08 Ｓｏｉウェーハの製造方法

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CN107615445A CN107615445A (zh) 2018-01-19
CN107615445B true CN107615445B (zh) 2020-10-30

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US (1) US10204824B2 (enExample)
EP (1) EP3309820B1 (enExample)
JP (1) JP6380245B2 (enExample)
KR (1) KR102327330B1 (enExample)
CN (1) CN107615445B (enExample)
SG (1) SG11201709420PA (enExample)
TW (1) TWI685019B (enExample)
WO (1) WO2016203677A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6473970B2 (ja) * 2015-10-28 2019-02-27 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
CN109037031B (zh) * 2018-07-11 2021-11-19 华东师范大学 一种掺镍氧化铜薄膜晶体管及制备方法
CN110739285A (zh) * 2019-10-30 2020-01-31 北京工业大学 硅基金属中间层化合物半导体晶圆的结构及制备方法
US12381085B2 (en) * 2020-04-02 2025-08-05 Tokyo Electron Limited Bonded substrate peripheral laser processing method and substrate processing apparatus thereof
KR102456461B1 (ko) 2020-11-26 2022-10-19 현대제철 주식회사 딥러닝을 이용한 철강 미세 조직 분석 방법 및 시스템
CN112582332A (zh) * 2020-12-08 2021-03-30 上海新昇半导体科技有限公司 一种绝缘体上硅结构及其方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1502135A (zh) * 2001-04-06 2004-06-02 ��Խ�뵼����ʽ���� Soi晶片及其制造方法
CN1868054A (zh) * 2003-10-14 2006-11-22 特拉希特技术公司 制备和组装基材的方法
CN101084577A (zh) * 2004-12-28 2007-12-05 特拉希特技术公司 修整通过组装两晶片构成的结构的方法
CN101689478A (zh) * 2007-06-21 2010-03-31 信越半导体股份有限公司 Soi芯片的制造方法
CN103299395A (zh) * 2010-12-20 2013-09-11 信越半导体股份有限公司 Soi晶片的制造方法
CN104025254A (zh) * 2012-01-06 2014-09-03 信越半导体株式会社 贴合soi晶片的制造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JPH11307472A (ja) 1998-04-23 1999-11-05 Shin Etsu Handotai Co Ltd 水素イオン剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP2000124092A (ja) * 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP4123861B2 (ja) * 2002-08-06 2008-07-23 株式会社Ｓｕｍｃｏ 半導体基板の製造方法
JP4603865B2 (ja) * 2004-12-01 2010-12-22 信越化学工業株式会社 酸化膜付きシリコン基板の製造方法及び酸化膜付きシリコン基板
JP2007317988A (ja) 2006-05-29 2007-12-06 Shin Etsu Handotai Co Ltd 貼り合わせウエーハの製造方法
JP2008028070A (ja) 2006-07-20 2008-02-07 Sumco Corp 貼り合わせウェーハの製造方法
JP5135935B2 (ja) 2007-07-27 2013-02-06 信越半導体株式会社 貼り合わせウエーハの製造方法
JP5531642B2 (ja) 2010-01-22 2014-06-25 信越半導体株式会社 貼り合わせウェーハの製造方法
JP5704039B2 (ja) * 2011-10-06 2015-04-22 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
JP5673572B2 (ja) 2012-01-24 2015-02-18 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1502135A (zh) * 2001-04-06 2004-06-02 ��Խ�뵼����ʽ���� Soi晶片及其制造方法
CN1868054A (zh) * 2003-10-14 2006-11-22 特拉希特技术公司 制备和组装基材的方法
CN101084577A (zh) * 2004-12-28 2007-12-05 特拉希特技术公司 修整通过组装两晶片构成的结构的方法
CN101689478A (zh) * 2007-06-21 2010-03-31 信越半导体股份有限公司 Soi芯片的制造方法
CN103299395A (zh) * 2010-12-20 2013-09-11 信越半导体股份有限公司 Soi晶片的制造方法
CN104025254A (zh) * 2012-01-06 2014-09-03 信越半导体株式会社 贴合soi晶片的制造方法

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Publication number Publication date
WO2016203677A1 (ja) 2016-12-22
JP6380245B2 (ja) 2018-08-29
KR102327330B1 (ko) 2021-11-17
EP3309820B1 (en) 2020-01-29
EP3309820A4 (en) 2019-01-23
KR20180016394A (ko) 2018-02-14
JP2017005201A (ja) 2017-01-05
CN107615445A (zh) 2018-01-19
SG11201709420PA (en) 2017-12-28
US20180144975A1 (en) 2018-05-24
EP3309820A1 (en) 2018-04-18
US10204824B2 (en) 2019-02-12
TW201643938A (zh) 2016-12-16
TWI685019B (zh) 2020-02-11

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