CN107004612A - 在基板与管芯之间包括光敏填料的集成器件封装 - Google Patents
在基板与管芯之间包括光敏填料的集成器件封装 Download PDFInfo
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- CN107004612A CN107004612A CN201580066082.2A CN201580066082A CN107004612A CN 107004612 A CN107004612 A CN 107004612A CN 201580066082 A CN201580066082 A CN 201580066082A CN 107004612 A CN107004612 A CN 107004612A
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Abstract
一种包括管芯、基板、填料以及导电互连的集成器件封装。管芯包括柱,其中柱具有第一柱宽度。基板(例如,封装基板、中介体)包括介电层和基板互连(例如,表面互连、嵌入式互连)。填料位于管芯与基板之间。导电互连位于填料内。导电互连包括与第一柱宽度大致相同或比其小的第一互连宽度。导电互连被耦合至柱和基板互连。填料是非导电光敏材料。填料是光敏膜。基板互连包括等于或大于第一柱宽度的第二互连宽度。导电互连包括至少糊剂、焊料和/或包括聚合材料的增强型焊料中的一者。
Description
相关申请的交叉引用
本申请要求于2014年12月12日在美国专利商标局提交的临时申请号62/091,400以及于2015年1月30日在美国专利商标局提交的非临时申请号14/610,876的优先权和权益,这两件申请的全部内容通过援引纳入于此。
背景
领域
各种特征涉及在基板与管芯之间包括光敏填料的集成器件封装。
背景技术
图1解说了包括管芯的集成封装的常规配置。具体地,图1解说了包括封装基板101、管芯103和填料130的集成器件封装100。封装基板101包括若干介电层(例如,介电层102)、若干互连(例如,迹线、通孔、焊盘)105和一组焊球115。封装基板101可包括互连111。互连111可以是位于封装基板101的表面上(例如,封装基板的介电层的表面上)的表面互连。互连111可以是迹线和/或焊盘。
如图1中所示,管芯103通过柱121、焊料123和互连111耦合至封装基板101。柱121被耦合至管芯103。柱121可以是金属层(例如,铜柱)。填料130位于封装基板101与管芯103之间。填料130包裹着柱121、焊料123和互连111。在一些实现中,填料130是糊剂。管芯103通过使用热压倒装芯片(TCFC)工艺耦合至封装基板101。使用TCFC工艺的结果是其产生横向拉长的焊料123,如图1中所示。具体地,拉长的焊料123具有比柱121的宽度和/或互连111的宽度大的横向宽度。拉长的焊料123在包括高密度、低节距和/或低间距的互连的封装中是有问题的,因为拉长的焊料123可能与附近的焊料、柱和/或互连形成物理接触,导致封装中的短路。
图2解说了可如何在管芯与封装基板之间形成焊料的另一示例。如图2中所示,管芯103通过柱121、焊料200和互连111耦合至封装基板101。填料230位于封装基板101与管芯103之间。填料230包裹着柱121、焊料200和互连111。填料230是底部填料。
在图2中,管芯103通过使用批量回流工艺耦合至封装基板101。使用批量回流工艺的结果是其也产生横向拉长的焊料200。具体地,拉长的焊料200具有比柱121的宽度和/或互连111的宽度大的横向宽度。此外,焊料200耦合至互连111的侧面部分(侧壁)。拉长的焊料200在包括高密度、低节距和/或低间距的互连的封装中是有问题的,因为拉长的焊料200可能与附近的焊料、柱和/或互连形成物理接触,导致封装中的短路。
图3解说了可如何在管芯与封装基板之间形成焊料的又一示例。具体地,图3解说了管芯103通过柱321、焊料323和互连311耦合至封装基板301。填料330位于封装基板301与管芯303之间。填料330包裹着柱321、焊料323和互连311。
柱321具有比互连311的宽度小的宽度。结果所得的柱321与互连311之间的焊料323是具有比柱321的宽度大的宽度的焊料323。这导致不必要的材料(例如,过多焊料323),从而导致集成封装的较高成本。此外,至少大部分焊料323具有比柱321大的尺寸。
因此,存在对提供这样一种设计的集成器件封装的需求,该设计不太可能产生将致使短路的焊料,从而导致较少缺陷的集成器件封装。理想地,这样的集成器件封装将具有更好的设计和形状因子、更低的成本,同时满足移动、可穿戴或便携式计算设备的需求和/或要求。
概述
本文所描述的各个特征、装置和方法涉及包括基板与管芯之间的光敏填料的集成器件封装。
第一示例提供了一种包括管芯、基板、位于管芯与基板之间的填料、以及位于填料内的导电互连的集成器件封装。管芯包括管芯互连,其中管芯互连包括第一管芯互连宽度。基板包括介电层和基板互连。导电互连包括与第一管芯互连宽度大致相同或比其小的第一互连宽度,其中导电互连被耦合至管芯互连和基板互连。
第二示例提供了一种用于制造集成器件封装的方法。该方法提供了包括管芯互连的管芯。管芯互连包括第一管芯互连宽度。该方法将非导电层和导电互连耦合至管芯和管芯互连,其中耦合非导电层和导电互连包括将导电互连耦合至管芯互连。导电互连包括与第一管芯互连宽度大致相同或比其小的第一互连宽度。该方法将管芯和非导电层耦合至包括介电层和基板互连的基板,其中将管芯和非导电层耦合至基板包括将导电互连耦合至基板互连。
附图
在结合附图理解下面阐述的详细描述时,各种特征、本质和优点会变得明显,在附图中,同样的参考特征贯穿始终作相应标识。
图1解说了常规集成器件封装。
图2解说了如何通过焊料将管芯耦合至基板的特写视图。
图3解说了如何通过焊料将管芯耦合至基板的特写视图。
图4解说了包括光敏填料的集成器件封装的横截面的剖面视图的示例。
图5解说了包括光敏填料的集成器件封装的横截面的剖面视图的示例。
图6解说了包括光敏填料的集成器件封装的横截面的剖面视图的示例。
图7解说了包括光敏填料的集成器件封装的横截面的剖面视图的示例。
图8解说了包括光敏填料的集成器件封装的横截面的剖面视图的示例。
图9解说了基板上包括阻焊层的集成器件封装的一部分。
图10解说了基板上包括阻焊层的另一集成器件封装的一部分。
图11解说了基板上包括阻焊层的集成器件封装的一部分。
图12解说了基板上包括阻焊层的另一集成器件封装的一部分。
图13解说了基板上包括阻焊层的集成器件封装的一部分。
图14(其包括图14A-14B)解说了用于提供/制造包括光敏填料的集成器件封装的示例性工序。
图15解说了一种用于提供/制造包括光敏填料的集成器件封装的方法的示例性流程图。
图16(其包括图16A-16B)解说了用于提供/制造包括光敏填料的集成器件封装的示例性工序。
图17解说了一种用于提供/制造包括光敏填料的集成器件封装的方法的示例性流程图。
图18解说了半加成图案化(SAP)工艺的示例。
图19解说了半加成图案化(SAP)工艺的流程图的示例。
图20解说了镶嵌工艺的示例。
图21解说了镶嵌工艺的流程图的示例。
图22解说了可集成本文所描述的集成器件、集成器件封装、半导体器件、管芯、集成电路、基板、中介体和/或PCB的各种电子设备。
详细描述
在以下描述中,给出了具体细节以提供对本公开的各方面的透彻理解。然而,本领域普通技术人员将理解,没有这些具体细节也可实践这些方面。例如,电路可用框图示出以避免使这些方面湮没在不必要的细节中。在其他实例中,公知的电路、结构和技术可不被详细示出以免模糊本公开的这些方面。
概览
一些特征涉及包括管芯、基板、填料以及导电互连的集成器件封装。管芯包括柱(例如,管芯互连),其中该柱具有第一柱宽度。基板(例如,封装基板、中介体)包括介电层和基板互连(例如,表面互连、嵌入式互连)。填料位于管芯与基板之间。导电互连位于填料内。导电互连包括与第一柱宽度大致相同或比其小的第一互连宽度。导电互连被耦合至柱和基板互连。在一些实现中,填料是非导电光敏材料。在一些实现中,填料是光敏膜。基板互连包括等于或大于第一柱宽度的第二互连宽度。基板互连包括等于或大于第一互连宽度的第二互连宽度。在一些实现中,导电互连包括至少糊剂、焊料和/或包括聚合材料的增强型焊料中的一者。
在一些实现中,互连是器件(例如,集成器件、集成器件封装、管芯)和/或基底(例如,封装基板、印刷电路板、中介体)的允许或促成两个点、元件和/或组件之间的电连接的元件或组件。在一些实现中,互连可包括迹线、通孔、焊盘、柱、重分布金属层、和/或凸块下金属化(UBM)层。在一些实现中,互连是为信号(例如,数据信号、接地信号、功率信号)提供电路径的电传导材料。互连可包括一个以上的元件/组件。
包括光敏填料的示例性集成器件封装
图4解说了包括光敏填料的集成器件封装。具体地,图4解说了包括基板401、管芯403和填料430的集成器件封装400。基板401可以是封装基板和/或中介体。基板401包括若干介电层(例如,介电层402、404、406、408、410)、若干互连(例如,迹线、通孔、焊盘)405、阻焊层412和一组焊球415。基板401可以是包括核心层的基板(例如,其中介电层402是核心层),或者基板401可以是无核基板。基板401可包括互连411(例如,基板互连)。互连411可以是位于基板401的表面上(例如,基板的介电层408的表面上)的表面互连。互连411可以是迹线和/或焊盘。基板401可包括若干互连411。
如图4中所示,管芯403通过柱421、导电互连423和互连411耦合至基板401。应当注意,管芯403可通过若干柱421、若干导电互连423和若干互连411耦合至基板401。柱421被耦合至管芯403。柱421被耦合(例如,电耦合)至管芯403的互连(例如,重分布互连、凸块下金属化(UBM)层)。在一些实现中,柱421是管芯403的一部分。柱421可以是管芯互连。柱421可具有不同形状和大小。柱421可以是金属层(例如,铜柱)。填料430位于封装基板401与管芯403之间。填料430包裹着柱421、导电互连423和互连411。填料430是非导电层和/或非导电膜。在一些实现中,填料430是光敏填料。光敏填料可以是可光图案化、可光刻和/或可光蚀刻的材料。例如,光敏填料可以是这样一种材料,一旦该光敏填料被暴露于光(例如,UV光),该材料就能被移除(洗去)。
导电互连423(例如,电传导互连)被耦合至柱421和互连411。不同实现可以将不同材料用于导电互连423。在一些实现中,导电互连423是糊剂(例如,铜糊剂)和/或焊料(例如,固化的焊料、包括聚合材料的增强型焊料)。
如图4中所示,导电互连423具有与柱421的尺寸(例如,管芯互连宽度)和/或互连411的尺寸大致相同(例如,相等)或比其小的尺寸(例如,宽度、直径)。在一些实现中,至少大部分(例如,一半以上、基本上全部、整个)导电互连423具有与柱421(例如,管芯互连)的尺寸(例如,管芯互连宽度)和/或互连411的尺寸大致相同或比其小的尺寸。与产生拉长的焊料的常规工艺不同,导电互连423的尺寸受填料430的控制和/或限定。具体地,导电互连423被限定在填料430的空腔中,如上所述填料430可以是非导电层/非导电膜。下文至少在图14A-14B中进一步描述如何形成导电互连423。在一些实现中,柱421、导电互连423、和/或互连411的节距约为40微米(μm)或更小。节距被定义为两个相邻和/或毗邻的互连柱、和/或导电互连之间中心到中心的距离。
作为填料430中的导电互连423的以上设计的结果,导电互连423将不接触另一导电互连或互连。另外,与常规方法相比,以上设计减少或消除了多余材料,由此导致较低成本的产品和/或器件。
在一些实现中,管芯可被耦合至嵌入在基板的表面中的互连。
图5解说了包括基板501、管芯403和填料430的集成器件封装500。基板501可以是封装基板和/或中介体。基板501包括若干介电层(例如,介电层402、404、406、408、410)、若干互连(例如,迹线、通孔、焊盘)405、阻焊层412和一组焊球415。基板501可以是包括核心层的基板(例如,其中介电层402是核心层),或者基板401可以是无核基板。基板401可包括互连511(例如,基板互连)。互连511可以是至少(例如,部分地、完全地)位于基板401的表面中(例如,基板的介电层408中)的嵌入式互连。互连511可以是迹线和/或焊盘。基板501可包括若干互连511。
如图5中所示,管芯403通过柱421、导电互连423和互连511耦合至基板501。应当注意,管芯403可通过若干柱421、若干导电互连423和若干互连511耦合至基板501。柱421被耦合至管芯403。柱421可以是管芯互连。柱421可以是金属层(例如,铜柱)。填料430位于封装基板501与管芯403之间。填料430包裹着柱421、导电互连423和互连511。填料430是非导电层和/或非导电膜。在一些实现中,填料430是光敏填料。光敏填料可以是可光图案化、可光刻、和/或可光蚀刻的材料。例如,光敏填料可以是这样一种材料,一旦该光敏填料被暴露于光(例如,UV光),该材料就能被移除(洗去)。
导电互连423(例如,电传导互连)被耦合至柱421和互连511。不同实现可以将不同材料用于导电互连423。在一些实现中,导电互连423是糊剂(例如,铜糊剂)和/或焊料(例如,固化的焊料、包括聚合材料的增强型焊料)。
如图5中所示,导电互连423具有与柱421的尺寸(例如,管芯互连宽度)和/或互连511的尺寸大致相同(例如,相等)或比其小的尺寸(例如,宽度、直径)。在一些实现中,至少大部分(例如,一半以上、基本上全部、整个)导电互连423具有与柱421(例如,管芯互连)的尺寸(例如,管芯互连宽度)和/或互连511的尺寸大致相同或比其小的尺寸。与产生拉长的焊料的常规工艺不同,导电互连423的尺寸受填料430的控制和/或限定。具体地,导电互连423被限定在填料430的空腔中,如上所述填料430可以是非导电层/非导电膜。下文至少在图14A-14B中进一步描述如何形成导电互连423。在一些实现中,柱421、导电互连423、和/或互连511的节距约为40微米(μm)或更小。节距被定义为两个相邻和/或毗邻的互连柱、和/或导电互连之间中心到中心的距离。
作为填料430中的导电互连423的以上设计的结果,导电互连423将不接触另一导电互连或互连。另外,与常规集成器件封装相比,以上设计减少或消除了多余材料,由此导致较低成本的产品、器件和/或封装。
在一些实现中,管芯的柱可具有与耦合至基板的互连的尺寸不同的尺寸。图6解说了包括基板501、管芯403和填料630的集成器件封装600。基板501可以是封装基板和/或中介体。基板501包括若干介电层(例如,介电层402、404、406、408、410)、若干互连(例如,迹线、通孔、焊盘)405、阻焊层412和一组焊球415。基板501可以是包括核心层的基板(例如,其中介电层402是核心层),或者基板501可以是无核基板。基板501可包括互连511(例如,基板互连)。互连511可以是至少(例如,部分地、完全地)位于基板501的表面中(例如,基板的介电层408中)的嵌入式互连。互连511可以是迹线和/或焊盘。
如图6中所示,管芯403通过柱621、导电互连623和互连511耦合至基板501。应当注意,管芯403可通过若干柱621、若干导电互连623和若干互连511耦合至基板501。柱621被耦合至管芯403。柱621被耦合(例如,电耦合)至管芯403的互连(例如,重分布互连、凸块下金属化(UBM)层)。在一些实现中,柱621是管芯403的一部分。柱621可以是管芯互连。柱621可具有不同形状和大小。柱621可以是金属层(例如,铜柱)。填料630位于封装基板501与管芯403之间。填料630包裹着柱621、导电互连623和互连511。填料630是非导电层和/或非导电膜。在一些实现中,填料630是光敏填料。光敏填料可以是可光图案化、可光刻、和/或可光蚀刻的材料。例如,光敏填料可以是这样一种材料,一旦该光敏填料被暴露于光(例如,UV光),该材料就能被移除(洗去)。
导电互连623(例如,电传导互连)被耦合至柱621和互连511。不同实现可以将不同材料用于导电互连623。在一些实现中,导电互连623是糊剂(例如,铜糊剂)和/或焊料(例如,固化的焊料、包括聚合材料的增强型焊料)。
如图6中所示,导电互连623具有与柱621(例如,管芯互连)的第一尺寸(例如,管芯互连宽度)大致相同(例如,相等)或比其小的第一尺寸(例如,宽度、直径)。在一些实现中,至少大部分(例如,一半以上、基本上全部、整个)导电互连623具有与柱621的尺寸和/或互连511的尺寸大致相同或比其小的尺寸。另外,导电互连623具有比互连511的第二尺寸小的第一尺寸。在此示例中,互连511具有比柱621和导电互连623两者都大的尺寸(例如,宽度、直径)。与产生完全湿涂(wet)至基板上的互连(例如,迹线、焊盘)的整个表面的焊料(见图3)的常规工艺不同,导电互连623的尺寸受填料630的控制和/或限定,填料630限制导电互连623仅湿涂(例如,物理耦合)至互连511的一部分。具体地,导电互连623被限定在填料630的空腔中,如上所述填料630可以是非导电层/非导电膜。下文至少在图14A-14B中进一步描述如何形成导电互连623。在一些实现中,柱621、导电互连623、和/或互连511的节距约为40微米(μm)或更小。
在一些实现中,管芯可被耦合至嵌入在基板的表面中的互连,其中嵌入式互连偏离基板的表面。
图7解说了包括基板701、管芯403和填料730的集成器件封装700。基板701可以是封装基板和/或中介体。基板701包括若干介电层(例如,介电层402、404、406、408、410)、若干互连(例如,迹线、通孔、焊盘)405、阻焊层412和一组焊球415。基板701可以是包括核心层的基板(例如,其中介电层402是核心层),或者基板401可以是无核基板。基板401可包括互连711(例如,基板互连)。互连711可以是至少(例如,完全地)位于基板701的表面中(例如,基板的介电层408中)的嵌入式互连。互连711被嵌入在基板的表面中,使得互连711偏离基板401的表面(例如,偏离基板的介电层408的表面)。互连711可以是迹线和/或焊盘。基板701可包括若干互连711。
如图7中所示,管芯403通过柱421、导电互连723和互连711耦合至基板701。应当注意,管芯403可通过若干柱421、若干导电互连723和若干互连711耦合至基板701。柱421被耦合至管芯403。柱621可以是管芯互连。柱421可以是金属层(例如,铜柱)。填料730位于封装基板701与管芯403之间。填料730包裹着柱421、导电互连723和互连711。填料730是非导电层和/或非导电膜。在一些实现中,填料730是光敏填料。光敏填料可以是可光图案化、可光刻、和/或可光蚀刻的材料。例如,光敏填料可以是这样一种材料,一旦该光敏填料被暴露于光(例如,UV光),该材料就能被移除(洗去)。
导电互连723(例如,电传导互连)被耦合至柱421和互连711。不同实现可以将不同材料用于导电互连723。在一些实现中,导电互连723是糊剂(例如,铜糊剂)和/或焊料(例如,固化的焊料、包括聚合材料的增强型焊料)。导电互连723被耦合至嵌入式互连711,使得至少一部分导电互连723被至少部分地嵌入在基板701中(例如,至少部分地嵌入在基板701的介电层408中)。
如图7中所示,导电互连723具有与柱421的尺寸(例如,管芯互连宽度)和/或互连711的尺寸大致相同(例如,相等)或比其小的尺寸(例如,宽度、直径)。在一些实现中,至少大部分(例如,一半以上、基本上全部、整个)导电互连723具有与柱421的尺寸和/或互连711的尺寸大致相同或比其小的尺寸。与产生拉长的焊料的常规工艺不同,导电互连723的尺寸受填料730的控制和/或限定。具体地,导电互连723被限定在填料730的空腔中,如上所述填料730可以是非导电层/非导电膜。下文至少在图14A-14B中进一步描述如何形成导电互连723。在一些实现中,柱421、导电互连723、和/或互连711的节距约为40微米(μm)或更小。
作为填料730中的导电互连723的以上设计的结果,导电互连723将不接触另一导电互连或互连。另外,与常规集成器件封装相比,以上设计减少或消除了多余材料,由此导致较低成本的产品、器件和/或封装。
在一些实现中,管芯的柱可具有与基板中的嵌入式互连的尺寸不同的尺寸。图8解说了包括基板701、管芯403和填料830的集成器件封装800。基板701可以是封装基板和/或中介体。基板701包括若干介电层(例如,介电层402、404、406、408、410)、若干互连(例如,迹线、通孔、焊盘)405、阻焊层412和一组焊球415。基板701可以是包括核心层的基板(例如,其中介电层402是核心层),或者基板701可以是无核基板。基板701可包括互连711(例如,基板互连)。互连711可以是至少(例如,部分地、完全地)位于基板701的表面中(例如,基板的介电层408中)的嵌入式互连。互连711被嵌入在基板的表面中,使得互连711偏离基板701的表面(例如,偏离基板的介电层408的表面)。互连711可以是迹线和/或焊盘。
如图8中所示,管芯403通过柱821、导电互连823和互连711耦合至基板701。应当注意,管芯403可通过若干柱821、若干导电互连823和若干互连711耦合至基板701。柱821被耦合至管芯403。柱821可以是管芯互连。柱821被耦合(例如,电耦合)至管芯403的互连(例如,重分布互连、凸块下金属化(UBM)层)。在一些实现中,柱821是管芯403的一部分。柱821可具有不同形状和大小。柱821可以是金属层(例如,铜柱)。填料830位于封装基板701与管芯403之间。填料830包裹着柱821、导电互连823和互连711。填料830是非导电层和/或非导电膜。在一些实现中,填料830是光敏填料。光敏填料可以是可光图案化、可光刻、和/或可光蚀刻的材料。例如,光敏填料可以是这样一种材料,一旦该光敏填料被暴露于光(例如,UV光),该材料就能被移除(洗去)。
导电互连823(例如,电传导互连)被耦合至柱821和互连711。不同实现可以将不同材料用于导电互连823。在一些实现中,导电互连823是糊剂(例如,铜糊剂)和/或焊料(例如,固化的焊料、包括聚合材料的增强型焊料)。导电互连823被耦合至嵌入式互连711,使得至少一部分导电互连823被至少部分地嵌入在基板701中(例如,至少部分地嵌入在基板701的介电层408中)。
如图8中所示,导电互连823具有与柱821(例如,管芯互连)的第一尺寸(例如,管芯互连宽度)大致相同(例如,相等)或比其小的第一尺寸(例如,宽度、直径)。在一些实现中,至少大部分(例如,一半以上、基本上全部、整个)导电互连823具有与柱821的尺寸和/或互连711的尺寸大致相同或比其小的尺寸。另外,导电互连823具有比互连711的第二尺寸小的第一尺寸。在此示例中,互连711具有比柱821和导电互连823两者都大的尺寸(例如,宽度、直径)。与产生完全湿涂至基板上的互连(例如,迹线、焊盘)的整个表面的焊料(见图3)的常规工艺不同,导电互连823的尺寸受填料830的控制和/或限定,填料830限制导电互连823仅湿涂(例如,物理耦合)至互连711的一部分。具体地,导电互连823被限定在填料830的空腔中,如上所述填料830可以是非导电层/非导电膜。下文至少在图14A-14B中进一步描述如何形成导电互连823。在一些实现中,柱821、导电互连823、和/或互连711的节距约为40微米(μm)或更小。
在一些实现中,阻焊(SR)层可位于管芯403与基板(例如,基板401、501、601、701、801)之间。图9-13解说了位于管芯403与基板之间的阻焊层900。在一些实现中,阻焊层900是基板的一部分。如图9-13中所示,阻焊层900位于介电层408上。
已经描述了包括光敏填料的若干集成器件封装,现在将在下文描述用于提供和/或制造这样的集成器件封装的工序和方法。
用于提供/制造包括光敏填料的集成器件封装的示例性工序
在一些实现中,提供/制造包括光敏填料的集成器件封装包括若干工艺。图14(其包括图14A-14B)解说了用于提供/制造包括光敏填料的集成器件封装的示例性工序。在一些实现中,图14A-14B的工序可被用来提供/制造图4-8的集成器件封装和/或本公开中描述的其他集成器件封装。然而,出于简化目的,将在提供/制造图6的集成器件封装的上下文中描述图14A-14B。
应当注意,图14A-14B的工序可以组合一个或多个阶段以简化和/或阐明用于提供集成器件封装的工序。在一些实现中,可以改变或修改各工艺的次序。
如图14A中所示,阶段1解说了在提供非导电层1400并将其耦合至载体1401之后的状态。非导电层1400可以是光敏层。光敏层可以是可光图案化、可光刻、和/或可光蚀刻的材料。非导电层1400可以是非导电膜。非导电层1400可以是填料。
阶段2解说了在形成光致抗蚀掩模层1402并将其耦合至非导电层1400之后的状态。光致抗蚀掩模层1402可包括如由光致抗蚀掩模层1402中的凹腔所例示出的图案。
阶段3解说了在非导电层1400中形成凹腔之后的状态。在一些实现中,在光蚀刻工艺(例如,光刻工艺)之后形成凹腔,其中非导电层1400通过光致抗蚀掩模层1402暴露于光(例如,UV光),并且非导电层1400的一些部分被移除(例如,洗去)。
阶段4解说了在光致抗蚀掩模层1402从非导电层1400解耦(例如,移除、剥离)之后留下剩余非导电层1400和载体1401的状态。
阶段5解说了在非导电层1400的凹腔(例如,凹腔1403)中形成导电互连1404之后的状态。不同实现可以将不同材料用于导电互连1404。在一些实现中,导电互连1404是糊剂(例如,铜糊剂)和/或焊料(例如,固化的焊料、包括聚合材料的增强型焊料)。在一些实现中,使用丝网印刷工艺在凹腔中形成导电互连1404。在一些实现中,导电互连1404可被固化。
应当注意,不同实现可提供不同水平高度或量的导电材料以形成导电互连1404。在一些实现中,非导电层1400的凹腔填满导电材料以形成导电互连1404。在其他实现中,非导电层1400的凹腔部分地填充导电材料以形成导电互连1404。凹腔中的导电材料可在非导电层1400的凹腔内移动和移位。
如图14B中所示,阶段6解说了在包括柱1412的管芯1410被耦合至非导电层1400和导电互连1404之后的状态。柱1412被耦合至导电互连1404。
阶段7解说了在载体1401从非导电层1400和导电互连1404解耦(例如,移除、剥离)之后留下管芯1410、柱1412、非导电层1400和导电互连1404的状态。
阶段8解说了在管芯1410、柱1412、非导电层1400和导电互连1404被耦合至基板1420之后的状态。非导电层1400可以是光敏填料。在一些实现中,基板1420(例如,封装基板、中介体)类似于如图5-6中示出和描述的基板501。如阶段8处所示,导电互连1404以如上文至少在图5-6中描述的方式耦合至基板的互连(例如,基板互连、表面互连、嵌入式互连)。
用于提供/制造包括光敏填料的集成器件封装的示例性方法
图15解说了一种用于提供/制造包括光敏填料的集成器件封装的方法1500的示例性流程图。在一些实现中,图15的方法可被用来提供/制造图4-8的包括光敏填料的集成器件封装和/或本公开中的其他电容器。
应当注意,图15的流程图可以组合一个或多个步骤和/或过程以简化和/或阐明用于提供集成器件封装的方法。在一些实现中,可以改变或修改各过程的次序。
该方法(在1505)提供非导电层并将该非导电层耦合至载体。非导电层可以是光敏层。光敏层可以是可光蚀刻的材料。非导电层可以是非导电膜。
该方法(在1510)将光致抗蚀掩模层耦合至非导电层。光致抗蚀掩膜层可包括图案。
该方法还(在1515)在非导电层中形成凹腔。在一些实现中,在光蚀刻工艺之后形成凹腔,其中非导电层通过光致抗蚀掩模层暴露于光(例如,UV光),并且非导电层的一些部分被移除(例如,洗去)。
该方法(在1520)移除光致抗蚀掩膜层,留下剩余非导电层和载体。
该方法随后(在1525)在非导电层的凹腔中形成导电互连。不同实现可以将不同材料用于导电互连。在一些实现中,导电互连是糊剂(例如,铜糊剂)和/或焊料(例如,固化的焊料、包括聚合材料的增强型焊料)。在一些实现中,使用丝网印刷工艺在凹腔中形成导电互连。在一些实现中,导电互连可被固化。
应当注意,不同实现可提供不同水平高度或量的导电材料以形成导电互连。在一些实现中,非导电层的凹腔填满导电材料以形成导电互连。在其他实现中,非导电层的凹腔部分地填充导电材料以形成导电互连。凹腔中的导电材料可在非导电层的凹腔内移动和移位。
该方法(在1530)将包括柱的管芯耦合至非导电层和导电互连。管芯的柱被耦合至导电互连。
该方法(在1535)移除载体,留下管芯、柱、非导电层和导电互连。
该方法(在1540)将管芯、柱、非导电层和导电互连耦合至基板。非导电层可以是光敏填料。在一些实现中,基板(例如,封装基板、中介体)类似于如图5-6中示出和描述的基板501。导电互连以如上文至少在图5-6中描述的方式耦合至基板的互连(例如,基板互连、表面互连、嵌入式互连)。
用于提供/制造包括光敏填料的集成器件封装的示例性工序
在一些实现中,提供/制造包括光敏填料的集成器件封装包括若干工艺。图16(其包括图16A-16B)解说了用于提供/制造包括光敏填料的集成器件封装的另一示例性工序。在一些实现中,图16A-16B的工序可被用来提供/制造图4-8的集成器件封装和/或本公开中描述的其他集成器件封装。然而,出于简化目的,将在提供/制造图6的集成器件封装的上下文中描述图16A-16B。
应当注意,图16A-16B的工序可以组合一个或多个阶段以简化和/或阐明用于提供集成器件的工序。在一些实现中,可以改变或修改各工艺的次序。
如图16A中所示,阶段1解说了在提供非导电层1600并将其耦合至载体1601之后的状态。非导电层1600可以是光敏层。光敏层可以是可光蚀刻的材料。非导电层1600可以是非导电膜。
阶段2解说了在形成光致抗蚀掩模层1602并将其耦合至非导电层1600之后的状态。光致抗蚀掩模层1602可包括如由光致抗蚀掩模层1602中的凹腔所例示出的图案。
阶段3解说了在非导电层1600中形成凹腔之后的状态。在一些实现中,在光蚀刻工艺之后形成凹腔,其中非导电层1600通过光致抗蚀掩模层1602暴露于光(例如,UV光),并且非导电层1600的一些部分被移除(例如,洗去)。
阶段4解说了在光致抗蚀掩模层1602从非导电层1600解耦(例如,移除、剥离)之后留下剩余非导电层1600和载体1601的状态。
阶段5解说了在非导电层1600的凹腔(例如,凹腔1603)中形成导电互连1604之后的状态。不同实现可以将不同材料用于导电互连1604。在一些实现中,导电互连1604是糊剂(例如,铜糊剂)和/或焊料(例如,固化的焊料、包括聚合材料的增强型焊料)。在一些实现中,使用丝网印刷工艺在凹腔中形成导电互连1604。在一些实现中,导电互连1604可被固化。
应当注意,不同实现可提供不同水平高度或量的导电材料以形成导电互连1604。在一些实现中,非导电层1600的凹腔填满导电材料以形成导电互连1604。在其他实现中,非导电层1600的凹腔部分地填充导电材料以形成导电互连1604。凹腔中的导电材料可在非导电层1600的凹腔内移动和移位。
如图16B中所示,阶段6解说了在非导电层1600、导电互连1604和载体1601被上下翻转之后的状态。
阶段7解说了在经翻转的非导电层1600、导电互连1604和载体1601被耦合至基板1620之后的状态。在一些实现中,基板1620(例如,封装基板、中介体)类似于如图5-6中示出和描述的基板501。如阶段7处所示,导电互连1604以如上文至少在图5-6中描述的方式耦合至基板的互连(例如,基板互连、表面互连、嵌入式互连)。
阶段8解说了在载体1601从非导电层1600和导电互连1604解耦(例如,移除、剥离)之后留下非导电层1600、导电互连1604和基板1620的状态。
阶段9解说了在管芯1610和柱1612被耦合至非导电层1600和导电互连1604之后的状态。非导电层1600可以是光敏填料。
用于提供/制造包括光敏填料的集成器件封装的示例性方法
图17解说了一种用于提供/制造包括光敏填料的集成器件封装的方法1700的示例性流程图。在一些实现中,图17的方法可被用来提供/制造图4-8的包括光敏填料的集成器件封装和/或本公开中的其他电容器。
应当注意,图17的流程图可以组合一个或多个步骤和/或过程以简化和/或阐明用于提供集成器件封装的方法。在一些实现中,可以改变或修改各过程的次序。
该方法(在1705)提供非导电层并将该非导电层耦合至载体。非导电层可以是光敏层。光敏层可以是可光蚀刻的材料。非导电层可以是非导电膜。
该方法(在1710)将光致抗蚀掩模层耦合至非导电层。光致抗蚀掩膜层可包括图案。
该方法还(在1715)在非导电层中形成凹腔。在一些实现中,在光蚀刻工艺之后形成凹腔,其中非导电层通过光致抗蚀掩模层暴露于光(例如,UV光),并且非导电层的一些部分被移除(例如,洗去)。
该方法(在1720)移除光致抗蚀掩膜层,留下剩余非导电层和载体。
该方法随后(在1725)在非导电层的凹腔中形成导电互连。不同实现可以将不同材料用于导电互连。在一些实现中,导电互连是糊剂(例如,铜糊剂)和/或焊料(例如,固化的焊料、包括聚合材料的增强型焊料)。在一些实现中,使用丝网印刷工艺在凹腔中形成导电互连。在一些实现中,导电互连可被固化。
应当注意,不同实现可提供不同水平高度或量的导电材料以形成导电互连。在一些实现中,非导电层的凹腔填满导电材料以形成导电互连。在其他实现中,非导电层的凹腔部分地填充导电材料以形成导电互连。凹腔中的导电材料可在非导电层的凹腔内移动和移位。
该方法(在1730)将非导电层和导电互连耦合至基板。非导电层可以是光敏填料。在一些实现中,基板(例如,封装基板、中介体)类似于如图5-6中示出和描述的基板501。导电互连以如上文至少在图5-6中描述的方式耦合至基板的互连(例如,基板互连、表面互连、嵌入式互连)。
该方法(在1735)移除载体,留下非导电层、导电互连和基板。
该方法(在1740)将包括柱的管芯耦合至非导电层、导电互连和基板。管芯的柱被耦合至导电互连,导电互连被耦合至基板的互连。
示例性半加成图案化(SAP)工艺
在本公开中描述了各种互连(例如,迹线、通孔、焊盘)。这些互连可被形成在集成器件封装的封装基板和/或重分布部分中。在一些实现中,这些互连可包括一个或多个金属层。例如,在一些实现中,这些互连可包括第一金属晶种层和第二金属层。可使用不同镀敷工艺来提供(例如,形成)这些金属层。以下是具有晶种层的互连(例如,迹线、通孔、焊盘)的详细示例以及可如何使用不同镀敷工艺来形成这些互连。
不同实现可使用不同工艺来形成和/或制造金属层(例如,互连、重分布层、凸块下金属化层、突起)。在一些实现中,这些工艺包括半加成图案化(SAP)工艺和/或镶嵌工艺。这些各种不同工艺在下文进一步描述。
图18解说了用于使用半加成图案化(SAP)工艺来形成互连以在一个或多个介电层中提供和/或形成互连的工序。如图18中所示,阶段1解说了在提供(例如,形成)介电层1802之后的集成器件(例如,基板)的状态。在一些实现中,阶段1解说了介电层1802包括第一金属层1804。在一些实现中,第一金属层1804是晶种层。在一些实现中,可在提供(例如,接收或形成)介电层1802之后在介电层1802上提供(例如,形成)第一金属层1804。阶段1解说了在介电层1802的第一表面上提供(例如,形成)第一金属层1804。在一些实现中,第一金属层1804是通过使用沉积工艺(例如,PVD、CVD、镀敷工艺)来提供的。
阶段2解说了在第一金属层1804上选择性地提供(例如,形成)光致抗蚀层1806(例如,光显影抗蚀层)之后的集成器件的状态。在一些实现中,选择性地提供光致抗蚀层1806包括在第一金属层1804上提供光致抗蚀层1806并且通过显影(例如,使用显影工艺)来选择性地移除光致抗蚀层1806的一些部分。阶段2解说了提供光致抗蚀层1806,使得凹腔1808被形成。
阶段3解说了在凹腔1808中形成第二金属层1810之后的集成器件的状态。在一些实现中,在第一金属层1804的暴露部分之上形成第二金属层1810。在一些实现中,第二金属层1810是通过使用沉积工艺(例如,镀敷工艺)来提供的。
阶段4解说了在移除光致抗蚀层1806之后的集成器件的状态。不同实现可使用不同工艺来移除光致抗蚀层1806。
阶段5解说了在选择性地移除第一金属层1804的一些部分之后的集成器件的状态。在一些实现中,移除第一金属层1804中未被第二金属层1810覆盖的一个或多个部分。如阶段5所示,剩余第一金属层1804和第二金属层1810可形成和/或限定集成器件和/或基板中的互连1812(例如,迹线、通孔、焊盘)。在一些实现中,移除第一金属层1804,以使得位于第二金属层1810下方的第一金属层1804的尺寸(例如,长度、宽度)与第二金属层1810的尺寸(例如,长度、宽度)大致相同或者比其小,这可导致底切,如图18的阶段5所示。在一些实现中,以上提及的过程可被迭代若干次以在集成器件和/或基板的一个或多个介电层中提供和/或形成若干互连。
图19解说了用于使用(SAP)工艺以在一个或多个介电层中提供和/或形成互连的方法的流程图。该方法(在1905)提供介电层(例如,介电层1802)。在一些实现中,提供介电层包括形成介电层。在一些实现中,提供介电层包括形成第一金属层(例如,第一金属层1804)。在一些实现中,第一金属层是晶种层。在一些实现中,可在提供(例如,接收或形成)介电层之后在介电层上提供(例如,形成)第一金属层。在一些实现中,第一金属层是通过使用沉积工艺(例如,物理气相沉积(PVD)或镀敷工艺)来提供的。
该方法(在1910)在第一金属层上选择性地提供光致抗蚀层(例如,光显影抗蚀层1806)。在一些实现中,选择性地提供抗蚀层包括在第一金属层上提供第一抗蚀层并且选择性地移除该抗蚀层的一些部分(这提供了一个或多个凹腔)。
该方法随后(在1915)在光致抗蚀层的凹腔中提供第二金属层(例如,第二金属层1810)。在一些实现中,在第一金属层的暴露部分之上形成第二金属层。在一些实现中,第二金属层是通过使用沉积工艺(例如,镀敷工艺)来提供的。
该方法进一步(在1920)移除抗蚀层。不同实现可使用不同工艺来移除抗蚀层。该方法还(在1925)选择性地移除第一金属层的一些部分。在一些实现中,移除第一金属层中未被第二金属层覆盖的一个或多个部分。在一些实现中,任何剩余第一金属层和第二金属层可形成和/或限定集成器件和/或基板中的一个或多个互连(例如,迹线、通孔、焊盘)。在一些实现中,以上提及的方法可被迭代若干次以在集成器件和/或基板的一个或多个介电层中提供和/或形成若干互连。
示例性镶嵌工艺
图20解说了用于使用镶嵌工艺来形成互连以在介电层中提供和/或形成互连的工序。如图20中所示,阶段1解说了在提供(例如,形成)介电层2002之后的集成器件的状态。在一些实现中,介电层2002是无机层(例如,无机膜)。
阶段2解说了在介电层2002中形成凹腔2004之后的集成器件的状态。不同实现可使用不同工艺来在介电层2002中提供凹腔2004。
阶段3解说了在介电层2002上提供第一金属层2006之后的集成器件的状态。如阶段3所示,在介电层2002的第一表面上提供第一金属层2006。在介电层2002上提供第一金属层2006,以使得第一金属层2006采取介电层2002的轮廓,包括腔体2004的轮廓在内。在一些实现中,第一金属层2006是晶种层。在一些实现中,第一金属层2006是通过使用沉积工艺(例如,物理气相沉积(PVD)、化学气相沉积(CVD)、或镀敷工艺)来提供的。
阶段4解说了在凹腔2004中和介电层2002的表面形成第二金属层2008之后的集成器件的状态。在一些实现中,在第一金属层2006的暴露部分之上形成第二金属层2008。在一些实现中,第二金属层2008是通过使用沉积工艺(例如,镀敷工艺)来提供的。
阶段5解说了在移除第二金属层2008的一些部分和第一金属层2006的一些部分之后的集成器件的状态。不同实现可使用不同工艺来移除第二金属层2008和第一金属层2006。在一些实现中,化学机械抛光(CMP)工艺被用来移除第二金属层2008的一些部分和第一金属层2006的一些部分。如阶段5所示,剩余第一金属层2006和第二金属层2008可形成和/或限定集成器件和/或基板中的互连2012(例如,迹线、通孔、焊盘)。如阶段5所示,以在第二金属层2010的基底部分和(诸)侧面部分上形成第一金属层2006的方式来形成互连2012。在一些实现中,凹腔2004可包括两级电介质中的沟和/或孔的组合,以使得可以在单个沉积步骤中形成通孔和互连(例如,金属迹线)。在一些实现中,以上提及的过程可被迭代若干次以在集成器件和/或基板的一个或多个介电层中提供和/或形成若干互连。
图21解说了用于使用镶嵌工艺来形成互连以在介电层中提供和/或形成互连的方法2100的流程图。该方法(在2105)提供介电层(例如,介电层2002)。在一些实现中,提供介电层包括形成介电层。在一些实现中,提供介电层包括从供应器接收介电层。在一些实现中,介电层是无机层(例如,无机膜)。
该方法(在2110)在介电层中形成至少一个凹腔(例如,凹腔2004)。不同实现可使用不同工艺来在介电层中提供凹腔。
该方法(在2115)在介电层上提供第一金属层(例如,第一金属层2006)。在一些实现中,在介电层的第一表面上提供(例如,形成)第一金属层。在一些实现中,在介电层上提供第一金属层,以使得第一金属层采取介电层的轮廓,包括凹腔的轮廓在内。在一些实现中,第一金属层是晶种层。在一些实现中,第一金属层2006是通过使用沉积工艺(例如,PVD、CVD或镀敷工艺)来提供的。
该方法(在2120)在凹腔中和介电层的表面提供第二金属层(例如,第二金属层2008)。在一些实现中,在第一金属层的暴露部分之上形成第二金属层。在一些实现中,第二金属层是通过使用沉积工艺(例如,镀敷工艺)来提供的。在一些实现中,第二金属层与第一金属层类似或相同。在一些实现中,第二金属层不同于第一金属层。
该方法随后(在2125)移除第二金属层的一些部分和第一金属层的一些部分。不同实现可使用不同工艺来移除第二金属层和第一金属层。在一些实现中,化学机械抛光(CMP)工艺被用来移除第二金属层的一些部分和第一金属层的一些部分。在一些实现中,剩余第一金属层和第二金属层可形成和/或限定互连(例如,互连2012)。在一些实现中,互连可包括集成器件和/或基板中的至少迹线、通孔、和/或焊盘中的一者。在一些实现中,以在第二金属层的基底部分和(诸)侧面部分上形成第一金属层的方式来形成互连。在一些实现中,以上提及的方法可被迭代若干次以在集成器件和/或基板的一个或多个介电层中提供和/或形成若干互连。
示例性电子设备
图22解说了可集成有前述集成器件、半导体器件、集成电路、管芯、中介体、封装或层叠封装(PoP)中的任意者的各种电子设备。例如,移动电话2202、膝上型计算机2204、以及固定位置终端2206可包括如本文所描述的集成器件2200。集成器件2200可以是例如本文所描述的集成电路、管芯、封装或层叠封装中的任意者。图22中所例示出的设备2202、2204、2206仅是示例性的。其他电子设备也可以集成器件2200为其特征,此类电子设备包括但不限于移动设备、手持式个人通信系统(PCS)单元、便携式数据单元(诸如个人数字助理)、能启用全球定位系统(GPS)的设备、导航设备、机顶盒、音乐播放器、视频播放器、娱乐单元、固定位置数据单位(诸如仪表读取装备)、通信设备、智能电话、可穿戴设备、平板计算机、或者存储或检索数据或计算机指令的任何其他设备,或者其任何组合。
图4、5、6、7、8、9A-9B、10、11A-11B、12、13、14、15、16、17、18、19、20、21、和/或22中所例示的组件、步骤、特征、和/或功能中的一者或多者可被重新编排和/或组合成单个组件、步骤、特征或功能,或体现在若干组件、步骤、或功能中。也可添加额外的元件、组件、步骤、和/或功能而不会脱离本公开。还应当注意,本公开中的图4、5、6、7、8、9、10、11、12、13、14A-14B、15、16A-16B、17、18、19、20、21和/或22及其相应描述并不限于管芯和/或IC。在一些实现中,图4、5、6、7、8、9、10、11、12、13、14A-14B、15、16A-16B、17、18、19、20、21和/或22及其相应描述可被用来制造、创建、提供、和/或产生集成器件。在一些实现中,集成器件可以包括管芯、管芯封装、集成电路(IC)、集成器件封装、晶片、半导体器件、层叠封装、和/或中介体。
措辞“示例性”在本文中用于表示“用作示例、实例或例示”。本文中描述为“示例性”的任何实现或方面不必被解释为优于或胜过本公开的其他方面。同样,术语“方面”不要求本公开的所有方面都包括所讨论的特征、优点或操作模式。术语“耦合”在本文中用于指两个对象之间的直接或间接耦合。例如,如果对象A物理地接触对象B,且对象B接触对象C,则对象A和C可仍被认为是彼此耦合的——即便它们并非彼此直接物理接触。
一“组”对象可包括一个或多个对象。例如,一组通孔可包括一个或多个通孔。一组互连可包括一个或多个互连。
还应注意,这些实施例可作为被描绘为流程图、流图、结构图、或框图的过程来被描述。尽管流程图可把各操作描述为顺序过程,但是这些操作中有许多操作能够并行或并发地执行。另外,这些操作的次序可以被重新安排。过程在其操作完成时终止。
本文所描述的本公开的各种特征可被实现于不同系统中而不会脱离本公开。应当注意,本公开的以上各方面仅是示例,且不应被解释成限定本公开。对本公开的各方面的描述旨在是解说性的,而非限定所附权利要求的范围。由此,本发明的教导可以现成地应用于其他类型的装置,并且许多替换、修改和变形对于本领域技术人员将是显而易见的。
Claims (20)
1.一种集成器件封装,包括:
管芯,所述管芯包括管芯互连,其中所述管芯互连包括第一管芯互连宽度;
基板,所述基板包括介电层和基板互连;
填料,所述填料位于所述管芯与所述基板之间;以及
导电互连,所述导电互连位于所述填料内,所述导电互连包括与所述第一管芯互连宽度大致相同或比其小的第一互连宽度,其中所述导电互连被耦合至所述管芯互连和所述基板互连。
2.如权利要求1所述的集成器件封装,其特征在于,所述填料是非导电光敏材料。
3.如权利要求1所述的集成器件封装,其特征在于,所述填料是光敏膜。
4.如权利要求1所述的集成器件封装,其特征在于,所述基板互连包括等于或大于所述第一管芯互连宽度的第二互连宽度。
5.如权利要求1所述的集成器件封装,其特征在于,所述基板互连包括等于或大于所述第一互连宽度的第二互连宽度。
6.如权利要求1所述的集成器件封装,其特征在于,所述导电互连包括至少糊剂、焊料和/或包括聚合材料的增强型焊料中的一者。
7.如权利要求1所述的集成器件封装,其特征在于,所述基板互连是至少表面互连和/或嵌入式互连中的一者。
8.如权利要求1所述的集成器件封装,其特征在于,所述管芯互连是来自包括约40微米(μm)或更小的节距的一组柱中的一者。
9.如权利要求1所述的集成器件封装,其特征在于,所述基板是至少封装基板和/或中介体中的一者。
10.如权利要求1所述的集成器件封装,其特征在于,所述集成器件封装被集成到从包括以下各项的组中选择的设备中:音乐播放器、视频播放器、娱乐单元、导航设备、通信设备、移动设备、移动电话、智能电话、个人数字助理、固定位置终端、平板计算机、计算机、可穿戴设备、以及膝上型计算机,并且进一步包括所述设备。
11.一种用于制造集成器件封装的方法,包括:
提供包括管芯互连的管芯,其中所述管芯互连包括第一管芯互连宽度;
将非导电层和导电互连耦合至所述管芯和所述管芯互连,其中耦合所述非导电层和所述导电互连包括将所述导电互连耦合至所述管芯互连,所述导电互连包括与所述第一管芯互连宽度大致相同或比其小的第一互连宽度;以及
将所述管芯和所述非导电层耦合至包括介电层和基板互连的基板,其中将所述管芯和所述非电导层耦合至所述基板包括将所述导电互连耦合至所述基板互连。
12.如权利要求11所述的方法,其特征在于,所述非导电层是非导电光敏材料。
13.如权利要求11所述的方法,其特征在于,所述非导电层是光敏膜。
14.如权利要求11所述的方法,其特征在于,所述基板互连包括等于或大于所述第一管芯互连宽度的第二互连宽度。
15.如权利要求11所述的方法,其特征在于,所述基板互连包括等于或大于所述第一互连宽度的第二互连宽度。
16.如权利要求11所述的方法,其特征在于,所述导电互连包括至少糊剂、焊料和/或包括聚合材料的增强型焊料中的一者。
17.如权利要求11所述的方法,其特征在于,所述基板互连是至少表面互连和/或嵌入式互连中的一者。
18.如权利要求11所述的方法,其特征在于,所述管芯互连是来自包括约40微米(μm)或更小的节距的一组柱中的一者。
19.如权利要求11所述的方法,其特征在于,所述基板是至少封装基板和/或中介体中的一者。
20.如权利要求11所述的方法,其特征在于,所述集成器件封装被集成到从包括以下各项的组中选择的设备中:音乐播放器、视频播放器、娱乐单元、导航设备、通信设备、移动设备、移动电话、智能电话、个人数字助理、固定位置终端、平板计算机、计算机、可穿戴设备、以及膝上型计算机,并且进一步包括所述设备。
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US10037941B2 (en) | 2018-07-31 |
US20160172299A1 (en) | 2016-06-16 |
WO2016094721A1 (en) | 2016-06-16 |
CN107004612B (zh) | 2020-11-24 |
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