JP5018399B2 - 回路基板の製造方法 - Google Patents
回路基板の製造方法 Download PDFInfo
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- JP5018399B2 JP5018399B2 JP2007278491A JP2007278491A JP5018399B2 JP 5018399 B2 JP5018399 B2 JP 5018399B2 JP 2007278491 A JP2007278491 A JP 2007278491A JP 2007278491 A JP2007278491 A JP 2007278491A JP 5018399 B2 JP5018399 B2 JP 5018399B2
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- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/731—Location prior to the connecting process
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- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Description
12 フィルム
13 マスク
14 炭酸ガスレーザ
15 テーパ状の貫通孔
16 金メッキ板
17 ポジレジスト膜
18 樹脂フィルム
100 回路基板
101 第1フィルム
101a 第1フィルムの表面側の第1開口
101b 第1フィルムの裏面側の第2開口
102 はんだボール
103 第2フィルム
103a 第2フィルムの表面側の第3開口
103b 第2フィルムの裏面側の第4開口
104 半導体素子
105 基板電極
106 半導体素子電極
201 第1フィルム
201a 第1フィルムの表面側の第1開口
201b 第1フィルムの裏面側の第2開口
202 はんだボール
203 第2フィルム
203a 第2フィルムの表面側の第3開口
203b 第2フィルムの裏面側の第4開口
204 半導体素子
205 基板電極
206 半導体素子電極
301 第1フィルム
301a 第1フィルムの表面側の第1開口
301b 第1フィルムの裏面側の第2開口
302 はんだボール
303 第2フィルム
303a 第2フィルムの表面側の第3開口
303b 第2フィルムの裏面側の第4開口
304 半導体素子
305 基板電極
306 半導体素子電極
307 導電ペースト
Claims (5)
- 第1基板上に第1電極を形成する工程と、
第2基板上に第2電極を形成する工程と、
第1フィルムに、該第1フィルムの表面側の第1開口が、裏面側の第2開口よりも大き
い第1貫通孔を形成する工程と、
第2フィルムに、該第2フィルムの表面側の第3開口が、裏面側の第4開口よりも大き
い第2貫通孔を形成する工程と、
前記第1フィルムの前記第1開口上に、はんだボールを載置する工程と、
前記はんだボールを介して、前記第1フィルム上に前記第2フィルムを配置し、該第1
フィルムの前記第1開口と、該第2フィルムの前記第3開口との位置合わせを行う工程と
、
前記第1基板の前記第1電極と、前記第1フィルムの前記第2開口との位置合わせを行
う工程と、
前記第2基板の前記第2電極と、前記第2フィルムの前記第4開口との位置合わせを行
う工程と、
前記第2フィルムの貫通孔に更に導電ペーストを充填し、その後前記はんだボールを加
熱溶融して、前記第1電極と前記第2電極とを電気的に接続する工程と
を含むことを特徴とする回路基板の製造方法。 - 前記第1フィルム及び第2フィルムは、熱可塑フィルム、熱融着フィルム、または熱硬
化性フィルムであることを特徴とする請求項1記載の回路基板の製造方法。 - 前記はんだボールは、SnAg、SnIn、SnBi、SuAg及びSuAgCuを含
むはんだペーストで形成されたことを特徴とする請求項1又は2記載の回路基板の製造方
法。 - 前記加熱溶融を行う前、又は後、又は同時に、前記第1フィルムと前記第2フィルムを
加圧することを特徴とする請求項1乃至3のいずれか一項に記載の回路基板の製造方法。 - 基板上に第1電極を形成する工程と、
半導体素子上に第2電極を形成する工程と、
第1フィルムに、該第1フィルムの表面側の第1開口が、裏面側の第2開口よりも大き
い第1貫通孔を形成する工程と、
第2フィルムに、該第2フィルムの表面側の第3開口が、裏面側の第4開口よりも大き
い第2貫通孔を形成する工程と、
前記第1フィルムの前記第1開口上に、はんだボールを載置する工程と、
前記はんだボールを介して、前記第1フィルム上に前記第2フィルムを配置し、該第1
フィルムの前記第1開口と、該第2フィルムの前記第3開口との位置合わせを行う工程と
、
前記基板上に形成された前記第1電極と、前記第1フィルムの前記第2開口との位置合
わせを行う工程と、
前記半導体素子に形成された前記第2電極と、前記第2フィルムの前記第4開口との位
置合わせを行う工程と、
前記第2フィルムの貫通孔に更に導電ペーストを充填し、その後前記はんだボールを加
熱溶融して、前記第1電極と前記第2電極とを電気的に接続する工程と
を含むことを特徴とする回路基板の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007278491A JP5018399B2 (ja) | 2007-10-26 | 2007-10-26 | 回路基板の製造方法 |
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Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007278491A JP5018399B2 (ja) | 2007-10-26 | 2007-10-26 | 回路基板の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009110991A JP2009110991A (ja) | 2009-05-21 |
JP5018399B2 true JP5018399B2 (ja) | 2012-09-05 |
Family
ID=40779197
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007278491A Expired - Fee Related JP5018399B2 (ja) | 2007-10-26 | 2007-10-26 | 回路基板の製造方法 |
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JP (1) | JP5018399B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8237279B2 (en) | 2010-09-10 | 2012-08-07 | International Business Machines Corporation | Collar structure around solder balls that connect semiconductor die to semiconductor chip package substrate |
JP5662855B2 (ja) * | 2011-03-25 | 2015-02-04 | 株式会社日立製作所 | プリント基板の製造装置および製造方法 |
US10037941B2 (en) * | 2014-12-12 | 2018-07-31 | Qualcomm Incorporated | Integrated device package comprising photo sensitive fill between a substrate and a die |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05251505A (ja) * | 1991-12-27 | 1993-09-28 | Minnesota Mining & Mfg Co <3M> | Icチップのエリアテープへの接続方法 |
JP3316998B2 (ja) * | 1994-03-07 | 2002-08-19 | 富士通株式会社 | 薄膜コネクタとそれを用いた半導体チップの実装方法 |
JP3362370B2 (ja) * | 1998-05-14 | 2003-01-07 | 住友ベークライト株式会社 | 導電性ボール配列シートおよび導電性ボール配列シート製造装置 |
JP2001185577A (ja) * | 1999-12-24 | 2001-07-06 | Hitachi Ltd | 電子機器 |
JP4970767B2 (ja) * | 2005-10-26 | 2012-07-11 | リンテック株式会社 | 導電接合シート用の絶縁シート、導電接合シート、導電接合シートの製造方法および電子複合部品の製造方法 |
-
2007
- 2007-10-26 JP JP2007278491A patent/JP5018399B2/ja not_active Expired - Fee Related
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JP2009110991A (ja) | 2009-05-21 |
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