CN106415826A - 半导体器件和制造半导体器件的方法 - Google Patents
半导体器件和制造半导体器件的方法 Download PDFInfo
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- CN106415826A CN106415826A CN201580032469.6A CN201580032469A CN106415826A CN 106415826 A CN106415826 A CN 106415826A CN 201580032469 A CN201580032469 A CN 201580032469A CN 106415826 A CN106415826 A CN 106415826A
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Abstract
本技术涉及能够抑制半导体器件的翘曲的半导体器件以及制造半导体器件的方法。脱模剂(101)涂布于上芯片(11)的侧面部分。因此,当涂布用于保护凸块(21)的密封树脂(31)时,上芯片(11)与下芯片(12)之间的凸块(21)得到保护,并且由于脱模剂(101),其成填角形状突出的一部分不会粘附至上芯片(11)的侧面部分,并且因此形成间隙(111)。因此,即使伴随上芯片(11)的侧面部分与下芯片(12)的上表面之间的密封树脂(31)的干燥而出现收缩,也不会产生使下芯片(12)翘曲的压力,因此可以抑制翘曲。该技术可应用于半导体器件。
Description
技术领域
本技术涉及半导体器件及制造半导体器件的方法并且尤其涉及能够抑制半导体器件的翘曲的半导体器件及制造半导体器件的方法。
背景技术
通过在电路基板上倒装芯片安装半导体芯片获取的半导体器件已知为半导体器件的模式。在这类半导体器件中,电路基板和半导体芯片通过称作凸块的连接端子电气且机械地连接至彼此。
另外,电路基板与半导体芯片之间的间隔(间隙)利用称作底部填充材料的密封树脂填充用于保护作为连接端子的凸块。底部填充材料通过使用毛细现象填充电路基板与半导体芯片之间的间隔。在那时,在底部张开的填角(fillet)形成在半导体芯片的外周缘上,填角由从其中突出的底部填充材料形成。
诸如环氧树脂的热固性树脂用作底部填充材料。因此,处于液体状态的底部填充材料注入电路基板与半导体芯片之间的间隔中以填充该间隔并且此后通过热处理固化。在那时,翘曲会由于与底部填充材料的填角形突出部分的热收缩相关联的压力而出现在电路基板上。而且,当进行诸如温度循环试验的可靠性试验时,由于类似原因在电路基板上会出现翘曲。
因此,建议了通过形成凹陷部分防止下芯片上的树脂突出而采取措施的技术(参考专利文献1)。
另外,建议了通过使用线性膨胀系数不同的几种类型的密封树脂减小翘曲的技术(参考专利文献2)。
而且,建议了通过在下基板上设置凹槽减小翘曲的技术(参考专利文献3)。
现有技术文献
专利文献
专利文献1:特开2010-165814号公报
专利文献2:特开2013-141027号公报
专利文献3:特开10-233465号公报
发明内容
本发明要解决的问题
同时,应涂布密封树脂的位置基本上是设置在上芯片与下芯片之间的凸块部分。然而,通常当涂布密封树脂时,密封树脂均匀地应用于下芯片的上表面,但是密封树脂涂布于除了上芯片的底面的侧面,使得密封树脂在上芯片与下芯片之间以填角形状粘附。然后,由于填角形密封树脂在固化时的热收缩,在粘附至上芯片的侧面的密封树脂与粘附至下芯片的上表面的密封树脂之间产生压力,所以在半导体器件中出现与压力相关联的翘曲,使得芯片可能破裂。
另外,虽然专利文献1的技术通过设置防止树脂在下芯片上的突出的凹陷部分采取措施,但是设置大的凹陷部分会增加成本。另外,当将来芯片制成更薄时,下芯片的强度会由于凹陷部分本身降低。
另外,虽然专利文献2的技术通过使用具有不同线性膨胀系数的密封树脂减小翘曲,但是树脂的线性膨胀系数与诸如粘度和弹性的另外的物理特性有相互关系,使得除翘曲以外的性能或许可能改变并且可能无法自由选择树脂。
而且,在专利文献3的技术中的下基板上设置了凹槽,使得当芯片制成更薄时强度同样会降低。
鉴于这种状况实现本技术并且本技术的目的尤其是通过简单方法抑制半导体器件的翘曲。
问题的解决方案
根据本技术的一方面的半导体器件包括:上半导体芯片;下半导体芯片;凸块,连接上半导体芯片至下半导体芯片;密封树脂,保护凸块;以及间隙,形成在从密封树脂的存在凸块的区域突出的填角形区域与上半导体芯片的侧面与下半导体芯片的上表面中的任一个之间。
间隙可以通过在涂布密封树脂之前在从当涂布密封树脂时存在凸块的区域突出的填角形区域与上半导体芯片的侧面与下半导体芯片的上表面中的任一个之间的位置中布置隔板、涂布密封树脂、并且此后去除隔板形成。
隔板可以是与密封树脂接触的部分被涂布脱模剂的板状构件或者由在密封树脂被干燥时的通过热蒸发或者升华的材料形成的板状构件。
间隙可以形成在上半导体芯片的侧面与填角形密封树脂之间。
脱模剂可以涂布于上半导体芯片的侧面,并且间隙可以在通过涂布于上半导体芯片的侧面的脱模剂从上半导体芯片的侧面释放填角形密封树脂时形成。
除了上半导体芯片的侧面,脱模剂可以涂布于上表面。
间隙可以形成在下半导体芯片的除与上半导体芯片相对的区域以外的区域的上表面与填角形密封树脂之间。
脱模剂可以涂布于下半导体芯片的除与上半导体芯片相对的区域以外的区域中的上表面,并且间隙可以在填角形密封树脂通过涂布于下半导体芯片的除与上半导体芯片相对的区域以外的区域的上表面的脱模剂而从下半导体芯片的除与上半导体芯片相对的区域以外的区域的上表面释放时形成。
多个上半导体芯片可以在彼此通过凸块连接并且通过凸块连接至下半导体芯片的状态下堆叠,并且间隙可以形成在从存在凸块的区域突出的填角形密封树脂与多个堆叠的上半导体芯片的侧面与下半导体芯片的上表面中的任一个之间。
通过堆叠多个上半导体芯片获取的第一配置以及由上半导体芯片形成的第二配置可以通过凸块在相邻位置处连接至下半导体芯片,第二配置不同于第一配置,并且间隙可以形成在第一配置和第二配置彼此不相邻的区域中、形成在从存在凸块的区域突出的填角形密封树脂与第一配置的侧面与下半导体芯片的上表面中的任一个之间、以及在密封树脂与第二配置的侧面与下半导体芯片的上表面中的任一个之间。
根据本技术的一方面制造半导体器件的方法是制造包括以下的半导体器件的方法:上半导体芯片;下半导体芯片;凸块,连接上半导体芯片至下半导体芯片;密封树脂,保护凸块;以及间隙,形成在从密封树脂的存在凸块的区域突出的填角形区域与上半导体芯片的侧面与下半导体芯片的上表面中的任一个之间,方法,其中,在涂布密封树脂之前执行形成间隙的处理。
形成间隙的处理是在从当涂布密封树脂时存在凸块的区域突出的填角形区域与上半导体芯片的侧面与下半导体芯片的上表面中的任一个之间的位置中布置隔板,并且隔板可以在涂布密封树脂之后去除的处理。
隔板可以是与密封树脂接触的部分涂布脱模剂的板状构件或者在密封树脂被干燥时通过热蒸发或者升华的材料形成的板状构件。
形成间隙的处理可以是将脱模剂涂布至上半导体芯片的侧面的处理。
形成间隙的处理可以是将脱模剂涂布至下半导体芯片的不与上半导体芯片相对的区域中的上表面的处理。
本技术的一方面是半导体器件,该半导体器件包括:上半导体芯片;以及下半导体芯片,其中,凸块连接上半导体芯片至下半导体芯片,密封树脂保护凸块,并且间隙形成在从存在凸块的区域突出的填角形区域与上半导体芯片的侧面与下半导体芯片的上表面中的任一个之间。
本发明的效果
根据本技术的一方面,半导体器件的翘曲可以得到抑制。
附图说明
图1是示出了一般半导体器件的配置的视图。
图2是示出了应用本技术的半导体器件的配置的视图。
图3是示出了应用本技术的半导体器件的第一变型的视图。
图4是示出了制造图3中的半导体器件的方法的视图。
图5是示出了制造图2和图3中的半导体器件的过程的流程图。
图6是示出了应用本技术的半导体器件的第二变型的视图。
图7是示出了制造图6中的半导体器件的过程的流程图。
图8是示出了应用本技术的半导体器件的第三变型的视图。
图9是示出了制造图8中的半导体器件的过程的流程图。
图10是示出了应用本技术的半导体器件的第三变型的另一实例的视图。
图11是示出了应用本技术的半导体器件的第四变型的视图。
图12是示出了应用本技术的半导体器件的第五变型的视图。
图13是示出了应用本技术的半导体器件的第六变型的视图。
具体实施方式
<一般半导体器件的配置>
本技术是用于抑制半导体器件翘曲的技术。应当注意,在描述本技术的半导体器件的配置之前,描述一般半导体器件的配置。
图1中的半导体器件通过将半导体芯片(上芯片11)倒装安装在电路基板(下芯片12)上获取。在图1中的半导体器件中,电路基板(下芯片12)和半导体芯片(上芯片11)通过称作凸块21的连接端子电气且机械地连接至彼此。
另外,电路基板(下芯片12)与半导体芯片(上芯片11)之间的间隔(间隙)填充有称作底部填充材料的密封树脂31以保护凸块21。电路基板(下芯片12)与半导体芯片(上芯片11)之间的间隔通过使用毛细现象(capillary phenomenon)利用密封树脂31填充。在那时,在底部张开的填角(fillet)形成在半导体芯片(上芯片11)的外周缘上,填角由从其中突出的密封树脂31形成,如在图1的左侧部分中示出的。
同时,诸如环氧树脂的热固性树脂用作密封树脂31。因此,处于液体状态的密封树脂31注入电路基板(下芯片12)与半导体芯片(上芯片11)之间的间隔以填充该间隔,并且此后通过热处理固化。
在那时,由于与密封树脂31的填角状突出部分的热收缩相关联的压力,在半导体芯片(上芯片11)和电路基板(下芯片12)上均出现翘曲,如在图1的右侧部分中示出的。而且,同样当进行诸如温度循环试验的可靠性试验时,由于类似原因在电路基板上出现翘曲。
<应用本技术的半导体器件>
图2示出了应用本技术的半导体器件的配置。应注意,具有与图1中的配置相同功能的配置分配相同的名称和参考标号;其描述适当省去。
就是说,图2中的半导体器件与图1中的半导体器件的不同之处在于脱模剂101涂布于上芯片11的侧面。脱模剂101是氟树脂等,例如,其防止粘附涂布的密封树脂31。脱模剂101在涂布密封树脂31之前涂布于上芯片11的侧面,使得当此后密封树脂31涂布于凸块21时,密封树脂31没有粘附至上芯片11的侧面,密封树脂31不与脱模剂101接触,并且设置了间隙111。
就是说,如图2所示,上芯片11的侧面没有粘结至密封树脂31并且其间设置了间隙111,使得上述与热收缩相关联的压力没有产生并且变得可以抑制下芯片12的翘曲。
<第一变型>
虽然至此描述了脱模剂101仅涂布至上芯片11的侧面的实例,脱模剂101涂布于侧面足够了,使得脱模剂101不仅可以涂布至上芯片11的侧面而且可以涂布至其上表面,如在图3中示出的。
通过以这种方式配置,变得不需要在制造过程中仅选择性地将脱模剂101涂布至上芯片11的侧面,使得例如可以同时将利用水或者有机溶剂稀释的脱模剂101-1至101-3涂布至如图4所示的布置在切割台121上的上芯片11-1至11-3,因此简化工作过程。应当注意,虽然在图4中示出了三个上芯片11-1至11-3布置在切割台121上的实例,但是其数量可以等于或大于此。
<第一制造过程>
接下来参考图5中的流程图描述第一制造过程。
在步骤S31,脱模剂101仅涂布至如图2所示的布置在切割台121上的上芯片11的侧面或者涂布至如在图3和图4中示出的上表面和侧面。
在步骤S32,上芯片11被切块以单独切割。
在步骤S33,上芯片11和下芯片12通过凸块21电气且机械地连接至彼此。
在步骤S34,密封树脂31涂布于下芯片12的上表面,通过毛细现象浸透到凸块21中,并且进一步干燥(dry)以固化为如图2或者图3所示的填角形状。
在步骤S35,通过涂布于上芯片11的侧面的脱模剂101防止粘附涂布的密封树脂31,使得在上芯片11的侧面与密封树脂31之间形成间隙111。
通过上述制造过程,通过涂布于上芯片11的侧面的脱模剂101防止形成在浸透到上芯片11与下芯片12之间的凸块21中的密封树脂31的下芯片12上的填角形部分粘附,使得在脱模剂101与上芯片11的侧面之间设置有间隙111。因此,如参考图1描述的,由于与填角形密封树脂31的干燥相关联的收缩导致的压力的产生得到抑制,使得上芯片11和下芯片12的翘曲得到防止。
<第二变型>
至此描述了半导体器件的配置实例,在该配置实例中,通过将脱模剂101涂布至上芯片11的侧面以防止粘附密封树脂31来抑制由于填角形密封树脂31产生的压力。然而,间隙111可以设置在密封树脂31的任何部分上,只要在上芯片11的侧面与下芯片12的上表面之间不会由于填角形密封树脂31的收缩而产生压力。因此,例如,还可以将脱模剂101涂布至下芯片12的上表面并且配置为如图6所示的间隙111设置在填角形密封树脂31的底面与下芯片12的上表面之间。
<第二制造过程>
接下来参考图7中的流程图描述图6中的半导体器件的制造过程。
在步骤S51,脱模剂101涂布于下芯片12上的设置凸块21的区域周围的区域,该区域不与上芯片11相对。
在步骤S52,上芯片11和下芯片12通过凸块21电气且机械地连接至彼此。
在步骤S53,密封树脂31涂布至下芯片12的上表面以及脱模剂101上,浸透到凸块21中,并且进一步干燥以固化为填角形状。
在步骤S54,通过涂布于下芯片12的上表面的脱模剂101防止粘附涂布的密封树脂31,使得间隙111形成在如图6所示的下芯片12的上表面上的不与上芯片11相对的区域与从凸块21突出为填角形状的密封树脂31之间。
通过上述制造过程,通过涂布于上芯片11下面的下芯片12的上表面的脱模剂101,防止粘附浸透到上芯片11与下芯片12之间的凸块21的形成在密封树脂31的下芯片12上的填角形部分,使得在脱模剂101与填角形密封树脂31之间设置有间隙111。因此,如参考图6描述的,由于与填角形密封树脂31的干燥相关联的收缩导致的压力的产生得到抑制,使得上芯片11和下芯片12的翘曲得到防止。
<第三变型>
至此描述了通过将脱模剂101涂布在上芯片11的侧面上和下芯片12的上表面上来形成间隙111的实例。然而,只要间隙111形成为抑制由于当填角形密封树脂31固化时导致的压力产生,另一配置也是可行的;例如,还可以在填角形密封树脂31的任何部分上设置涂布脱模剂101的隔板,并且在密封树脂31固化之后去除隔板,因此形成间隙111。
更详细地,例如,如在图8的上部分中示出的,粘附整个表面(或仅与密封树脂31接触的一部分)被涂布脱模剂101的隔板131以覆盖上芯片11的侧面并且此后涂布密封树脂31以固化。然后,在密封树脂31完全固化之前在附图中如图8的下部分中示出的箭头指示的方向上去除隔板131,因此形成间隙111。
另外,在该情况下,当密封树脂31干燥并且固化时去除隔板131,使得隔板还可以由链烷烃(paraffin,石蜡)等形成,例如,在密封树脂31干燥并且固化时逐渐蒸发(或者升华)并且因此形成间隙111。
<第三制造方法>
接下来参考图9中的流程图描述图8中的半导体器件的制造过程。
在步骤S71,整个表面(或者仅与密封树脂31接触的部分)被涂布脱模剂101的隔板131设置在上芯片11的侧面上。
在步骤S72,上芯片11和下芯片12通过凸块21电气且机械地连接至彼此。
在步骤S73,密封树脂31涂布于下芯片12的上表面和脱模剂101上,浸透到凸块21中,并且进一步干燥以固化为填角形状。
在步骤S74,隔板131在密封树脂31完全固化之前去除。根据此,密封树脂31涂布为如在图8中示出的间隙111形成在上芯片11的侧面与密封树脂31之间。
通过上述制造过程,间隙111设置在浸透到上芯片11与下芯片12之间的凸块21中的密封树脂31的形成在下芯片12上填角形突出部分与上芯片11的侧面之间。因此,如参考图8描述的,由于与填角形密封树脂31的干燥相关联的收缩导致的压力的产生得到抑制,使得上芯片11和下芯片12的翘曲得到防止。
另外,虽然至此描述了这样的实例,在该实例中,在隔板131粘附至上芯片11的侧面的状态下,密封树脂31涂布于上芯片11与下芯片12之间,隔板131还可以设置在形成凸块21的区域周围的上表面上。在该情况下,在附图的水平方向上去除隔板131并且在填角形密封树脂31与下芯片12之间设置间隙111,如在图6中示出的情况下。
而且,隔板131优选地设置为可以抑制由于与形成在上芯片11的侧面与下芯片12的上表面之间的填角形密封树脂31的固化相关联的收缩产生的压力。因此,如在图10的上部分中示出的,例如,还可以以相对于由于形成为填角形状的密封树脂31产生的压力的方向成预定角度的方向上设置隔板131,此后涂布密封树脂31,并且当密封树脂干燥以固化时,如在图10的下部分中示出的去除隔板131,因此形成间隙111。
<第四变型>
至此描述了相对于在填角形状的密封树脂31被干燥以固化时产生压力的方向成预定角度形成一个间隙111的实例。然而,设置间隙111使得压力没有产生足够了,使得不仅可以设置一个而且多个间隙111;例如,脱模剂101可以涂布于下芯片12的设置凸块21的区域周围的上表面并且脱模剂101可以涂布于上芯片11的上表面和侧面,如在图11中示出的。
通过以这种方式配置,当涂布密封树脂31时,间隙111设置在形成为填角形状的密封树脂31与上芯片11的侧面之间,并且间隙111还设置在密封树脂31与下芯片12的上表面之间。因此,由于与密封树脂31的干燥相关联的收缩导致的压力的产生得到抑制,使得上芯片11和下芯片12的翘曲得到抑制。
<第五变型>
至此描述了脱模剂101涂布于上芯片11的上表面和侧面并且脱模剂101进一步涂布于下芯片12的上表面,凸块21周围的区域被定位的实例。然而,压力的产生得到抑制足够了,使得压力的产生可以通过避免密封树脂31形成为填角形状得到抑制。
就是说,例如,如在图12中示出的,脱模剂101涂布于上芯片11的上表面和侧面并且凹槽151形成在下芯片12的上表面上的其中设置凸块21的区域周围,使得没有浸透到凸块21中的密封树脂31在凹槽151中流动。以这种方式,间隙111形成在密封树脂31与上芯片11的侧面之间并且密封树脂31没有形成为填角形状,使得上芯片11的侧面与下芯片12的上表面之间产生的压力得到抑制,并且因此,上芯片11和下芯片12的翘曲得到抑制。
<第六变型>
虽然至此描述了一个上芯片11堆叠在下芯片12上的实例,间隙111优选形成为同样抑制多个芯片堆叠在下芯片12上的配置中的由于与密封树脂31的干燥和固化相关联的收缩产生的压力。
就是说,例如,当通过凸块21堆叠上芯片的多层基板171通过凸块21堆叠在下芯片12上时,如在图13的上部分中示出的,脱模剂101在下芯片12上涂布在凸块21的周围并且此后涂布密封树脂31以浸透到多层基板171的最低部分上的凸块21中。以这种方式,间隙111形成在下芯片12的上表面上的凸块21周围的区域与填角形密封树脂31之间。
因此,可以抑制由于与密封树脂31的干燥和固化相关联的收缩导致的压力的产生,使得可以抑制下芯片12的翘曲。就是说,图13的上部分中的半导体器件具有与图6中的半导体器件相似的功能作用。
另外,如在图13的中间部分中示出的,当单个上芯片11和多层基板171堆叠在下芯片12上时,还可以将脱模剂101涂布至上芯片11未堆叠在下芯片12上的相邻区域中的堆叠多层基板171的区域周围的区域,并且将脱模剂101涂布至上芯片11的不与多层基板171相邻的上表面和侧面。
通过以这种方式配置,可以抑制如在图13的上部分中的半导体器件中的压力的产生,如在图13的中间部分中的右端中示出的。另外,如在图13的中间部分中的左端中示出的,可以获取与图2或图3相似的作用。
而且,对于图13的中间部分的左端,例如,通过将脱模剂31涂布至下芯片12的上表面上的不与多层基板171相邻的区域,如在图13的下部分中示出的,在下芯片12的上表面与密封树脂31之间可以形成间隙111,使得可以获取与图6中的半导体器件相似的作用。
应当注意,在图13中的情况下,也如图10所示,可以相对于通过密封树脂31产生的压力的方向在预定方向上形成隔板131并且涂布密封树脂31,并且此后去除隔板131以形成间隙111。另外,在图13的下部分中,附图的左侧上的上芯片11可以通过凸块21堆叠多个上芯片11获取。而且,当多个上芯片11、多个多层基板171等在相同的下芯片12上通过凸块21连接时,诸如处理器和存储器的各种配置可以用作上芯片11和多层基板171的功能。例如,通过设置处理器和存储器在相同的下芯片12上连接,可以减少布置距离,并且因此,可以实现低阻抗,使得可以降低加热温度并且提高处理速度。
如上所述,在本技术中,相对于压力产生的方向成预定角度的间隙形成在上芯片的侧面上的填角形密封树脂上或者下芯片的除与上芯片相对的区域以外的区域,使得上芯片和下芯片的翘曲减小,上芯片和下芯片的与翘曲相关联的裂纹的出现得到抑制,并且可以实现具有更高可靠性的半导体器件。
另外,可以抑制在下芯片上没有形成凹陷部分或者凹槽的情况下出现翘曲,使得由于抑制翘曲而降低半导体器件的强度得到抑制。
而且,可以在不考虑密封树脂的材料的情况下抑制翘曲。
应注意,本技术的实施方式并不局限于上述实施方式,并且在不背离本技术的范围的情况下,可做出各种变形。
另外,上述流程图中描述的每个步骤可通过一个设备执行或通过多个设备以共享方式来执行。
此外,当在一个步骤中包括多个处理时,包括在一个步骤中的多个处理可通过一个设备执行或通过多个设备以共享方式来执行。
应注意,本技术另外可以具有以下配置。
(1)一种半导体器件,包括:
上半导体芯片;
下半导体芯片;
凸块,将上半导体芯片连接至下半导体芯片;
密封树脂,保护凸块;以及
间隙,形成在从密封树脂的存在凸块的区域突出的填角形区域与上半导体芯片的侧面和下半导体芯片的上表面中的任一个之间。
(2)根据(1)的半导体器件,其中,
间隙通过如下步骤形成:在涂布密封树脂之前,在从当涂布密封树脂时存在凸块的区域突出的填角形区域与上半导体芯片的侧面和下半导体芯片的上表面中的任一个之间的位置中布置隔板、涂布密封树脂、并且此后去除隔板。
(3)根据(2)的半导体器件,其中,
隔板是与密封树脂接触的部分被涂布脱模剂的板状构件或者在密封树脂被干燥时通过热蒸发或者升华的材料形成的板状构件。
(4)根据(1)的半导体器件,其中,
间隙形成在上半导体芯片的侧面与填角形密封树脂之间。
(5)根据(4)的半导体器件,其中,
脱模剂涂布于上半导体芯片的侧面,并且
当通过涂布于上半导体芯片的侧面的脱模剂从上半导体芯片的侧面释放填角形密封树脂时形成间隙。
(6)根据(5)的半导体器件,其中,
除了上半导体芯片的侧面,脱模剂还涂布于上表面。
(7)根据(1)的半导体器件,其中,
间隙形成在下半导体芯片的除与上半导体芯片相对的区域以外的区域的上表面与填角形密封树脂之间。
(8)根据(7)的半导体器件,其中,
脱模剂涂布于下半导体芯片的除与上半导体芯片相对的区域以外的区域中的上表面,并且
当填角形密封树脂通过涂布于下半导体芯片的除与上半导体芯片相对的区域以外的区域的上表面的脱模剂从下半导体芯片的除与上半导体芯片相对的区域以外的区域的上表面释放时形成间隙。
(9)根据(1)的半导体器件,其中,
多个上半导体芯片在彼此通过凸块连接并且通过凸块连接至下半导体芯片的状态下堆叠,并且
间隙形成在从存在凸块的区域突出的填角形密封树脂与多个堆叠的上半导体芯片的侧面与下半导体芯片的上表面中的任一个之间。
(10)根据(1)的半导体器件,其中,
通过堆叠多个上半导体芯片获得的第一配置以及由上半导体芯片形成的第二配置在相邻位置处通过凸块连接至下半导体芯片,第二配置不同于第一配置,并且
间隙形成在第一配置和第二配置彼此不相邻的区域中、形成在从存在凸块的区域突出的填角形密封树脂与第一配置的侧面和下半导体芯片的上表面中的任一个之间、以及在密封树脂与第二配置的侧面和下半导体芯片的上表面中的任一个之间。
(11)一种制造半导体器件的方法,半导体器件包括:
上半导体芯片;
下半导体芯片;
凸块,将上半导体芯片连接至下半导体芯片;
密封树脂,保护凸块;以及
间隙,形成在从密封树脂的存在凸块的区域突出的填角形区域与上半导体芯片的侧面与下半导体芯片的上表面中的任一个之间,其中,
在涂布密封树脂之前执行形成间隙的处理。
(12)根据(11)的制造半导体器件的方法,其中,
形成间隙的处理是如下处理:在从当涂布密封树脂时存在凸块的区域突出的填角形区域与上半导体芯片的侧面和下半导体芯片的上表面中的任一个之间的位置中布置隔板,并且
在涂布密封树脂之后去除隔板。
(13)根据(12)的制造半导体器件的方法,其中,
隔板是与密封树脂接触的部分被涂布脱模剂的板状构件或者在密封树脂被干燥时通过热蒸发或者升华的材料形成的板状构件。
(14)根据(11)的制造半导体器件的方法,其中,
形成间隙的处理是将脱模剂涂布至上半导体芯片的侧面的处理。
(15)根据(11)的制造半导体器件的方法,其中,
形成间隙的处理是将脱模剂涂布至下半导体芯片的不与上半导体芯片相对的区域中的上表面的处理。
符号说明
11 上芯片、12 下芯片、21 凸块、31 密封树脂、101 脱模剂、111 间隙、131 隔板、151 凹槽、171 多层基板。
Claims (15)
1.一种半导体器件,包括:
上半导体芯片;
下半导体芯片;
凸块,将所述上半导体芯片连接至所述下半导体芯片;
密封树脂,保护所述凸块;以及
间隙,形成在填角形区域与所述上半导体芯片的侧面和所述下半导体芯片的上表面中的任一个之间,所述填角形区域从所述密封树脂的存在所述凸块的区域突出。
2.根据权利要求1所述的半导体器件,其中,
所述间隙通过如下步骤形成:在涂布所述密封树脂之前在从当涂布所述密封树脂时存在所述凸块的区域突出的所述填角形区域与所述上半导体芯片的侧面和所述下半导体芯片的上表面中的任一个之间的位置中布置隔板、涂布所述密封树脂、并且此后去除所述隔板。
3.根据权利要求2所述的半导体器件,其中,
所述隔板是与所述密封树脂接触的部分被涂布脱模剂的板状构件或者在所述密封树脂被干燥时通过热蒸发或者升华的材料形成的板状构件。
4.根据权利要求1所述的半导体器件,其中,
所述间隙形成在所述上半导体芯片的侧面与填角形密封树脂之间。
5.根据权利要求4所述的半导体器件,其中,
脱模剂涂布于所述上半导体芯片的侧面,并且
当通过涂布于所述上半导体芯片的侧面的所述脱模剂从所述上半导体芯片的侧面释放所述填角形密封树脂时形成所述间隙。
6.根据权利要求5所述的半导体器件,其中,
除了所述上半导体芯片的侧面,所述脱模剂还涂布于上表面。
7.根据权利要求1所述的半导体器件,其中,
所述间隙形成在所述下半导体芯片的除与所述上半导体芯片相对的区域以外的区域中的上表面与填角形密封树脂之间。
8.根据权利要求7所述的半导体器件,其中,
脱模剂涂布于所述下半导体芯片的除与所述上半导体芯片相对的区域以外的区域中的上表面,并且
当所述填角形密封树脂通过涂布于所述下半导体芯片的除与所述上半导体芯片相对的区域以外的区域中的上表面的所述脱模剂而从所述下半导体芯片的除与所述上半导体芯片相对的区域以外的区域中的上表面释放时形成所述间隙。
9.根据权利要求1所述的半导体器件,其中,
多个所述上半导体芯片在通过所述凸块彼此连接并且通过所述凸块连接至所述下半导体芯片的状态下堆叠,并且
所述间隙形成在从存在所述凸块的区域突出的填角形密封树脂与多个堆叠的所述上半导体芯片的侧面和所述下半导体芯片的上表面中的任一个之间。
10.根据权利要求1所述的半导体器件,其中,
通过堆叠多个所述上半导体芯片获取的第一配置以及由所述上半导体芯片形成的第二配置在相邻位置处通过所述凸块连接至所述下半导体芯片,所述第二配置不同于所述第一配置,并且
所述间隙形成在所述第一配置和所述第二配置彼此不相邻的区域中、形成在从存在所述凸块的区域突出的填角形密封树脂与所述第一配置的侧面和所述下半导体芯片的上表面中的任一个之间、以及在所述密封树脂与所述第二配置的侧面和所述下半导体芯片的上表面中的任一个之间。
11.一种制造半导体器件的方法,所述半导体器件包括:
上半导体芯片;
下半导体芯片;
凸块,将所述上半导体芯片连接至所述下半导体芯片;
密封树脂,保护所述凸块;以及
间隙,形成在从所述密封树脂的存在所述凸块的区域突出的填角形区域与所述上半导体芯片的侧面和所述下半导体芯片的上表面中的任一个之间,其中,所述方法包括
在涂布所述密封树脂之前执行形成所述间隙的处理。
12.根据权利要求11所述的制造半导体器件的方法,其中,
形成所述间隙的处理是如下处理:在从当涂布所述密封树脂时存在所述凸块的区域突出的所述填角形区域与所述上半导体芯片的侧面和所述下半导体芯片的上表面中的任一个之间的位置中布置隔板,并且
在涂布所述密封树脂之后去除所述隔板。
13.根据权利要求12所述的制造半导体器件的方法,其中,
所述隔板是与所述密封树脂接触的部分被涂布脱模剂的板状构件或者在所述密封树脂被干燥时通过热蒸发或者升华的材料形成的板状构件。
14.根据权利要求11所述的制造半导体器件的方法,其中,
形成所述间隙的处理是将脱模剂涂布至所述上半导体芯片的侧面的处理。
15.根据权利要求11所述的制造半导体器件的方法,其中,
形成所述间隙的处理是将脱模剂涂布至所述下半导体芯片的不与所述上半导体芯片相对的区域中的上表面的处理。
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US10014234B2 (en) | 2016-12-02 | 2018-07-03 | Globalfoundries Inc. | Semiconductor device comprising a die seal including long via lines |
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Citations (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0766242A (ja) * | 1993-08-20 | 1995-03-10 | Internatl Business Mach Corp <Ibm> | 電子素子アセンブリおよび再加工方法 |
JPH09172110A (ja) * | 1995-12-21 | 1997-06-30 | Toshiba Corp | 半導体装置 |
US20020090162A1 (en) * | 2001-01-11 | 2002-07-11 | Toyoki Asada | Electronic device and optical transmission module |
JP2003100960A (ja) * | 2001-09-19 | 2003-04-04 | Keihin Corp | Bgaパッケージ実装構造とその製造方法 |
JP2005302750A (ja) * | 2004-04-06 | 2005-10-27 | Fujitsu Ltd | 超音波フリップチップ実装方法 |
WO2007015683A1 (en) * | 2005-08-04 | 2007-02-08 | Infineon Technologies Ag | An integrated circuit package and a method for forming an integrated circuit package |
CN100435297C (zh) * | 2003-09-30 | 2008-11-19 | 松下电器产业株式会社 | 半导体装置及其制造方法 |
JP2009026791A (ja) * | 2007-07-17 | 2009-02-05 | Denso Corp | モールドパッケージおよびその製造方法 |
JP2009070898A (ja) * | 2007-09-11 | 2009-04-02 | Nec Corp | 部品実装用基板、電子装置及び部品実装方法 |
CN101529584A (zh) * | 2006-10-19 | 2009-09-09 | 松下电器产业株式会社 | 半导体元件的安装结构体及半导体元件的安装方法 |
JP2010050308A (ja) * | 2008-08-22 | 2010-03-04 | Casio Hitachi Mobile Communications Co Ltd | 電子部品の接着方法、回路基板、及び電子機器 |
CN101960578A (zh) * | 2008-04-18 | 2011-01-26 | 松下电器产业株式会社 | 倒装芯片安装方法和倒装芯片安装装置及其所使用的工具保护膜 |
JP2011119381A (ja) * | 2009-12-02 | 2011-06-16 | Nec Corp | 半導体装置の実装構造及び実装方法 |
JP2012028443A (ja) * | 2010-07-21 | 2012-02-09 | Denso Corp | 半導体装置および半導体装置の製造方法 |
JP2012238702A (ja) * | 2011-05-11 | 2012-12-06 | Hitachi Chem Co Ltd | 半導体装置の製造方法、及び半導体ウェハ積層体の製造方法 |
CN103137500A (zh) * | 2011-11-28 | 2013-06-05 | 尔必达存储器株式会社 | 制造半导体器件的方法 |
CN102047404B (zh) * | 2008-12-16 | 2013-07-10 | 松下电器产业株式会社 | 半导体装置和倒装芯片安装方法及倒装芯片安装装置 |
TW201421621A (zh) * | 2012-10-31 | 2014-06-01 | 3M Innovative Properties Co | 底部塡充組合物及半導體器件及其製造方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5864178A (en) | 1995-01-12 | 1999-01-26 | Kabushiki Kaisha Toshiba | Semiconductor device with improved encapsulating resin |
US6570245B1 (en) * | 2000-03-09 | 2003-05-27 | Intel Corporation | Stress shield for microelectronic dice |
JP2003092312A (ja) * | 2001-01-11 | 2003-03-28 | Hitachi Ltd | 電子装置及び光伝送モジュール |
WO2012153846A1 (ja) | 2011-05-11 | 2012-11-15 | 日立化成工業株式会社 | 半導体装置の製造方法、半導体素子付き半導体ウェハの製造方法、接着剤層付き半導体ウェハの製造方法及び半導体ウェハ積層体の製造方法 |
JP2012238704A (ja) * | 2011-05-11 | 2012-12-06 | Hitachi Chem Co Ltd | 半導体装置の製造方法、接着剤層付き半導体ウェハの製造方法、半導体素子付き半導体ウェハの製造方法、及び半導体ウェハ積層体の製造方法 |
-
2015
- 2015-06-16 WO PCT/JP2015/067260 patent/WO2015198911A1/ja active Application Filing
- 2015-06-16 CN CN201580032469.6A patent/CN106415826A/zh active Pending
- 2015-06-16 US US15/316,206 patent/US10553457B2/en active Active
- 2015-06-16 JP JP2016529356A patent/JP6694599B2/ja not_active Expired - Fee Related
Patent Citations (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0766242A (ja) * | 1993-08-20 | 1995-03-10 | Internatl Business Mach Corp <Ibm> | 電子素子アセンブリおよび再加工方法 |
JPH09172110A (ja) * | 1995-12-21 | 1997-06-30 | Toshiba Corp | 半導体装置 |
US20020090162A1 (en) * | 2001-01-11 | 2002-07-11 | Toyoki Asada | Electronic device and optical transmission module |
JP2003100960A (ja) * | 2001-09-19 | 2003-04-04 | Keihin Corp | Bgaパッケージ実装構造とその製造方法 |
CN100435297C (zh) * | 2003-09-30 | 2008-11-19 | 松下电器产业株式会社 | 半导体装置及其制造方法 |
JP2005302750A (ja) * | 2004-04-06 | 2005-10-27 | Fujitsu Ltd | 超音波フリップチップ実装方法 |
WO2007015683A1 (en) * | 2005-08-04 | 2007-02-08 | Infineon Technologies Ag | An integrated circuit package and a method for forming an integrated circuit package |
CN101529584A (zh) * | 2006-10-19 | 2009-09-09 | 松下电器产业株式会社 | 半导体元件的安装结构体及半导体元件的安装方法 |
JP2009026791A (ja) * | 2007-07-17 | 2009-02-05 | Denso Corp | モールドパッケージおよびその製造方法 |
JP2009070898A (ja) * | 2007-09-11 | 2009-04-02 | Nec Corp | 部品実装用基板、電子装置及び部品実装方法 |
CN101960578A (zh) * | 2008-04-18 | 2011-01-26 | 松下电器产业株式会社 | 倒装芯片安装方法和倒装芯片安装装置及其所使用的工具保护膜 |
JP2010050308A (ja) * | 2008-08-22 | 2010-03-04 | Casio Hitachi Mobile Communications Co Ltd | 電子部品の接着方法、回路基板、及び電子機器 |
CN102047404B (zh) * | 2008-12-16 | 2013-07-10 | 松下电器产业株式会社 | 半导体装置和倒装芯片安装方法及倒装芯片安装装置 |
JP2011119381A (ja) * | 2009-12-02 | 2011-06-16 | Nec Corp | 半導体装置の実装構造及び実装方法 |
JP2012028443A (ja) * | 2010-07-21 | 2012-02-09 | Denso Corp | 半導体装置および半導体装置の製造方法 |
JP2012238702A (ja) * | 2011-05-11 | 2012-12-06 | Hitachi Chem Co Ltd | 半導体装置の製造方法、及び半導体ウェハ積層体の製造方法 |
CN103137500A (zh) * | 2011-11-28 | 2013-06-05 | 尔必达存储器株式会社 | 制造半导体器件的方法 |
TW201421621A (zh) * | 2012-10-31 | 2014-06-01 | 3M Innovative Properties Co | 底部塡充組合物及半導體器件及其製造方法 |
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US20170162404A1 (en) | 2017-06-08 |
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