CN105720034B - 引线框架、半导体装置 - Google Patents

引线框架、半导体装置 Download PDF

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Publication number
CN105720034B
CN105720034B CN201510882130.7A CN201510882130A CN105720034B CN 105720034 B CN105720034 B CN 105720034B CN 201510882130 A CN201510882130 A CN 201510882130A CN 105720034 B CN105720034 B CN 105720034B
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Prior art keywords
lead
order difference
difference part
terminal
semiconductor device
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Chinese (zh)
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CN105720034A (zh
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笠原哲一郎
坂井直也
小林秀基
大串正幸
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Shinko Electric Co Ltd
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Shinko Electric Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • H01L23/49551Cross section geometry characterised by bent parts
    • H01L23/49555Cross section geometry characterised by bent parts the bent parts being the outer leads
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/4952Additional leads the additional leads being a bump or a wire
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  • Physics & Mathematics (AREA)
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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
CN201510882130.7A 2014-12-19 2015-12-03 引线框架、半导体装置 Active CN105720034B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014-257463 2014-12-19
JP2014257463A JP6325975B2 (ja) 2014-12-19 2014-12-19 リードフレーム、半導体装置

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CN105720034A CN105720034A (zh) 2016-06-29
CN105720034B true CN105720034B (zh) 2019-07-05

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US (1) US9698084B2 (enrdf_load_stackoverflow)
JP (1) JP6325975B2 (enrdf_load_stackoverflow)
KR (1) KR102452097B1 (enrdf_load_stackoverflow)
CN (1) CN105720034B (enrdf_load_stackoverflow)
TW (1) TWI668826B (enrdf_load_stackoverflow)

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JP6325975B2 (ja) * 2014-12-19 2018-05-16 新光電気工業株式会社 リードフレーム、半導体装置
JP6577373B2 (ja) * 2016-01-18 2019-09-18 新光電気工業株式会社 リードフレーム及びその製造方法、半導体装置
JP6788509B2 (ja) * 2017-01-17 2020-11-25 株式会社三井ハイテック リードフレームの製造方法およびリードフレーム
JP6661565B2 (ja) * 2017-03-21 2020-03-11 株式会社東芝 半導体装置及びその製造方法
DE102017120747B4 (de) * 2017-09-08 2020-07-30 Infineon Technologies Austria Ag SMD-Gehäuse mit Oberseitenkühlung und Verfahren zu seiner Bereitstellung
RU180407U1 (ru) * 2018-02-06 2018-06-13 Закрытое акционерное общество "ГРУППА КРЕМНИЙ ЭЛ" Выводная рамка корпуса интегральной микросхемы
DE102018217659B4 (de) 2018-10-15 2022-08-04 Vitesco Technologies GmbH Anordnung und Verfahren zur Herstellung einer elektrisch leitfähigen Verbindung zwischen zwei Substraten
JP7271337B2 (ja) 2019-06-27 2023-05-11 新光電気工業株式会社 電子部品装置及び電子部品装置の製造方法
JP7467214B2 (ja) * 2020-04-22 2024-04-15 新光電気工業株式会社 配線基板、電子装置及び配線基板の製造方法
KR102514564B1 (ko) * 2021-06-28 2023-03-29 해성디에스 주식회사 홈이 형성된 리드를 포함하는 리드 프레임
JP2023030665A (ja) * 2021-08-23 2023-03-08 株式会社ディスコ パッケージ基板、パッケージ基板の加工方法及びパッケージチップ
CN114121853B (zh) * 2022-01-27 2022-05-24 深圳中科四合科技有限公司 大尺寸芯片适配小尺寸封装体的封装结构

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JP3691790B2 (ja) 2001-12-27 2005-09-07 株式会社三井ハイテック 半導体装置の製造方法及び該方法によって製造された半導体装置
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