CN105206537A - 晶片封装环境中制作ai/ge键合的方法及由其生产的产品 - Google Patents

晶片封装环境中制作ai/ge键合的方法及由其生产的产品 Download PDF

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CN105206537A
CN105206537A CN201510523929.7A CN201510523929A CN105206537A CN 105206537 A CN105206537 A CN 105206537A CN 201510523929 A CN201510523929 A CN 201510523929A CN 105206537 A CN105206537 A CN 105206537A
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bonding
substrate wafer
wafer
mems
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史蒂文·S·纳西里
安东尼·弗朗西斯·小弗兰纳里
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Abstract

本申请涉及晶片封装环境中制作AI/GE键合的方法及由其生产的产品。一种通过铝锗键合(110)进行第一MEMS衬底(102)与第二CMOS衬底(104)之间的键合以形成坚固的电及机械触点的方法，所述第一MEMS衬底(102)包括至少一个经图案化的大致锗层，所述第二CMOS衬底(104)包括至少一个经图案化的大致铝层。

Description

晶片封装环境中制作AI/GE键合的方法及由其生产的产品
分案申请的相关信息
本案是分案申请。该分案的母案是申请日为2006年3月9日、申请号为200680015534.5、发明名称为“晶片封装环境中制作AI/GE键合的方法及由其生产的产品”的发明专利申请案。
相关申请案交叉参考
2003年10月20日所申请的标题为“X-YAxisDual-MassTuningForkGyroscopewithVerticallyIntegratedElectronicsandWafer-ScaleHermeticPackaging”的美国专利申请案第10/690,224号。
2003年10月20日所申请的标题为“MethodofMakinganX-YAxisDual-MassTuningForkGyroscopewithVerticallyIntegratedElectronicsandWafer-ScaleHermeticPackaging”的美国专利申请案第10/691,472号。
2004年2月2日所申请的标题为“VerticallyIntegratedMEMSStructure”的美国专利申请案第10/770,838号。
2004年2月2日所申请的标题为“VerticalIntegrationofaMEMSStructurewithElectronicsinaHermeticallySealedCavity”的美国专利申请案第10/771,135号。
技术领域
本发明一般来说涉及晶片键合，且更特定来说，涉及一种晶片封装环境中的键合方法及系统。
背景技术
MEMS技术已稳定发展了一段时间，且结果已设想并验证了用于几个应用的各个MEMS装置。MEMS技术是一种有吸引力的提供惯性传感器(例如，用于测量直线加速度的加速计及用于测量角速度的陀螺仪)的方法。MEMS惯性传感器通常包括挠性接附到所述装置剩余部分的检测质量块。依据详细装置设计，由致动器驱动及/或由传感器以各种方式传感所述检测质量块与所述装置的剩余部分之间的相对运动。其他MEMS应用包括光学应用(例如，活动反射镜)及RF应用(例如，RF开关及谐振器)。
由于MEMS制造技术通常是基于处理平面硅晶片，故可根据所述致动及/或惯性传感器中所实施的传感(或其他应用)是平面内或平面外(即，垂直)有效地分类MEMS装置。更具体来说，若装置的传感及/或致动全部是平面内，则其是“平面内”，否则其是“垂直”。因而，尽管制造难度趋向于增大，MEMS装置仍经历稳定的发展。
一种已用于制造垂直MEMS装置的方法是混合集成，其中单个地MEMS组合件的元件以形成所需垂直结构。举例而言，将隔离物接附到衬底，随后将可变形隔板接附到所述隔离物，从而提供在隔板与由所述隔离物控制的衬底之间具有间隔的垂直MEMS结构。美国专利第6,426,687号提供了关于此方法的详细信息。尽管混合集成可提供垂直MEMS装置，但成本往往会高，这是因为通常需要手动处理步骤，且因为通常对单个装置实施混合集成。因此，需要现有技术中未实现的低成本集成MEMS装置。
CMOS兼容性晶片-晶片键合对于晶片级封装极为合意。其应用已在各种不同技术中得到验证。然而，多数所述工艺一直受限于保护灵敏特征免于后处理处理(例如，锯割、芯片键合、测试、封装等)。
需要一种坚固的晶片级集成，其可允许同时进行晶片级封装且电互连极高且可开发大量新型、更小、低成本、富有特征的MEMS产品。下文说明常规键合方法及其问题。
有机或基于粘合剂的方法
诸如苯并环丁烯(BCB)、聚酰胺、光致抗蚀剂、可图案化RTV及其他的材料已经旋涂并用于形成晶片之间的永久连接。所述材料具有缺点，这是因为其是有机的，故其趋向于释气且因而不适合于形成气密封闭体，且同样其易于溶解或潮湿，其可导致与长期可靠性及装置性能漂移相关的问题。此外，其是绝缘材料且因而不能形成两个衬底之间的导电路径。
进行晶片-晶片键合的一种流行方法是通过使用熔结玻璃。熔结玻璃通常被丝网印刷于覆盖晶片上并回流以形成随后晶片-晶片键合的图案化玻璃界面。熔结玻璃通常具有近500℃的熔点且可在晶片-晶片对准粘合之后在具有受控环境的具体温度室中再熔融。熔结玻璃的主要用途提供覆盖衬底及MEMS的气密密封腔。在MEMS工业中熔结玻璃技术已被利用了数十年。数个主要缺点是熔结玻璃不提供MEMS与覆盖物之间的电互连，为实现气密密封界面，需要最少400微米的密封环宽度，此使小型MEMS装置(例如，谐振器或光学装置)远大于不使用其时。同样，丝网印刷的熔结玻璃固有地是具有数十微粒厚度及数微米不均匀性的厚膜工艺。
金属-金属键合
已通过铟-金、焊料-金、金-金等验证了CMOS兼容低共熔键合。为键合CMOS晶片，所有所述现有技术系统需要添加非标准层，例如镀敷欲添加到所述CMOS晶片的铅、铟、金等。尽管所述工艺能够形成气密密封及电界面，从而实现精细特征，但小间隙及晶片均匀性是极大的挑战且将导致收率损失。
有许多MEMS装置应用需要所述CMOS衬底之间的电机械界面及存在微米间隙且需要亚微米均匀性的MEMS衬底。多数镀敷工艺需要数十微米厚度的下层障壁金属化，且整个晶片的均匀性经测量为微米级。因此，使用此键合方法不可能指定所述MEMS与CMOS衬底之间的一个或两个微米间隙控制。
进行所述MEMS与CMOS衬底之间的高密度可靠电触点的能力可以是非常有益的且可提供有许多附加功能性、智能电子器件、更小尺寸及更低成本的全新一代的MEMS装置。最后，基于环境考虑，提供无铅合金是很重要的。
因此，需要一种提供克服上文所指出问题的晶片键合的系统及方法。所述系统及方法应易于实施、节省成本且适合于现有键合工艺。本发明能满足这种需要。
发明内容
本发明揭示一种通过使用铝锗低共熔合金键合两个衬底以形成坚固的电及机械触点的方法。铝锗键合具有下述唯一属性组合：(1)其可形成气密密封；(2)其可用于形成两个衬底之间的导电路径；(3)其可经图案化以便定位所述导电路径；(4)可与用作标准铸造CMOS工艺用铝进行所述键合；(5)此工艺与随着后处理而完全地制造的CMOS晶片兼容；(6)此工艺可提供高密度电互连；且(7)此工艺是高度可控的且提供两个衬底之间的最小间隙。此具有在不向所述CMOS晶片添加任何额外处理层的情况下允许晶片级键合或封装的显著优点。
附图说明
图1是根据本发明制造晶片级封装的方法的流程图。
图2A及2B是根据本发明的组合件的第一实施例的剖视图及俯视图。
图3A及3B是根据本发明的组合件的第二实施例的剖视图及俯视图。
图4图解实例性键合轮廓以实现正确Al/GE键合。
具体实施方式
一般来说，本发明涉及晶片键合，且更特定来说，涉及在MEMS装置与电衬底互连环境的晶片级封装中利用铝及锗进行键合的方法及系统。提供下述说明以使所属技术领域的技术人员能够制作并使用本发明，且是根据专利申请案及其要求所提供。所属技术领域的技术人员将容易地明了对本文所述较佳实施方案及一般原理及特征的各种修改。因而，本发明并不意欲被局限于所示的实施例，而应赋予其与本文所述的原理及特征相一致的最广泛的范畴。
图1是根据本发明制造晶片级封装的方法的流程图。所述方法包含：通过步骤12提供包括锗顶层的MEMS结构，且通过步骤14提供包括铝顶层的CMOS结构。最后，所述方法包含：通过步骤16将所述MEMS结构的所述顶层与所述CMOS结构的所述顶层键合。
下文说明根据本发明的较佳实施例。图2A及2B是根据本发明的组合件100的第一实施例的剖视图及俯视图。参照图2A中所示的实施例，将包括铝的标准铸造CMOS晶片104键合到包括锗的MEMS衬底102以提供铝/锗(Al/GE)键合110。在所述实施例中，空腔106位于衬底104中。CMOS衬底晶片104可以是任何具有图2B中所示经图案化的铝的衬底，其经设计以与MEMS衬底102面接以生产全功能产品。此外，多个铝触点116位于CMOS衬底104的顶部上，其通过互连107耦合到键合垫105。将通路107提供于键合垫105及铝触点116两者内以允许其电连接。例如，衬底104可仅包含金属层及用于提供到所述MEMS层电互连的互连的集合。此外，MEMS衬底102包括MEMS特征108以在MEMS衬底104上构建所述MEMS层，例如相应腔106。提供间隙控制支座111以提供MEMS衬底102距CMOS衬底104的精确间距。间隙控制支座111提供所述装置的密封环112。
图3A及3B是根据本发明的组合件的第二实施例的剖视图及俯视图。组合件200包括许多与图2的组合件100相同的元件且那些元件具有相同的参考编号。此外，组合件200具有穿过MEMS衬底102’及间隙控制支座111’的通路触点202以提供信号的电馈通。
衬底104的另一重要特征是多层金属化标准在CMOS铸造中的可用性，其中化学机械抛光氧化物以生产非常平坦的金属化层以适合于与所述MEMS层上所存在的锗一起形成Al/Ge低共熔合金。MEMS衬底102可以是硅晶片或装配有所有MEMS特征及功能(包括任何类型的经预处理特征)的硅晶片的组合。
在所述较佳实施例中，所述MEMS衬底(其上已图案化有所述锗)是经硼掺杂而具有0.006-0.02Ω-cm导电率的硅衬底。所述p+掺杂形成与键合后的铝锗低共熔混合物的欧姆接触。
现在参照下文更详细地说明所述键合层。
键合层
在较佳实施例中，铸造CMOS晶片的顶部金属层是Al∶Si∶Cu为97.5∶2∶0.5比例的混合物，且具有700nm的厚度，且位于使用CMP平民化的氧化物层上，所述CMP是0.5tm或更小几何形状的多数CMOS工艺的标准处理步骤。在较佳实施例中，所述MEMS上的键合层是在标准真空溅镀沉积系统中沉积的500nm锗，其经正确地图案化以匹配经图案化以进行键合的相应铝。
下文是根据本发明的设备及工艺的较佳实施例的示例。
所需设备
在(例如)由ElectronicVisionsGroup，Inc.或SussMicrotec，Inc.所供应的市售晶片键合机中实施所述键合。所述设备应满足如下标准并具有如下性能：(1)顶夹盘及底夹盘二者的温度控制到标称450℃；(2)环境压力控制到亚托(sub-tor)；(3)环境气体控制(通过吹扫线路)；(4)管供有4-3-5百分比的合成气体；(5)能够在所述晶片对上施加最小3000N的均匀力。
在所述较佳实施例中，所述晶片经预先清洁且然后在键合之前于兼容对准工具中对准。
键合前清洁
在所述较佳实施例中，在键合之前清洁所述CMOS晶片及所述MEMS晶片两者。假设两个晶片皆无任何光致抗蚀剂或来自先前处理步骤的其他外来杂质。通过如下步骤清洁所述晶片：(1)浸入去离子水中1.30秒；(2)浸入50∶1HF中13.0秒；(3)倾卸冲洗；及(4)标准旋转-漂洗-干燥工艺。
对准
在ElectronicVisions620晶片-晶片对准器中对准所述键合对。插入分离标志以在键合之前维持所键合对的分离。
键合
将所述经对准对传递到ElectronicVisions501键合机。所述机器的吹扫线路已管供有合成气体。在所述键合方法的冷却期之后，完成所述键合且无需进一步处理。图4中显示实现正确Al/Ge键合的实例性键合温度曲线图的示例。
各种及替代实施例的说明
替代实施例包括(例如)：(1)在所述锗上利用不同的材料以在随后MEMS处理期间保护所述锗；(2)采用不同的键合前清洁方法；(3)在未经对准的情况下实施所述键合；(4)可在不图案化所述铝及/或锗的情况下实施所述键合；(5)可在除所述键合前清洁外无任何附加处理的情况下键合所述CMOS晶片；(6)所述铝锗键合可经配置以不形成气密密封；(7)利用除MEMS晶片外的衬底(例如，简单覆盖晶片)；(8)所述MEMS衬底可包含除陀螺仪外的某物(例如，压力传感器或加速计)；(9)所述标准CMOS晶片的所述铝可包含不同配方的标准铝(2％硅、2％硅/1％铜等)。
另外，(10)可利用特定温度曲线图；(11)可使用合成气体来使触点表面脱氧；(12)可根据IC制造所使用的标准金属化利用铝；(13)可将铝衬底保持低于预定温度以防止铝及锗合金从所述衬底上的所述氧化物的完全浸出；(14)可使用受控环境(例如，合成气体)实施所述键合；(15)可使用低压键合力或高压键合力实施所述键合作为辅助用于/以辅助破坏氧化的铝以引发所述相互作用；(16)可在键合工艺之前预对准两个晶片；(17)可利用特殊清洁溶液来从两个表面清洁所述氧化物；(18)可通过溅射蚀刻清洁所述键合表面；(19)在MEMS处理期间可利用TiW薄层保护所述键合表面；(20)除更大浓度合成气体及更高力的键合外，可包括使用等离子体及/或其他原有清洁技术的键合前清洁；(21)可将所述锗沉积于不导电层(例如，二氧化硅)以形成绝缘触点。
可将所述锗沉积于已经掺杂的半导体衬底上以使所述衬底的所述铝与所述MEMS之间的所得触点是整流性的。所述衬底可以是经n型掺杂至0.02-0.05Ω-cm的硅衬底。
可将所述锗沉积于已经掺杂的半导体衬底上以便所述衬底的所述铝与所述MEMS之间的所得触点是欧姆性的。
本文揭示一种键合两个衬底之间的锗铝以形成坚固电及机械触点的方法及结构。铝锗键合具有下述唯一属性组合：(1)其可形成气密密封；(2)其可用于形成两个衬底之间的导电路径；(3)其可经图案化以便定位所述导电路径；(4)可与可用作标准铸造CMOS工艺的铝进行所述键合。此具有在不向所述CMOS晶片添加任何额外处理层的情况下允许晶片级键合或封装的显著优点。
尽管已根据所示实施例阐述了本发明，但所属技术领域的技术人员将容易地认识到，所述实施例可有若干变化且这些变化皆在本发明的精神及范围内。因此，所属技术领域的技术人员可在不违背随附权利要求书的精神及范围的情况下对本发明做许多修改。

Claims (7)

1.一种用于键合第一衬底晶片和第二衬底晶片的方法，经图案化的铝层设置在所述第一衬底晶片上，经图案化的锗层设置在所述第二衬底晶片上，所述方法包含：
将所述第一衬底晶片放置在第一夹盘中；
将所述第二衬底晶片放置在第二夹盘中；
将所述第一衬底晶片和所述第二衬底晶片对准；及
在所述经图案化的锗层和所述经图案化的铝层之间形成低共熔键合，其中通过在所述第一夹盘和所述第二夹盘上施加力且将温度从铝/锗键合的低共熔点升高到第二预定温度来形成所述低共熔键合，所述第二预定温度在450℃以下。
2.如权利要求1所述的方法，其中所述第一衬底晶片和所述第二衬底晶片的一者为覆盖晶片。
3.如权利要求1所述的方法，其中在所述第二衬底晶片和所述经图案化的锗层的一部分之间提供绝缘层。
4.如权利要求1所述的方法，包含使用氧化还原剂来使所述经图案化的铝层的键合表面以及所述经图案化的锗层的键合表面脱氧。
5.一种用于键合第一衬底晶片和第二衬底晶片的方法，铝层设置在所述第一衬底晶片上，锗层设置在所述第二衬底晶片上，所述方法包含：
将所述第一衬底晶片放置在第一夹盘中；
将所述第二衬底晶片放置在第二夹盘中；
将所述第一衬底晶片和所述第二衬底晶片对准；及
在所述锗层和所述铝层之间形成低共熔键合，其中通过在所述第一夹盘和所述第二夹盘上施加力且将温度升高到铝/锗键合的低共熔点以上来形成所述低共熔键合。
6.如权利要求5所述的方法，其中所述温度升高到不超过450℃。
7.如权利要求5所述的方法，其中所述第一衬底晶片和所述第二衬底晶片中的一者为覆盖晶片。
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