WO2011070625A1 - 半導体基板の接合方法およびmemsデバイス - Google Patents
半導体基板の接合方法およびmemsデバイス Download PDFInfo
- Publication number
- WO2011070625A1 WO2011070625A1 PCT/JP2009/006786 JP2009006786W WO2011070625A1 WO 2011070625 A1 WO2011070625 A1 WO 2011070625A1 JP 2009006786 W JP2009006786 W JP 2009006786W WO 2011070625 A1 WO2011070625 A1 WO 2011070625A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor substrate
- bonding
- layer
- aluminum
- containing layer
- Prior art date
Links
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
- B23K20/02—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating by means of a press ; Diffusion bonding
- B23K20/023—Thermo-compression bonding
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
- B23K20/16—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating with interposition of special material to facilitate connection of the parts, e.g. material for absorbing or producing gas
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
- B23K20/22—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating taking account of the properties of the materials to be welded
- B23K20/233—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating taking account of the properties of the materials to be welded without ferrous layer
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00269—Bonding of solid lids or wafers to the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2101/00—Articles made by soldering, welding or cutting
- B23K2101/36—Electric or electronic devices
- B23K2101/40—Semiconductor devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/01—Packaging MEMS
- B81C2203/0118—Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/29124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45025—Plural core members
- H01L2224/4503—Stacked arrangements
- H01L2224/45032—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83201—Compression bonding
- H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
- H01L2224/83805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01032—Germanium [Ge]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
Definitions
- the present invention relates to a semiconductor substrate bonding method in which two semiconductor substrates are eutectic bonded and a MEMS device formed by bonding the semiconductor substrates.
- a silicon wafer in which a MEMS structure is formed has a germanium layer
- a silicon wafer in which an integrated circuit is formed has an aluminum-containing layer.
- a method is known in which an eutectic alloy composed of germanium and aluminum is formed and fixed by pressing and heating the aluminum layer in a face-to-face state (see Patent Document 1).
- the bonding of the two semiconductor substrates is effective for a package such as an integrated circuit formed on each semiconductor substrate, but this package requires electrical continuity with an external circuit, and also has humidity, temperature,
- the purpose is to protect from the outside environment such as Chile. That is, since the bonding of the semiconductor substrate serves these purposes, a high sealing rate and bonding strength of the bonded portion are required.
- the weight ratio of the germanium layer to the aluminum-containing layer that forms the eutectic alloy is important for the high sealing rate and bonding strength of the bonded portion I found out that
- the present invention has been made in view of the above knowledge, and it is an object of the present invention to provide a semiconductor substrate bonding method that realizes bonding with high sealing rate and bonding strength, and a MEMS device formed by bonding. And
- an aluminum-containing layer containing aluminum as a main component and a germanium layer are interposed in contact between the bonding surface of the first semiconductor substrate and the bonding surface of the second semiconductor substrate,
- the weight ratio is preferably 33 wt% to 42 wt%.
- a 1st semiconductor substrate and a 2nd semiconductor substrate can be joined with a high sealing rate and joining strength (refer the test result mentioned later).
- the aluminum-containing layer and the germanium layer may be formed on any bonding surface of the first semiconductor substrate and the second semiconductor substrate. Furthermore, the aluminum-containing layer and the germanium layer may be formed on the bonding surface of the same semiconductor substrate or may be formed on the bonding surface of different semiconductor substrates.
- the film thickness of the germanium layer it is preferable to adjust the film thickness of the germanium layer so that all of the germanium layer and a part of the aluminum-containing layer in contact with the germanium layer form a eutectic alloy.
- the above weight ratio can be controlled with high accuracy, and bonding with a high sealing rate and high bonding strength can be performed efficiently.
- the aluminum-containing layer and the germanium layer are preferably formed on either the first semiconductor substrate or the second semiconductor substrate.
- the film-forming process before the said semiconductor substrate joining can be reduced, and a joining process can be simplified.
- the aluminum-containing layer has a predetermined width and is formed in a ring shape in plan view
- the germanium layer has one or more streaky layer portions formed in a ring shape in plan view on the aluminum-containing layer. It is preferable.
- the semiconductor substrates can be bonded with high sealing properties.
- the aluminum-containing layer is formed in a ring shape in plan view with a predetermined width
- the germanium layer is formed on the aluminum-containing layer in a ring shape in plan view. It is preferable to have a plurality of branch layer portions branched from the portion.
- the eutectic alloy formed by heating and pressing is easily fixed to the first semiconductor substrate, and the bonding strength High bonding can be performed.
- the aluminum-containing layer and the germanium layer are formed on the second semiconductor substrate, and pits into which the eutectic alloy generated by pressurization / heating enters are formed on the bonding surface of the first semiconductor substrate. It is preferable.
- the eutectic alloy in a molten state formed by heating and pressurizing in a vacuum enters the pit by a capillary phenomenon. For this reason, the eutectic alloy spreads over the pits. As a result, the eutectic alloy layer is formed so as to bite into the first semiconductor substrate, so that the bonding strength of the bonded portion can be increased.
- the pit formed in the first semiconductor substrate may be a plurality of holes formed intermittently or may be a slit-like groove formed continuously.
- the MEMS device of the present invention is a MEMS device formed by bonding by the above-described semiconductor substrate bonding method, wherein the first semiconductor substrate has a MEMS structure formed so as to be dug into the bonding surface side.
- the MEMS structure, the integrated circuit, and the external circuit have electrical continuity by bonding with a high sealing rate and bonding strength, and are protected from the external environment such as humidity, temperature, and dust.
- the MEMS device is preferably any one of an acceleration sensor, an angular velocity sensor, an infrared sensor, a pressure sensor, a magnetic sensor, and an acoustic sensor.
- an accurate acceleration sensor, angular velocity sensor, infrared sensor, pressure sensor, magnetic sensor, and acoustic sensor can be provided by an effective package.
- 1 is an external perspective view schematically showing a MEMS chip and a CMOS chip according to an embodiment.
- 1 is a perspective view schematically showing a MEMS device according to an embodiment. It is sectional drawing showing the film-forming arrangement
- a MEMS wafer having a large number of sensing units and a CMOS wafer having a large number of integrated circuits for controlling each sensing unit are opposed to each other by eutectic bonding with a metal.
- the formed MEMS sensor and the integrated circuit are opposed to each other in separate steps, and eutectic bonding is performed.
- this eutectic bonding uses wafer level package technology (WLP technology) in which the wafers are encapsulated in a lump and then separated into chips.
- WLP technology wafer level package technology
- the MEMS device is manufactured by such eutectic bonding.
- an acceleration sensor an angular velocity sensor, an infrared sensor, a pressure sensor, a magnetic sensor, and an acoustic sensor can be considered.
- FIG. 1A is an enlarged view of one piece of a MEMS wafer (not shown) in which a large number of sensing units 12 are formed in a matrix.
- the MEMS chip 10 which is this one piece for convenience.
- the MEMS chip 10 includes a substrate 11 made of silicon (Si), and a sensing unit 12 formed in the center of the substrate 11 by a microfabrication technique.
- the sensing unit 12 is formed so as to be dug in the center of the substrate 11 and is configured with elements such as an acceleration sensor, an angular velocity sensor, an infrared sensor, a pressure sensor, a magnetic sensor, and an acoustic sensor as described above.
- the substrate 11 is provided with a joint 30a having a square ring shape in plan view so as to surround the sensing unit 12.
- the sensing unit 12 and the bonding unit 30 a are reversed so that the sensing unit 12 and the bonding unit 30 a face the CMOS chip 20 described later, and are bonded to the CMOS chip 20.
- the joint portion 30a of the MEMS chip 10 is abutted against the joint portion 30b formed on the CMOS chip 20, and both are eutectic bonded by the metal layer formed on the joint portion 30b.
- the substrate 11 corresponds to a first semiconductor substrate referred to in the claims
- the sensing unit 12 corresponds to a MEMS structure referred to in the claims.
- FIG. 1B is an enlarged view of a single piece from a CMOS wafer (not shown) in which a large number of integrated circuits 22 are formed in a matrix.
- the CMOS chip 20 which is this one piece will be described.
- the CMOS chip 20 has a substrate 21 made of silicon and an integrated circuit 22 formed on the substrate 21 by a microfabrication technique (semiconductor manufacturing technique).
- a rectangular joint 30b in plan view is disposed so as to surround the circuit central portion 23 of the integrated circuit 22 that faces the sensing portion 12 of the MEMS chip 10 during eutectic bonding.
- the integrated circuit 22 controls the sensing unit 12 of the MEMS chip 10 and is connected to input / output signal lines from the outside.
- the integrated circuit 22 has an aluminum wiring, and as will be described in detail later, the aluminum-containing layer 31 formed when the aluminum wiring is formed becomes a part of the eutectic alloy at the time of bonding. That is, the joint portion 30b of the CMOS chip 20 is formed in substantially the same shape as the joint portion 30a of the MEMS chip 10 in plan view.
- the joint portion 30b of the CMOS chip 20 includes an aluminum-containing alloy that is a eutectic alloy on the substrate 11.
- a layer 31 is formed, and a germanium layer 32 which is a eutectic alloy is formed on the aluminum-containing layer 31 (for example, film formation by sputtering or vapor deposition technique).
- the substrate 21 corresponds to the second semiconductor substrate in the claims
- the bonding portion 30b corresponds to the bonding portion of the second semiconductor substrate in the claims.
- FIG. 2 shows a MEMS device 1 configured by dicing or breaking a MEMS wafer and a CMOS wafer after bonding (bonding bonding).
- the MEMS device 1 is configured by bonding a MEMS chip 10 and a CMOS chip 20 so that the sensing unit 12 and the circuit center part 23 face each other.
- the MEMS chip 10 MEMS wafer
- the CMOS chip 20 CMOS wafer
- Apply pressure As a result, the germanium layer 32 formed on the junction 30b of the CMOS chip 20 undergoes a eutectic reaction at the interface with the aluminum-containing layer 31, and an aluminum-germanium alloy (hereinafter referred to as eutectic alloy) is generated. .
- eutectic alloy aluminum-germanium alloy
- the molten eutectic alloy is pressed against and welded to the silicon surface of the bonding portion 30a, and is firmly bonded to obtain a strong bond.
- this eutectic bonding provides electrical continuity and high sealing performance between the substrates 11 and 21.
- the heating temperature at the time of bonding is preferably about 450 ° C. in consideration of thermal damage to the sensing unit 12 and the integrated circuit 22.
- the pressurization at the time of bonding may be performed from the CMOS chip 20 side or from both the MEMS chip 10 side and the CMOS chip 20 side. And after joining, each MEMS device 1 is manufactured through the separation process from the wafer state to each chip.
- FIG. 3 is an enlarged view taken along the line AA in FIG.
- the aluminum-containing layer 31 is uniformly formed on the bonding portion 30b of the CMOS chip 20 before the eutectic bonding.
- the germanium layer 32 on the aluminum-containing layer 31 is formed so that the outer end 32 a of the germanium layer 32 is set back inside the outer end 31 a of the aluminum-containing layer 31.
- no metal layer is formed on the joint 30a of the MEMS chip 10, and the silicon surface of the substrate 11 is exposed.
- the eutectic alloy layer 33 is formed between the substrate 11 and the substrate 21 by the bonding method described above, as shown in FIG. 5B, and the MEMS chip 10 and the CMOS chip 20 are eutectic bonded. Is done.
- pressurization and heating are appropriately controlled, and the portion of the aluminum-containing layer 31 that is not in contact with the germanium layer 32 remains without performing a eutectic reaction (residual portion 34).
- the germanium layer 32 is preferably formed in a thin film rather than the aluminum-containing layer 31 in order to cause a eutectic reaction efficiently.
- the film forming process after the formation of the sensing unit 12 can be simplified, and the structure of the sensing unit 12 that is a thin film is deformed. ⁇ Effects of film formation such as adhesion and damage can be avoided. Further, since the aluminum-containing layer 31 uses the aluminum wiring of the integrated circuit 22, the only metal film formation required for actual bonding is only germanium film formation on the bonding portion 30 b of the CMOS chip 20. It can be simplified.
- the joint portion 30 is disposed so as to surround the sensing portion 12 and the circuit center portion 23, and the eutectic alloy layer 33 is formed so as to be orthogonal to the inner and outer directions of the MEMS chip 10 and the CMOS chip 20 that face each other. Therefore, the MEMS chip 10 and the CMOS chip 20 can be bonded with high sealing performance and bonding strength.
- the aluminum-containing layer 31 and the germanium layer 32 may be formed at any of the junctions of the MEMS chip 10 and the CMOS chip 20, or may be formed at the junction of the same substrate or bonded to different substrates. The film may be formed on the part.
- the germanium layer 32 is formed so that the outer end 32a of the germanium layer 32 is set back to the inner side with respect to the outer end 31a of the aluminum-containing layer 31, the eutectic in a molten state by pressurization at the time of bonding. Even if the alloy spreads outward, the formed eutectic alloy is formed without protruding from the joint 30 and can prevent conduction to an undesired electrode, thereby improving device productivity (yield). Can do. When film formation can be performed with high accuracy, the film may be formed so that the outer end of the aluminum-containing layer 31 and the outer end of the germanium layer 32 are aligned.
- the weight ratio of the germanium layer 32 to the aluminum-containing layer 31 at the time of bonding will be described with reference to FIGS. 4 and 5.
- the heating temperature and the heating time are controlled together with the pressurization pressure so that all of the germanium layer 32 and a part of the aluminum-containing layer 31 undergo a eutectic reaction at the mutual bonding surfaces.
- the weight ratio of the germanium layer 32 to the aluminum-containing layer 31 is adjusted mainly by the ratio of the film thickness of the germanium layer 32 to the aluminum-containing layer 31. Accordingly, the germanium layer 32 and the portion of the aluminum-containing layer 31 that is in direct contact with the germanium layer 32 undergo a eutectic reaction, and a part of the aluminum-containing layer 31 remains as it is (see FIG. 3B).
- FIG. 4 and 5 show test results of eutectic bonding performed by changing the thickness of the germanium layer 32 as appropriate while setting the thickness of the aluminum-containing layer 31 to be constant (800 nm).
- FIG. 4 shows the film thickness of the aluminum-containing layer 31 and the germanium layer 32 formed before eutectic bonding, the weight ratio of the germanium layer 32 to the aluminum-containing layer 31, the sealing ratio and the shear strength of the bonded portion after eutectic bonding. This shows the relationship of (joining strength).
- FIG. 5 is a graph showing the relationship between the weight ratio of the germanium layer 32 to the aluminum-containing layer 31 and the sealing rate and shear strength (bonding strength) of the bonded portion after eutectic bonding.
- the sealing rate of the joint after eutectic bonding is about 50% or more.
- FIG. 4B shows that the joint strength after eutectic bonding (shear strength) is about 30 N or more when the weight ratio of the germanium layer 32 is between 27 wt% and 52 wt%. Yes.
- the sealing rate is 100%, and the shear strength (joint strength) is 41.6 N to 56.3 N (FIG. 4). reference).
- FIGS. 6 to 8 a modified example of the film formation arrangement of the aluminum-containing layer 31 and the germanium layer 32 according to this embodiment will be described.
- 6A shows a part of the joint 30b of the CMOS chip 20 before the eutectic bonding
- FIG. 6B shows a cross section of the joint 30 before the eutectic bonding (first modification).
- the aluminum-containing layer 31 is uniformly formed on the joint portion 30 b of the CMOS chip 20, while the germanium layer 32 is formed on the aluminum-containing layer 31 in a plurality of streaks. That is, the germanium layer 32 is composed of a plurality of concentric streaky layer portions 35 having a similar shape.
- FIG. 7 shows a second modification of the arrangement of the aluminum-containing layer 31 and the germanium layer 32 according to this embodiment.
- the aluminum-containing layer 31 is uniformly formed on the junction 30b of the CMOS chip 20 and is formed on the aluminum-containing layer 31 as in the first modification example.
- the formed germanium layer 32 is integrally formed of a single streaky layer portion 35 and a plurality of branch layer portions 36.
- the streaky layer portion 35 is formed in a square ring shape along the aluminum-containing layer 31 at the center in the width direction of the aluminum-containing layer 31.
- the plurality of branch layer portions 36 are formed so as to branch at right angles from the respective portions of the streaky layer portion 35 to both sides.
- the end portions of the germanium layer 32 are formed.
- the total area can be increased and strong eutectic bonding can be achieved.
- FIG. 8 shows a third modification of the arrangement of the aluminum-containing layer 31 and the germanium layer 32 according to this embodiment.
- the film forming arrangement of the third modification has a form in which the first modification and the second modification are combined. That is, in the third modification, the aluminum-containing layer 31 is uniformly formed on the joint portion 30b of the CMOS chip 20, and the germanium layer 32 formed on the aluminum-containing layer 31 has a plurality of streaky layer portions. 35 and a plurality of branch layer portions 36.
- the germanium layer 32 includes three concentric stripe-like layer portions 35 having a similar shape and a plurality of branch-like layer portions branched at right angles from the respective portions of the stripe-like layer portion 35 located in the middle. 36. Thereby, the MEMS chip 10 and the CMOS chip 20 can be bonded with higher sealing properties and bonding strength.
- the aluminum-containing layer 31 formed on the joint 30b of the CMOS chip 20 is composed of a plurality of aluminum annular layer portions 37.
- the plurality of aluminum annular layer portions 37 are formed in an annular shape in a plan view concentric with the joint portion 30b, and are disposed so as to be orthogonal to the inner and outer directions of the joint portion 30b.
- a plurality of annular germanium layers 32 are formed so as to fill the gaps between the plurality of aluminum annular layer portions 37.
- the plurality of germanium annular layer portions 38 are formed so as to contact in the vertical direction at the contact end portions 39 of the plurality of aluminum annular layer portions 37 and slightly overlap in the horizontal direction (multilayer portion 40). Yes.
- a plurality of pits 41 in which the substrate 11 is dug are formed in the joint portion 30a of the MEMS chip 10.
- the plurality of pits 41 are arranged so as to correspond to positions where the plurality of germanium annular layer portions 38 overlap with the plurality of aluminum annular layer portions 38 (multilayer portion 40), and are heated and pressurized in a molten state. These alloys are adapted to enter a plurality of pits 41.
- the plurality of pits 41 may be newly formed on the substrate 11 after the sensing unit 12 is formed, or a dig formed in the formation process of the sensing unit 12 may be used. Further, the pit 41 may be an intermittent hole shape or a continuous groove shape.
- FIG. 9C shows the joint after eutectic bonding.
- the molten eutectic alloy formed by heating penetrates into the plurality of pits 41 by capillary action in a vacuum by pressurization and spreads.
- the fixed eutectic alloy layer 33 is formed so as to bite into the joint portion 30 (substrate 11) of the MEMS chip 10. That is, since the eutectic alloy layer 33 is formed perpendicularly to the surface direction of the bonded portion as shown in the drawing, bonding with higher bonding strength is possible.
- the semiconductor substrates with high bonding strength and sealing property at appropriate portions while suppressing adverse effects on the sensing unit 12.
- the sensing unit 12, the integrated circuit 22, and the external circuit are electrically connected and protected from the external environment such as humidity, temperature, dust, etc. It is possible to provide a highly accurate MEMS device packaged as a unit.
- the silicon wafer on which the sensing unit 12 and the integrated circuit 22 that controls the sensing unit 12 are formed is used.
- the structure formed on the silicon wafer is not limited to this, and any circuit may be used. May be.
- a silicon wafer made of silicon a semiconductor substrate (compound semiconductor) using another material as a base material may be used.
- it is preferable that at least one of the semiconductor substrates to be bonded has an aluminum wiring.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Mechanical Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Micromachines (AREA)
- Pressure Sensors (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
Abstract
Description
本実施形態に係るMEMSデバイスは、このような共晶接合により製造されたものであり、例えば、加速度センサ、角速度センサ、赤外線センサ、圧力センサ、磁気センサおよび音響センサが考えられる。
図示のように、MEMSチップ10は、シリコン(Si)から成る基板11と、基板11の中央に微細加工技術により形成されたセンシング部12と、を有している。センシング部12は、基板11の中央に掘り込むように形成され、上述のように加速度センサ、角速度センサ、赤外線センサ、圧力センサ、磁気センサおよび音響センサ等の素子で構成されている。また、基板11には、センシング部12を囲繞するように、平面視方形環状の接合部30aが配設されている。実施形態のMEMSチップ10では、センシング部12および接合部30aが後述するCMOSチップ20と対面するように表裏反転させて、CMOSチップ20と接合される。そして、MEMSチップ10の接合部30aが、CMOSチップ20に形成した接合部30bに突き合わされ、接合部30bに成膜された金属層により、両者が共晶接合される。なお、基板11は、請求項でいう第1半導体基板に相当し、センシング部12は、請求項でいうMEMS構造体に相当する。
12 センシング部 11,21 基板
20 CMOSチップ 22 集積回路
31 含アルミニウム層 32 ゲルマニウム層
35 筋状層部 36 枝状層部
41 ピット
Claims (9)
- 第1半導体基板の接合面と第2半導体基板の接合面との間に、アルミニウムを主成分とする含アルミニウム層とゲルマニウム層とを接触状態で介在させ、加圧・加熱して、前記第1半導体基板と前記第2半導体基板とを共晶接合する半導体基板の接合方法であって、
共晶合金化する前記含アルミニウム層に対する前記ゲルマニウム層の重量比を、27wt%から52wt%としたことを特徴とする半導体基板の接合方法。 - 前記重量比を、33wt%から42wt%としたことを特徴とする請求項1に記載の半導体基板の接合方法。
- 前記ゲルマニウム層の全てと、これに接触する前記含アルミニウム層の一部とが共晶合金化するように、前記ゲルマニウム層の膜厚を調節することを特徴とする請求項1または2に記載の半導体基板の接合方法。
- 前記含アルミニウム層および前記ゲルマニウム層が、前記第1半導体基板および前記第2半導体基板のいずれか一方に成膜されていることを特徴とする請求項1ないし3のいずれかに記載の半導体基板の接合方法。
- 前記含アルミニウム層は、所定の幅を有して平面視環状に成膜され、
前記ゲルマニウム層は、前記含アルミニウム層上に平面視環状に成膜された1以上の筋状層部を有していることを特徴とする請求項4に記載の半導体基板の接合方法。 - 前記含アルミニウム層は、所定の幅を有して平面視環状に成膜され、
前記ゲルマニウム層は、前記含アルミニウム層上に平面視環状に成膜された筋状層部と、前記筋状層部から分岐した複数の枝状層部と、を有していることを特徴とする請求項4に記載の半導体基板の接合方法。 - 前記含アルミニウム層および前記ゲルマニウム層が、前記第2半導体基板に成膜され
前記第1半導体基板の接合面には、前記加圧・加熱により生じた共晶合金が浸入するピットが形成されていることを特徴とする請求項4ないし6のいずれかに記載の半導体基板の接合方法。 - 請求項1ないし7のいずれかに記載の半導体基板の接合方法によって、接合して成るMEMSデバイスであって、
前記第1半導体基板は、前記接合面側に掘り込むようにして作りこんだMEMS構造体を有し、
前記第2半導体基板は、前記接合面側に形成した前記MEMS構造体を制御する集積回路を有していることを特徴とするMEMSデバイス。 - 加速度センサ、角速度センサ、赤外線センサ、圧力センサ、磁気センサおよび音響センサのいずれかであることを特徴とする請求項8に記載のMEMSデバイス。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/513,403 US20120299128A1 (en) | 2009-12-11 | 2009-12-11 | Method of bonding semiconductor substrate and mems device |
JP2011544987A JP5367841B2 (ja) | 2009-12-11 | 2009-12-11 | 半導体基板の接合方法およびmemsデバイス |
PCT/JP2009/006786 WO2011070625A1 (ja) | 2009-12-11 | 2009-12-11 | 半導体基板の接合方法およびmemsデバイス |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2009/006786 WO2011070625A1 (ja) | 2009-12-11 | 2009-12-11 | 半導体基板の接合方法およびmemsデバイス |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2011070625A1 true WO2011070625A1 (ja) | 2011-06-16 |
Family
ID=44145197
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2009/006786 WO2011070625A1 (ja) | 2009-12-11 | 2009-12-11 | 半導体基板の接合方法およびmemsデバイス |
Country Status (3)
Country | Link |
---|---|
US (1) | US20120299128A1 (ja) |
JP (1) | JP5367841B2 (ja) |
WO (1) | WO2011070625A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015216257A (ja) * | 2014-05-12 | 2015-12-03 | 株式会社豊田中央研究所 | 半導体装置の製造方法及び半導体装置 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106542492A (zh) * | 2015-09-23 | 2017-03-29 | 中芯国际集成电路制造(北京)有限公司 | 焊盘结构、焊环结构和mems器件的封装方法 |
US10793427B2 (en) | 2017-04-04 | 2020-10-06 | Kionix, Inc. | Eutectic bonding with AlGe |
CN110116984B (zh) * | 2018-02-06 | 2022-01-28 | 中芯国际集成电路制造(上海)有限公司 | Mems器件及其制备方法 |
CN111137844B (zh) * | 2019-12-31 | 2023-07-28 | 绍兴中芯集成电路制造股份有限公司 | 共晶键合方法和半导体器件 |
FI20205914A1 (en) * | 2020-09-21 | 2022-03-22 | Teknologian Tutkimuskeskus Vtt Oy | Disc level component packaging |
DE102020215021A1 (de) | 2020-11-30 | 2022-06-02 | Robert Bosch Gesellschaft mit beschränkter Haftung | Mikromechanische Vorrichtung mit elektrisch kontaktierter Kappe |
EP4033521A1 (en) * | 2021-01-26 | 2022-07-27 | Infineon Technologies AG | Method for wafer bonding and compound semiconductor device |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58125673A (ja) * | 1982-01-12 | 1983-07-26 | 新明和工業株式会社 | 拡散接合方法 |
JPS60191679A (ja) * | 1984-03-13 | 1985-09-30 | Hitachi Ltd | 耐熱超合金の拡散接合方法 |
JPS61111789A (ja) * | 1984-11-07 | 1986-05-29 | Hitachi Ltd | 金属部材の接合法 |
JPH04317313A (ja) * | 1991-02-22 | 1992-11-09 | Messerschmitt Boelkow Blohm Gmbh <Mbb> | シリコン半導体素子を接合するための方法 |
JPH081644U (ja) * | 1996-04-12 | 1996-12-03 | 三菱マテリアル株式会社 | 半導体装置用軽量基板 |
JP2008177481A (ja) * | 2007-01-22 | 2008-07-31 | Hitachi Metals Ltd | 半導体センサー装置およびその製造方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2607699Y2 (ja) * | 1996-01-12 | 2002-03-04 | 三菱マテリアル株式会社 | 半導体装置用軽量基板 |
US6406636B1 (en) * | 1999-06-02 | 2002-06-18 | Megasense, Inc. | Methods for wafer to wafer bonding using microstructures |
JP2003068916A (ja) * | 2001-08-24 | 2003-03-07 | Sumitomo Electric Ind Ltd | 半導体素子収納用パッケージ |
US7442570B2 (en) * | 2005-03-18 | 2008-10-28 | Invensence Inc. | Method of fabrication of a AL/GE bonding in a wafer packaging environment and a product produced therefrom |
JP5175152B2 (ja) * | 2008-09-22 | 2013-04-03 | アルプス電気株式会社 | Memsセンサ |
JP2010238921A (ja) * | 2009-03-31 | 2010-10-21 | Alps Electric Co Ltd | Memsセンサ |
-
2009
- 2009-12-11 JP JP2011544987A patent/JP5367841B2/ja active Active
- 2009-12-11 WO PCT/JP2009/006786 patent/WO2011070625A1/ja active Application Filing
- 2009-12-11 US US13/513,403 patent/US20120299128A1/en not_active Abandoned
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58125673A (ja) * | 1982-01-12 | 1983-07-26 | 新明和工業株式会社 | 拡散接合方法 |
JPS60191679A (ja) * | 1984-03-13 | 1985-09-30 | Hitachi Ltd | 耐熱超合金の拡散接合方法 |
JPS61111789A (ja) * | 1984-11-07 | 1986-05-29 | Hitachi Ltd | 金属部材の接合法 |
JPH04317313A (ja) * | 1991-02-22 | 1992-11-09 | Messerschmitt Boelkow Blohm Gmbh <Mbb> | シリコン半導体素子を接合するための方法 |
JPH081644U (ja) * | 1996-04-12 | 1996-12-03 | 三菱マテリアル株式会社 | 半導体装置用軽量基板 |
JP2008177481A (ja) * | 2007-01-22 | 2008-07-31 | Hitachi Metals Ltd | 半導体センサー装置およびその製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015216257A (ja) * | 2014-05-12 | 2015-12-03 | 株式会社豊田中央研究所 | 半導体装置の製造方法及び半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
US20120299128A1 (en) | 2012-11-29 |
JPWO2011070625A1 (ja) | 2013-04-22 |
JP5367841B2 (ja) | 2013-12-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5367842B2 (ja) | 半導体基板の接合方法およびmemsデバイス | |
JP5367841B2 (ja) | 半導体基板の接合方法およびmemsデバイス | |
JP4885956B2 (ja) | 微小電気機械システムのパッケージング及び配線 | |
US8729685B2 (en) | Bonding process and bonded structures | |
TWI486303B (zh) | 由至少兩種半導體基材構成的複合物及其製造方法(二) | |
TWI498975B (zh) | 封裝結構與基材的接合方法 | |
JP2014529182A (ja) | コーティング後グラインディング前のダイシング | |
TWI566305B (zh) | 製造三維積體電路的方法 | |
JP5300470B2 (ja) | 半導体パッケージ及び同パッケージを形成する方法 | |
TW201718390A (zh) | 使用金屬矽化物形成的互補式金屬氧化物半導體微機電系統整合 | |
JP5021098B2 (ja) | 半導体基板の接合方法およびmemsデバイス | |
JP2014511560A (ja) | プレカットされウェハに塗布されるダイシングテープ上のアンダーフィル膜 | |
CN106257663A (zh) | 叠层结构、半导体器件和用于形成半导体器件的方法 | |
JP2007067175A (ja) | 半導体装置の製造方法 | |
JP2009506565A (ja) | 2つの要素を互いにシーリングまたは溶接する方法 | |
US8513091B2 (en) | Method for wafer bonding using gold and indium | |
KR100908648B1 (ko) | 복층 범프 구조물 및 그 제조 방법 | |
JP4913928B2 (ja) | 電子デバイスおよび電子デバイスの製造方法 | |
JP2016082060A (ja) | パッケージ | |
JP2009117869A (ja) | 機能素子パッケージの製造方法 | |
JP4913923B2 (ja) | 電子デバイスおよび電子デバイスの製造方法 | |
JP2012079935A (ja) | 複合基板の製造方法、及び複合基板 | |
JP5783601B2 (ja) | 中空パッケージ | |
KR20020032264A (ko) | 표면장력을 이용한 두 물체의 본딩방법과 이를 이용한구조물 제작방법 및 패키징방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 09852022 Country of ref document: EP Kind code of ref document: A1 |
|
DPE1 | Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101) | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2011544987 Country of ref document: JP |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 13513403 Country of ref document: US |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 09852022 Country of ref document: EP Kind code of ref document: A1 |