CN104871248B - 集成mram高速缓存模块 - Google Patents
集成mram高速缓存模块 Download PDFInfo
- Publication number
- CN104871248B CN104871248B CN201380066504.7A CN201380066504A CN104871248B CN 104871248 B CN104871248 B CN 104871248B CN 201380066504 A CN201380066504 A CN 201380066504A CN 104871248 B CN104871248 B CN 104871248B
- Authority
- CN
- China
- Prior art keywords
- mram
- last level
- chip
- main
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5643—Multilevel memory comprising cache storage devices
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Hall/Mr Elements (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Semiconductor Memories (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/721,092 US9378793B2 (en) | 2012-12-20 | 2012-12-20 | Integrated MRAM module |
| US13/721,092 | 2012-12-20 | ||
| PCT/US2013/076994 WO2014100619A1 (en) | 2012-12-20 | 2013-12-20 | Integrated mram cache module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104871248A CN104871248A (zh) | 2015-08-26 |
| CN104871248B true CN104871248B (zh) | 2017-10-20 |
Family
ID=49998680
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201380066504.7A Active CN104871248B (zh) | 2012-12-20 | 2013-12-20 | 集成mram高速缓存模块 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US9378793B2 (enExample) |
| EP (1) | EP2936493B1 (enExample) |
| JP (1) | JP6096929B2 (enExample) |
| CN (1) | CN104871248B (enExample) |
| HR (1) | HRP20170015T1 (enExample) |
| RS (1) | RS55452B1 (enExample) |
| SM (2) | SMT201700040T1 (enExample) |
| WO (1) | WO2014100619A1 (enExample) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6553033B2 (ja) * | 2013-08-13 | 2019-07-31 | ノースウェスタン ユニバーシティ | ペプチドコンジュゲート粒子 |
| KR20150019920A (ko) * | 2013-08-16 | 2015-02-25 | 에스케이하이닉스 주식회사 | 전자 장치 및 그 제조 방법 |
| JP5992592B1 (ja) | 2015-09-16 | 2016-09-14 | 株式会社東芝 | キャッシュメモリシステム |
| CN105527889A (zh) * | 2015-12-08 | 2016-04-27 | 中电海康集团有限公司 | 一种采用stt-mram作为单一存储器的微控制器 |
| CN105550127A (zh) * | 2015-12-08 | 2016-05-04 | 中电海康集团有限公司 | 一种基于stt-mram的读写缓存分离的ssd控制器 |
| CN105551516A (zh) * | 2015-12-15 | 2016-05-04 | 中电海康集团有限公司 | 一种基于stt-mram构建的存储器 |
| KR102353058B1 (ko) * | 2016-02-02 | 2022-01-20 | 삼성전자주식회사 | 시스템 온 칩 및 그것의 동작 방법 |
| CN107301455B (zh) * | 2017-05-05 | 2020-11-03 | 中国科学院计算技术研究所 | 用于卷积神经网络的混合立方体存储系统及加速计算方法 |
| JP7004453B2 (ja) * | 2017-08-11 | 2022-01-21 | 株式会社半導体エネルギー研究所 | グラフィックスプロセッシングユニット |
| JP6829172B2 (ja) * | 2017-09-20 | 2021-02-10 | キオクシア株式会社 | 半導体記憶装置 |
| US11968843B2 (en) * | 2018-06-28 | 2024-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Processing core and MRAM memory unit integrated on a single chip |
| CN112748859B (zh) * | 2019-10-30 | 2023-03-21 | 上海磁宇信息科技有限公司 | Mram-nand控制器及其数据写入方法 |
| CN117667829A (zh) * | 2022-08-24 | 2024-03-08 | 华为技术有限公司 | 一种片上系统 |
| CN118732924B (zh) * | 2023-03-28 | 2025-11-11 | 华为技术有限公司 | 一种数据访存方法及片上系统 |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006338513A (ja) * | 2005-06-03 | 2006-12-14 | Renesas Technology Corp | データ処理装置 |
| EP1739748A2 (en) * | 2005-06-28 | 2007-01-03 | Infineon Tehnologies AG | Magnetic shielding of MRAM chips |
| CN101430652A (zh) * | 2007-11-08 | 2009-05-13 | 国际商业机器公司 | 片内网络以及片内网络软件流水线操作方法 |
| CN101473436A (zh) * | 2006-06-16 | 2009-07-01 | 国际商业机器公司 | 用于以三维结构在高速缓存分层结构中的层之间实现非常高的带宽的方法,以及由此得到的三维结构 |
| US20120155160A1 (en) * | 2010-12-17 | 2012-06-21 | Everspin Technologies, Inc. | Memory controller and method for interleaving dram and mram accesses |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5502667A (en) * | 1993-09-13 | 1996-03-26 | International Business Machines Corporation | Integrated multichip memory module structure |
| US6289420B1 (en) * | 1999-05-06 | 2001-09-11 | Sun Microsystems, Inc. | System and method for increasing the snoop bandwidth to cache tags in a multiport cache memory subsystem |
| US20040193782A1 (en) | 2003-03-26 | 2004-09-30 | David Bordui | Nonvolatile intelligent flash cache memory |
| DE10317147A1 (de) | 2003-04-14 | 2004-10-28 | Nec Electronics (Europe) Gmbh | Sicheres Speichersystem mit Flash-Speichern und Cache-Speicher |
| JP3896112B2 (ja) * | 2003-12-25 | 2007-03-22 | エルピーダメモリ株式会社 | 半導体集積回路装置 |
| US20050177679A1 (en) | 2004-02-06 | 2005-08-11 | Alva Mauricio H. | Semiconductor memory device |
| TWI285893B (en) | 2004-11-12 | 2007-08-21 | Ind Tech Res Inst | Hybrid MRAM memory array architecture |
| JP2006323739A (ja) * | 2005-05-20 | 2006-11-30 | Renesas Technology Corp | メモリモジュール、メモリシステム、及び情報機器 |
| US7610445B1 (en) | 2005-07-18 | 2009-10-27 | Palm, Inc. | System and method for improving data integrity and memory performance using non-volatile media |
| US7464225B2 (en) * | 2005-09-26 | 2008-12-09 | Rambus Inc. | Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology |
| US20070290333A1 (en) * | 2006-06-16 | 2007-12-20 | Intel Corporation | Chip stack with a higher power chip on the outside of the stack |
| US20080133864A1 (en) | 2006-12-01 | 2008-06-05 | Jonathan Randall Hinkle | Apparatus, system, and method for caching fully buffered memory |
| KR101401560B1 (ko) * | 2007-12-13 | 2014-06-03 | 삼성전자주식회사 | 반도체 메모리 시스템 및 그것의 마모도 관리 방법 |
| JP2012014787A (ja) * | 2010-06-30 | 2012-01-19 | Sony Corp | 記憶装置 |
| KR101713051B1 (ko) | 2010-11-29 | 2017-03-07 | 삼성전자주식회사 | 하이브리드 메모리 시스템, 및 그 관리 방법 |
| JP2012243251A (ja) * | 2011-05-24 | 2012-12-10 | Elpida Memory Inc | メモリシステム |
| JP2013065150A (ja) * | 2011-09-16 | 2013-04-11 | Toshiba Corp | キャッシュメモリ装置、プロセッサ、および情報処理装置 |
| US20130108889A1 (en) * | 2011-10-27 | 2013-05-02 | Agency For Science, Technology And Research | Magnetoresistance Device and Memory Device Including the Magnetoresistance Device |
| US20130346695A1 (en) * | 2012-06-25 | 2013-12-26 | Advanced Micro Devices, Inc. | Integrated circuit with high reliability cache controller and method therefor |
-
2012
- 2012-12-20 US US13/721,092 patent/US9378793B2/en active Active
-
2013
- 2013-12-20 SM SM20170040T patent/SMT201700040T1/it unknown
- 2013-12-20 JP JP2015549786A patent/JP6096929B2/ja active Active
- 2013-12-20 HR HRP20170015TT patent/HRP20170015T1/hr unknown
- 2013-12-20 RS RS20161172A patent/RS55452B1/sr unknown
- 2013-12-20 EP EP13822034.8A patent/EP2936493B1/en active Active
- 2013-12-20 CN CN201380066504.7A patent/CN104871248B/zh active Active
- 2013-12-20 WO PCT/US2013/076994 patent/WO2014100619A1/en not_active Ceased
-
2017
- 2017-01-19 SM SM201700040T patent/SMT201700040B/it unknown
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006338513A (ja) * | 2005-06-03 | 2006-12-14 | Renesas Technology Corp | データ処理装置 |
| EP1739748A2 (en) * | 2005-06-28 | 2007-01-03 | Infineon Tehnologies AG | Magnetic shielding of MRAM chips |
| CN101473436A (zh) * | 2006-06-16 | 2009-07-01 | 国际商业机器公司 | 用于以三维结构在高速缓存分层结构中的层之间实现非常高的带宽的方法,以及由此得到的三维结构 |
| CN101430652A (zh) * | 2007-11-08 | 2009-05-13 | 国际商业机器公司 | 片内网络以及片内网络软件流水线操作方法 |
| US20120155160A1 (en) * | 2010-12-17 | 2012-06-21 | Everspin Technologies, Inc. | Memory controller and method for interleaving dram and mram accesses |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2014100619A1 (en) | 2014-06-26 |
| JP2016502223A (ja) | 2016-01-21 |
| SMT201700040T1 (it) | 2017-03-08 |
| SMT201700040B (it) | 2017-03-08 |
| EP2936493A1 (en) | 2015-10-28 |
| CN104871248A (zh) | 2015-08-26 |
| EP2936493B1 (en) | 2016-10-12 |
| JP6096929B2 (ja) | 2017-03-15 |
| RS55452B1 (sr) | 2017-04-28 |
| US9378793B2 (en) | 2016-06-28 |
| HRP20170015T1 (hr) | 2017-02-24 |
| US20140177325A1 (en) | 2014-06-26 |
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Legal Events
| Date | Code | Title | Description |
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| PB01 | Publication | ||
| EXSB | Decision made by sipo to initiate substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |