JP6096929B2 - 集積型mramモジュール - Google Patents
集積型mramモジュール Download PDFInfo
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- JP6096929B2 JP6096929B2 JP2015549786A JP2015549786A JP6096929B2 JP 6096929 B2 JP6096929 B2 JP 6096929B2 JP 2015549786 A JP2015549786 A JP 2015549786A JP 2015549786 A JP2015549786 A JP 2015549786A JP 6096929 B2 JP6096929 B2 JP 6096929B2
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- Prior art keywords
- mram
- main memory
- integrated circuit
- memory
- module
- Prior art date
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- 230000015654 memory Effects 0.000 claims description 118
- 238000012545 processing Methods 0.000 claims description 47
- 238000004891 communication Methods 0.000 claims description 5
- 230000008878 coupling Effects 0.000 claims description 3
- 238000010168 coupling process Methods 0.000 claims description 3
- 238000005859 coupling reaction Methods 0.000 claims description 3
- 230000005415 magnetization Effects 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 238000000034 method Methods 0.000 description 15
- 238000013461 design Methods 0.000 description 13
- 238000005516 engineering process Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000012546 transfer Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000011982 device technology Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004460 liquid liquid chromatography Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000003090 exacerbative effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5643—Multilevel memory comprising cache storage devices
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Hall/Mr Elements (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Semiconductor Memories (AREA)
Description
202a CPU
202b CPU
202c CPU
202d CPU
204a L2キャッシュ
204b L2キャッシュ
206 ネットワークNoC
208a L3キャッシュ
208b L3キャッシュ
210a メモリコントローラ
210b メモリコントローラ
212 メインメモリ
214 インターフェース
216 処理チップ
218 MRAMメモリモジュール
Claims (15)
- プロセッサと、
MRAMラストレベルキャッシュおよびMRAMメインメモリを備えるとともにチップ中に集積化された磁気抵抗ランダムアクセスメモリ(MRAM)モジュールと、
前記プロセッサと前記MRAMモジュールを結合するインターフェースと
を備え、
前記MRAMメインメモリが2つ以上のメインメモリスタックに分割され、前記MRAMラストレベルキャッシュが2つ以上のラストレベルキャッシュスタックに分割され、前記2つ以上のラストレベルキャッシュスタックが前記2つ以上のメインメモリスタックの拡張部として形成される、集積回路。 - 前記プロセッサが第1のチップ上に集積化され、前記MRAMモジュールが第2のチップ中に集積化され、前記インターフェースが前記第1のチップと前記第2のチップとの間の境界上に配置される、請求項1に記載の集積回路。
- 前記MRAMモジュールがメモリコントローラロジックをさらに備える、請求項1に記載の集積回路。
- 前記MRAMモジュールがモノリシックパッケージとして製造される、請求項1に記載の集積回路。
- 前記MRAMモジュールが複数のパッケージとして製造される、請求項1に記載の集積回路。
- 前記MRAMラストレベルキャッシュおよび前記MRAMメインメモリが、スピン注入磁化反転型MRAM(STT-MRAM)ビットセルを備える、請求項1に記載の集積回路。
- 前記MRAMモジュールが、中心部の前記MRAMメインメモリおよび前記MRAMメインメモリの第1の外縁に形成される前記MRAMラストレベルキャッシュを備える2次元(2D)アーキテクチャとして形成される、請求項1に記載の集積回路。
- 前記MRAMメインメモリの第2の外縁に形成されるロジック層をさらに備える、請求項7に記載の集積回路。
- 前記MRAMモジュールが、1つまたは複数のメインメモリ平面上に形成される前記MRAMメインメモリを備える3次元(3D)ホモジニアスアーキテクチャとして形成され、前記MRAMラストレベルキャッシュが、前記1つまたは複数のメインメモリ平面上に集積化される、請求項1に記載の集積回路。
- 前記1つまたは複数のメインメモリ平面と平行なロジック層平面中に形成されるロジック層をさらに備える、請求項9に記載の集積回路。
- 前記MRAMモジュールが、1つまたは複数のメインメモリ平面上に形成される前記MRAMメインメモリを備える3次元(3D)ヘテロジニアスアーキテクチャとして形成され、前記MRAMラストレベルキャッシュおよびロジック層が、前記1つまたは複数のメインメモリ平面に平行なヘテロジニアス平面上に集積化される、請求項1に記載の集積回路。
- セットトップボックス、音楽プレイヤ、ビデオプレイヤ、エンターテインメントユニット、ナビゲーションデバイス、通信デバイス、携帯情報端末(PDA)、固定位置データユニット、およびコンピュータからなるグループから選択されるデバイス中に集積化される、請求項1に記載の集積回路。
- 第1のパッケージ上に形成されるラストレベルキャッシュ無し処理手段と、
第2のパッケージ中に形成されるラストレベルキャッシュおよびメインメモリを備えるとともにチップ中に集積化された磁気抵抗ランダムアクセスメモリ(MRAM)メモリ手段と
を備え、
前記メインメモリが2つ以上のメインメモリスタックに分割され、前記ラストレベルキャッシュが2つ以上のラストレベルキャッシュスタックに分割され、前記2つ以上のラストレベルキャッシュスタックが前記2つ以上のメインメモリスタックの拡張部として形成される、システム。 - 前記第1のパッケージと前記第2のパッケージを連動する手段をさらに備える、請求項13に記載のシステム。
- 前記第2のパッケージがメモリコントローラ手段をさらに備える、請求項13に記載のシステム。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/721,092 | 2012-12-20 | ||
US13/721,092 US9378793B2 (en) | 2012-12-20 | 2012-12-20 | Integrated MRAM module |
PCT/US2013/076994 WO2014100619A1 (en) | 2012-12-20 | 2013-12-20 | Integrated mram cache module |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2016502223A JP2016502223A (ja) | 2016-01-21 |
JP2016502223A5 JP2016502223A5 (ja) | 2016-10-06 |
JP6096929B2 true JP6096929B2 (ja) | 2017-03-15 |
Family
ID=49998680
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015549786A Active JP6096929B2 (ja) | 2012-12-20 | 2013-12-20 | 集積型mramモジュール |
Country Status (8)
Country | Link |
---|---|
US (1) | US9378793B2 (ja) |
EP (1) | EP2936493B1 (ja) |
JP (1) | JP6096929B2 (ja) |
CN (1) | CN104871248B (ja) |
HR (1) | HRP20170015T1 (ja) |
RS (1) | RS55452B1 (ja) |
SM (1) | SMT201700040B (ja) |
WO (1) | WO2014100619A1 (ja) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20150019920A (ko) * | 2013-08-16 | 2015-02-25 | 에스케이하이닉스 주식회사 | 전자 장치 및 그 제조 방법 |
JP5992592B1 (ja) | 2015-09-16 | 2016-09-14 | 株式会社東芝 | キャッシュメモリシステム |
CN105550127A (zh) * | 2015-12-08 | 2016-05-04 | 中电海康集团有限公司 | 一种基于stt-mram的读写缓存分离的ssd控制器 |
CN105527889A (zh) * | 2015-12-08 | 2016-04-27 | 中电海康集团有限公司 | 一种采用stt-mram作为单一存储器的微控制器 |
CN105551516A (zh) * | 2015-12-15 | 2016-05-04 | 中电海康集团有限公司 | 一种基于stt-mram构建的存储器 |
KR102353058B1 (ko) * | 2016-02-02 | 2022-01-20 | 삼성전자주식회사 | 시스템 온 칩 및 그것의 동작 방법 |
CN107301455B (zh) * | 2017-05-05 | 2020-11-03 | 中国科学院计算技术研究所 | 用于卷积神经网络的混合立方体存储系统及加速计算方法 |
JP7004453B2 (ja) * | 2017-08-11 | 2022-01-21 | 株式会社半導体エネルギー研究所 | グラフィックスプロセッシングユニット |
JP6829172B2 (ja) * | 2017-09-20 | 2021-02-10 | キオクシア株式会社 | 半導体記憶装置 |
US11968843B2 (en) * | 2018-06-28 | 2024-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Processing core and MRAM memory unit integrated on a single chip |
CN112748859B (zh) * | 2019-10-30 | 2023-03-21 | 上海磁宇信息科技有限公司 | Mram-nand控制器及其数据写入方法 |
CN117667829A (zh) * | 2022-08-24 | 2024-03-08 | 华为技术有限公司 | 一种片上系统 |
CN118732924A (zh) * | 2023-03-28 | 2024-10-01 | 华为技术有限公司 | 一种数据访存方法及片上系统 |
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-
2012
- 2012-12-20 US US13/721,092 patent/US9378793B2/en active Active
-
2013
- 2013-12-20 CN CN201380066504.7A patent/CN104871248B/zh active Active
- 2013-12-20 JP JP2015549786A patent/JP6096929B2/ja active Active
- 2013-12-20 RS RS20161172A patent/RS55452B1/sr unknown
- 2013-12-20 WO PCT/US2013/076994 patent/WO2014100619A1/en active Application Filing
- 2013-12-20 EP EP13822034.8A patent/EP2936493B1/en active Active
-
2017
- 2017-01-05 HR HRP20170015TT patent/HRP20170015T1/hr unknown
- 2017-01-19 SM SM201700040T patent/SMT201700040B/it unknown
Also Published As
Publication number | Publication date |
---|---|
SMT201700040B (it) | 2017-03-08 |
CN104871248A (zh) | 2015-08-26 |
WO2014100619A1 (en) | 2014-06-26 |
US20140177325A1 (en) | 2014-06-26 |
EP2936493A1 (en) | 2015-10-28 |
HRP20170015T1 (hr) | 2017-02-24 |
CN104871248B (zh) | 2017-10-20 |
JP2016502223A (ja) | 2016-01-21 |
US9378793B2 (en) | 2016-06-28 |
EP2936493B1 (en) | 2016-10-12 |
RS55452B1 (sr) | 2017-04-28 |
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