WO2018004667A1 - Two transistor memory cell using high mobility metal oxide semiconductors - Google Patents

Two transistor memory cell using high mobility metal oxide semiconductors Download PDF

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Publication number
WO2018004667A1
WO2018004667A1 PCT/US2016/040764 US2016040764W WO2018004667A1 WO 2018004667 A1 WO2018004667 A1 WO 2018004667A1 US 2016040764 W US2016040764 W US 2016040764W WO 2018004667 A1 WO2018004667 A1 WO 2018004667A1
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Prior art keywords
gate
metal layer
source
metal
transistor
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PCT/US2016/040764
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French (fr)
Inventor
Van H. Le
Gilbert William DEWEY
Marko Radosavljevic
Rafael Rios
Jack T. Kavalieros
Shriram SHIVARAMAN
Mesut Meterelliyoz
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Intel Corporation
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Priority to PCT/US2016/040764 priority Critical patent/WO2018004667A1/en
Publication of WO2018004667A1 publication Critical patent/WO2018004667A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell

Definitions

  • the present description is related to memory cells for semiconductors and, in particular, to two transistor memory cells using metal oxide semiconductors.
  • SRAM Static Random Access Memory
  • CMOS Complementary Metal Oxide Semiconductor
  • DRAM Dynamic Random Access Memory
  • 6T SRAM two transistor
  • 3T memory gain cells are normally used for DRAM (Dynamic Random Access Memory).
  • DRAM is not as fast as 6T SRAM but is less expensive and requires less frequent refresh cycles.
  • a DRAM cell stores the memory state in a capacitor and so for optimum performance DRAM is built on separate dies for which the design of the capacitor is optimized. With a separate die, the DRAM can be made using the best or lowest cost techniques available for DRAM without regard to the logic circuitry. Nevertheless, there are still high off- state leakages that limit the retention times of the corresponding memory cell. Therefore, constant refresh cycles are required to retain the state stored in the memory. The refresh cycles require power so that DRAM also requires constant power and generates significant heat.
  • Figure 1 is a circuit diagram of a two transistor memory cell according to an
  • Figure 2 is a diagram of a two transistor memory cell array according to an embodiment.
  • Figure 3 is a cross-sectional side view diagram of a memory cell in metal layers above silicon logic according to an embodiment.
  • Figure 4 is a cross-sectional side view diagram of an alternative memory cell in metal layers above silicon logic according to an embodiment.
  • Figure 5 is a cross-sectional side view diagram of another alternative memory cell in metal layers above silicon logic according to an embodiment.
  • Figure 6 is a process flow diagram of fabricating a two transistor memory cell according to an embodiment.
  • Figure 7 is a block diagram of a computing device incorporating a die with a memory cell array according to an embodiment.
  • a low off-state leakage write transistor such as an metal oxide semiconductor (AOS), such as IGZO (Indium Gallium Zinc Oxide), transistor may be fabricated for use in a memory cell.
  • AOS metal oxide semiconductor
  • IGZO Indium Gallium Zinc Oxide
  • transistor may be fabricated for use in a memory cell.
  • AOS metal oxide semiconductor
  • IZO Indium Zinc Oxide
  • ITO Indium Tin Oxide
  • Non-Si based transistors such as metal oxide or amorphous oxide semiconductors (AOS) with high mobility and low off-state leakage current are suitable for use in very high speed memory applications, such as those normally reserved for SRAM.
  • these oxide semiconductor materials can be deposited in the back end layers of a silicon die stack to allow for vertical; 3-D integration. Stacking the memory over other logic increases the scaling density of the die.
  • the metal oxides may be amorphous, crystalline, or polycrystalline.
  • Embedded memory becomes increasingly important in efforts to reduce the total number of dies and also to increase speed.
  • a reduced overall memory array footprint helps reduce aerial density scaling and cost. This is particularly true of memory which comes in large arrays and with traditional SRAM that uses six transistors.
  • a 3-D vertical 2T memory array that can be created in the back end layers presents real benefits.
  • the described fabrication of 2T memory can replace 6T SRAM for certain on-die memory applications, thereby allowing for higher density and lower costs.
  • 2T memory cells are used in some high speed memory applications and offer a speed in between that of SRAM and DRAM.
  • the gate capacitance of one of the transistors is used as the storage element and the gate capacitance of the other transistor is used as the charging element.
  • the retention time of the memory cell is limited by the total leakage in the OFF state.
  • the current in the sensing transistor varies by orders of magnitude between a "0" or OFF state and the "1" or ON state, providing wide read margins.
  • the read speed depends at least on part on the speed of the sensing transistor.
  • Figure 1 is a circuit diagram of a single 2T memory cell 102.
  • It has a charging transistor 104 with a source coupled to a write bitline WBL and a gate coupled to a write word line WWL.
  • the drain is coupled to the gate of a read or sensing transistor 106.
  • the source of the sensing transistor is coupled to a read bit line RBL and the drain is coupled to a read word line RWL.
  • the charging or write transistor may be formed with a very low off-state leakage using an amorphous oxide semiconductor, AOS, such as IGZO as the channel material.
  • AOS amorphous oxide semiconductor
  • the sense or read transistor may be fabricated with a high mobility low leakage amorphous oxide semiconductor, AOS, such as IZO, or ITO channel. This provides for a fast read transistor.
  • the charge may then be stored in the channel of the charging transistor very quickly for fast write times.
  • the charge may be read quickly using the sensing transistor for fast read time. While the materials will be referred to generally herein as AOS or amorphous, other metal oxide semiconductor materials whether amorphous, crystalline, or polycrystalline may be used.
  • the AOS channel construction allows the transistors to be fabricated in metal and dielectric without doped silicon wells. This is indicated with various contacts of the transistors being labeled by a metal layer indicator from M0 to M3. These are provided as examples.
  • memory cells may be stacked over each other so that one memory cell may use metal layers M1-M4 and another uses M6-M9 or any other desired pattern to suit the intended memory array design.
  • Figure 2 is an example of a 2T memory cell array 122 with rows across the horizontal direction and columns down the vertical direction. The rows share bitlines and the columns share word lines. Each 2T grouping provides one bit of storage as ON or OFF. Considering one of the cells 124 in position (0,1) labeled as transistor A, it is shown as storing a "1" or ON state. This state was written by activating or setting to ON or high WBL1 and WWL0 for as long as it takes to store a sufficient charge.
  • RBL1 is charged to "1" for a precharge phase.
  • RWL0 is pulled to “0” to select cell (1,0).
  • the other RWL remain at “1.”
  • the ON or “1” state of transistor A is then sensed on RWL0 through the sense transistor.
  • Figure 3 is a cross-sectional side view diagram of a 3D vertical configuration for a memory cell 202 in metal layers over silicon logic circuitry.
  • the 2T memory cell is formed as embedded memory in a die that contains other logic.
  • the other logic may be for a central processor chip, a graphics processor chip, an image processing chip, a digital signal processor, or any of a variety of other types of logic and processing circuitry.
  • the die is built on a substrate 204, such as a silicon substrate and logic circuitry 206 is formed on the front side of the substrate. This typically referred to as FEOL (Front End of the Line).
  • FEOL Front End of the Line
  • the application of the metal layers alternating with dielectric layers is typically referred to as the BEOL (Back End of the Line) and is used to provide connections between the logic components transistors, capacitors, resistors, etc. of the FEOL.
  • the BEOL also uses vias through the dielectric between metal layers to provide connections from the logic to pads for external connections.
  • the dielectric layers are sometimes referred to as ILD (Interlayer Dielectric) with numbers to indicate the number of layers.
  • a bottom metal layer 208 applied over one or more metal and dielectric (ILD) layers over the logic circuitry 206.
  • the bottom metal layer may be copper, aluminum, tungsten or any other suitable metal material. This layer is indicated as the seventh metal layer, M7, but may be any other layer.
  • a dielectric layer 210 is applied over the bottom metal layer. The dielectric may be formed of any of a variety of different materials including Sn02, ITO, or IZO.
  • a second metal layer, M8, 212 is applied over the first dielectric 210.
  • Another dielectric layer 214 is applied over the second metal layer 212 and a top metal layer, M9, 216 is applied over the second dielectric. While three metal layers are sufficient to form the memory cell, there may be more layers for other purposes above and below the memory cell.
  • the memory cell is formed of a sensing transistor 221 and a charging transistor 231 coupled together with a via 232 between the first 208 and second 212 metal layers.
  • a source 220 and drain 224 are formed of the metal in the bottom metal layer 208. The source and drain may also serve as contacts for the RBL and RWL and connect to control circuitry and other memory cells in an array. In this way the bottom metal layer serves as connection lines and terminals for the sensing transistor 221.
  • the gate and channel of the sensing transistor are formed in the dielectric layer 210 above the first metal layer.
  • First a layer 226 of an AOS is applied.
  • This AOS layer forms a channel and is formed of a material that is suited to the metal, dielectric layer environment and that allows for fast reads and low leakage such as ITO or IGO. For a typical memory cell, this layer may be 6-8nm thick and is in direct electrical contact with the source and drain.
  • the first AOS layer 226 is covered with a high K dielectric layer 228 of e.g. 5-10nm thick, which is then covered with a metal layer 230 to form a gate over the AOS channel.
  • the thickness of the dielectric may be selected based on a balance of leakage and electrostatics for the device.
  • a conductive via 232 such as a filled copper via is formed over the gate to connect to the next metal layer 212 through the dielectric layer 210 in which the gate has been formed.
  • the charging transistor 231 has a source 234 and a drain 236 in the next or second metal layer 212.
  • the source 234 connects to the via 232 from the gate of the sensing transistor.
  • a second AOS layer 240 is formed as a channel in the dielectric layer 214 and between the source and the drain.
  • the charging transistor has an AOS layer 240 to serve as a channel, a high K dielectric layer 242 over the AOS layer and a metal layer 246 over the high K dielectric to form the gate.
  • a different AOS material may be selected such as IGZO for still lower leakage.
  • the charging transistor stores charge in the connection 232 between the source of the charging transistor and the gate of the sensing transistor.
  • the connection is a via through the dielectric.
  • the metal gate 246 above the storage node 232 is coupled through another via 248 to a connection pad 250 on the metal layer 216 above the gate.
  • This connection pad serves as the gate electrode for connection to the WWL.
  • the metal layer is used for routing the WWL, connecting to other memory cells, and connecting to the write circuitry and controllers. These controllers may be in the logic circuitry 206 below the metal layers or in another location.
  • Other vias 252 may be used to connect other components to form the memory array. Addressing, refresh, and read circuity may be formed in the logic circuitry 206 below the memory array and be connected to the metal layers using vertical vias 252.
  • This all AOS memory cell allows for a stackable memory array in the backend for 3D vertical embedded circuit integration that is compatible with logic processes.
  • the higher mobility AOS will also allow for faster reading of the memory value stored in the storage node.
  • Figure 4 is a cross-sectional side view diagram of an alternative structure for the all AOS
  • 2T memory cell of Figure 3 The structure is similar in that the source and drain contacts for the two transistors 262, 264 are formed in metal layers of the BEOL. Metal gates 266, 272 are formed in the dielectric layers between the metal layers. An AOS channel 270, 276 is formed over the source and drain and is isolated from the metal gate by a high K dielectric 268, 274.
  • the AOS channel and the high K dielectric are in horizontal layers only.
  • both the AOS channel 226, 240 and the high K dielectric 228, 242 wrap around the sides of the metal gate.
  • the bottom of the gate over the source and drain and the sides of the gate within the dielectric layer are covered by these two layers.
  • the films are deposited include a pre-formed trench between the source and the drain. As a result the IGZO channel is deposited without any damage to the film.
  • Figure 5 is a cross-sectional side view diagram of another alternative 3D vertical configuration for a memory cell in metal layers over silicon logic circuitry (not shown), a bottom metal layer Ml is applied over one or more metal and dielectric (ILD) layers over the logic circuitry. This layer is indicated as Ml, but may be any other layer. A dielectric layer is applied over the bottom metal layer, then another metal layer M2, then ILD, then another metal layer M3. There may be more layers for other purposes above and below the memory cell.
  • ILD metal and dielectric
  • the memory cell is formed of a sensing transistor 282 and a charging transistor 280 coupled together with a via between the first Ml and second M2 metal layers.
  • a source 292 and drain 293 for the sensing transistor 282 are formed of the metal in the top metal layer M3. The source and drain may also serve as contacts for the RBL and RWL and connect to control circuitry and other memory cells in an array.
  • the gate and channel of the sensing transistor are formed in the dielectric layer above the second metal layer.
  • the metal gate is covered with a high K dielectric layer which is then covered in a high mobility metal oxide layer to form the channel.
  • This oxide layer allows for fast reads and low leakage using a material such as ITO or IGO.
  • Conductive vias such as filled copper vias are formed over the gate channel to connect to the source and drain of the sensing transistor in M3.
  • the vias are formed after the gate has been formed and then the source and drain are formed by patterning the metal layer M3 over the vias.
  • the charging transistor 280 has a source 287 and a drain 291 formed by patterning the second metal layer M2.
  • the metal gate 288 of the sensing transistor is formed directly over the source 287 of the charging transistor although there may be a via formed in between depending on the particular design needs.
  • the storage node for the charging transistor 280 is in this source node 287 and a via between the source node and the charging transistor gate channel 285.
  • the gate electrode 290 of the charging transistor is formed in the first metal layer Ml and the charging transistor gate is formed directly over and in contact with this electrode. As with the sensing transistor gate, there may be a via (not shown) in between the two to suit particular transistor designs and dimension.
  • the charging transistor gate may be formed by first depositing the gate metal 283 over the patterned gate 290 in Ml, then a high K dielectric 284 over the metal and a metal oxide semiconductor 285 as a channel over the dielectric.
  • the oxide channels for both transistors may be covered in an oxynitride or other protective layer 286 before being covered in the ILD up to the next metal layer. Vias are formed over the channel through the ILD up to the next metal layer M2.
  • the source 287 and drain 291 of the charging transistor are formed in the next metal layer M2 over these vias.
  • the charging transistor channel may be formed of a different metal oxide semiconductor material, such as IGZO, for still lower leakage.
  • IGZO metal oxide semiconductor material
  • the gate electrode 290 in the first metal layer serves as a connection pad for connection to the WWL.
  • the first metal layer is used for routing the WWL, connecting to other memory cells, and connecting to the write circuitry and controllers which may be in the logic circuitry below the metal layers or in another location.
  • Figure 6 is a process flow diagram for forming a 2T memory cell array in BEOL layers as shown in Figures 3, 4 and 5.
  • the bottom layer metal lines are patterned to form the source and drain for the read transistor and the RBL and RWL for the memory array. This may be done using a damascene process or any other desired approach.
  • the particular metal lines for the source and drain may depend on the particular implementation as mentioned above.
  • RBL and RWL may be at the same layer or at a layer below the source and drain layers and then connected using vias. This is followed at 504 with a CMP (chemical metal planarization) over the metal layers.
  • CMP chemical metal planarization
  • a nitride etch stop layer is applied over the planarized metal and the first dielectric layer is formed over the metal lines.
  • the dielectric is patterned and etched to form openings for the sensing transistor gate.
  • the gate layers are deposited into the openings.
  • the high speed AOS material such as IGO or ITO is deposited as a channel. This may be done using CVD (Chemical Vapor Deposition) or in any of a variety of other ways.
  • the high K dielectric which may be applied using ALD (Atomic Layer Deposition) or in any of a variety of other ways is deposited, then at 514 the opening is filled with the metal.
  • a damascene approach may be used. The deposit may be only on the bottom of the opening as shown in Figure 4 or also on the sidewalls as shown in Figure 3. In any case the deposits are blanket layer deposition and the AOS material is in contact with the source and the drain.
  • a CMP is applied over the metal fill for the gate layer and then a further layer of nitride etch stop and dielectric is applied over the rest of the gate opening. Another CMP is performed over the second ILD.
  • a via is formed over the metal gate by etching openings into the planarized ILD and then filling the opening with copper or another suitable conductor.
  • the next metal layer is then patterned and applied at 520 over the via and the rest of the dielectric to form the source and drain areas of the charging transistor.
  • the next layer of dielectric is applied over the second metal layer.
  • the metal may first be planarized and protected with a nitride etch stop layer before the next layer of ILD is applied.
  • the dielectric is etched to open areas for the AOS channel and metal gate.
  • the ILD and nitride etch stop layer are removed to expose the metal lines corresponding to the source and drain.
  • a blanket AOS deposition is made using e.g. CVD so that the AOS is in contact with the source and drain of the charging transistor.
  • an AOS with a low off state leakage such as IGZO is chosen to reduce the refresh rate of the memory cell.
  • IGZO is chosen to reduce the refresh rate of the memory cell.
  • CMP is used again to planarize the metal of the gate.
  • a nitride etch stop deposition is performed over the gate metal at 534 then ILD is deposited to form the level of the next metal layer.
  • the ILD is planarized and then the via to the metal gate is formed.
  • openings are etched for vias to the metal gate and to the lower metal layers for any other desired connections and at 538 these are filled with a conductor.
  • next metal layer with a gate electrode and any other routing such as WWL and WBL are formed in the next metal layer.
  • the die is finished with routing layers, contact pads, solder balls and any other desired components. Additional operations may also be applied to the back side of the die, such as thinning, applying heat spreaders and other operations.
  • FIG. 7 illustrates a computing device 11 in accordance with one implementation.
  • the computing device 11 houses a board 2.
  • the board 2 may include a number of components, including but not limited to a processor 4 and at least one communication chip 6.
  • the processor 4 is physically and electrically coupled to the board 2.
  • the at least one communication chip 6 is also physically and electrically coupled to the board 2.
  • the communication chip 6 is part of the processor 4.
  • computing device 11 may include other components that may or may not be physically and electrically coupled to the board 2.
  • these other components include, but are not limited to, volatile memory (e.g., DRAM) 8, non-volatile memory (e.g., ROM) 9, flash memory (not shown), a graphics processor 12, a digital signal processor (not shown), a crypto processor (not shown), a chipset 14, an antenna 16, a display 18 such as a touchscreen display, a touchscreen controller 20, a battery 22, an audio codec (not shown), a video codec (not shown), a power amplifier 24, a global positioning system (GPS) device 26, a compass 28, an accelerometer (not shown), a gyroscope (not shown), a speaker 30, a camera 32, and a mass storage device (such as hard disk drive) 10, compact disk (CD) (not shown), digital versatile disk (DVD) (not shown), and so forth).
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • the communication chip 6 enables wireless and/or wired communications for the transfer of data to and from the computing device 11.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 6 may implement any of a number of wireless or wired standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, Ethernet derivatives thereof, as well as any other wireless and wired protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 11 may include a plurality of communication chips 6. For instance, a first communication chip 6 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second
  • communication chip 6 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the integrated circuit die of the processor, memory devices, communication devices, or other components are fabricated to include two transistor memory cells with an AOS as described herein.
  • the described memory cells may be embedded as memory for other components in a CMOS or other logic processing die or a standalone memory array may be made on its own die.
  • the term "processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the computing device 11 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 11 may be any other electronic device that processes data including a wearable device.
  • Embodiments may be implemented as a part of one or more memory chips, controllers, CPUs (Central Processing Unit), microchips or integrated circuits interconnected using a motherboard, an application specific integrated circuit (ASIC), and/or a field programmable gate array (FPGA).
  • CPUs Central Processing Unit
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • references to “one embodiment”, “an embodiment”, “example embodiment”, “various embodiments”, etc., indicate that the embodiment(s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Further, some embodiments may have some, all, or none of the features described for other embodiments.
  • Coupled is used to indicate that two or more elements co-operate or interact with each other, but they may or may not have intervening physical or electrical components between them.
  • Some embodiments pertain to a memory cell structure that includes a sensing transistor having a source and a drain in a first metal layer and a gate between the source and the drain, wherein the gate has a channel between and coupled to the source and the drain, the channel formed of an metal oxide semiconductor material, a charging transistor having a source and a drain in a second metal layer and a gate between the source and the drain, wherein the gate has a channel between and coupled to the source and the drain, the channel formed of metal oxide semiconductor material, wherein the source of the charging transistor is coupled to the gate of the sensing transistor, and a gate electrode in a third metal layer coupled to the gate of the charging transistor.
  • the metal oxide semiconductor material of the sensing transistor is selected as a high speed material.
  • the metal oxide semiconductor material of the sensing transistor is an indium gallium oxide or an indium tin oxide.
  • the metal oxide semiconductor material of the charging transistor is selected as a low off state leakage material.
  • the metal oxide semiconductor material of the charging transistor is an indium gallium zinc oxide.
  • inventions include an interlayer dielectric between the first metal layer and the second metal layer and wherein the gate of the sensing transistor is in the interlayer dielectric.
  • Further embodiments include a conductive via through the interlayer dielectric coupled to the gate of the sensing transistor and to the source of the charging transistor, the via forming a storage node of the charging transistor.
  • the gate electrode is coupled to the metal of the gate through the conductive via.
  • the first metal layer on a semiconductor die over logic circuitry of the die, wherein the second metal layer is over the first metal layer, and wherein the third metal layer is over the second metal layer.
  • Some embodiments pertain to a method that includes patterning a first metal layer to form a source and a drain, of a sensing transistor over logic circuitry on a semiconductor die, applying a first interlayer dielectric (ILD) over the first metal layer, depositing a high speed amorphous oxide semiconductor metal oxide semiconductor material into an opening in the first ILD as a sensing transistor gate channel, depositing a metal over the metal oxide semiconductor as a gate, forming a via over the gate, patterning a second metal layer to form a source and a drain of a charging transistor over the gate of the sensing transistor wherein the source of the charging transistor is coupled to the via, applying a second ILD over the second metal layer; depositing a low off state leakage metal oxide semiconductor material in an opening in the second ILD as charging transistor gate channel, depositing a metal over the charging transistor gate channel as a gate, forming a second via over the charging transistor gate, and patterning a third metal layer with a gate electrode coupled to the second via.
  • ILD interlayer di
  • the high speed metal oxide semiconductor OS material is an indium gallium oxide or an indium tin oxide.
  • the low off state leakage metal oxide semiconductor material is an indium gallium zinc oxide.
  • Further embodiments include depositing a high K dielectric over the high speed metal oxide semiconductor material before depositing the metal.
  • depositing a low off state leakage metal oxide semiconductor material comprises a damascene process to deposit the metal oxide semiconductor material in a pre-formed trench between the source and drain.
  • Some embodiments pertain to a computing system that includes a memory having instructions stored thereon, and a processor coupled to the memory to execute the instructions, the processor having silicon logic circuitry formed on a silicon substrate and embedded memory, the embedded memory having a sensing transistor having a source and a drain in a first metal layer and a gate between the source and the drain, wherein the gate has a channel between and coupled to the source and the drain, the channel formed of a metal oxide semiconductor material, a charging transistor having a source and a drain in a second metal layer and a gate between the source and the drain, wherein the gate has a channel between and coupled to the source and the drain, the channel formed of a metal oxide semiconductor material, wherein the source of the charging transistor is coupled to the gate of the sensing transistor, and a gate electrode in a third metal layer coupled to the gate of the charging transistor.
  • inventions include an interlayer dielectric between the first metal layer and the second metal layer and wherein the sensing transistor gate channel is formed of indium gallium oxide or indium tin oxide is in the interlayer dielectric.
  • Further embodiments include a conductive via through the interlayer dielectric coupled to the gate of the sensing transistor and to the source of the charging transistor, the via forming a storage node of the charging transistor. Further embodiments include a read word line coupled to the first metal layer, a write bit line in the second metal layer and a write word line in the third metal layer and wherein the read word line, the write bit line and the write word line are each coupled to the logic circuitry.
  • the embedded memory comprises a plurality of sensing transistors and charging transistors in an array coupled to a shared write bit line and a shared write word line.

Abstract

A two transistor memory cell is described that uses high mobility amorphous oxide semiconductors. In one example, a sensing transistor has a source and a drain in a first metal layer and a gate between the source and the drain. The gate has a channel formed of a metal oxide semiconductor. A charging transistor has a source and a drain in a second metal layer and a gate channel also formed of metal oxide semiconductor, wherein the source of the charging transistor is coupled to the gate of the sensing transistor, and a gate electrode in a third metal layer is coupled to the gate of the charging transistor.

Description

TWO TRANSISTOR MEMORY CELL USING
HIGH MOBILITY METAL OXIDE SEMICONDUCTORS
FIELD
The present description is related to memory cells for semiconductors and, in particular, to two transistor memory cells using metal oxide semiconductors.
BACKGROUND
In silicon semiconductor processors, memory is critical for performing many functions. For particularly high speed memory SRAM (Static Random Access Memory) is used. The SRAM circuits are usually embedded into the same die as logic circuitry, although discrete SRAM dies are also made. For embedded applications, the memory is built on the same die as the processor and so compatibility with CMOS (Complementary Metal Oxide Semiconductor) logic circuitry allows costs to be reduced. On the other hand a typical SRAM circuit has six transistors and so is expensive to produce in large numbers. SRAM also requires frequent refresh cycles and so it consumes power and generates heat.
2T (two transistor) or 3T memory gain cells are normally used for DRAM (Dynamic Random Access Memory). DRAM is not as fast as 6T SRAM but is less expensive and requires less frequent refresh cycles. A DRAM cell stores the memory state in a capacitor and so for optimum performance DRAM is built on separate dies for which the design of the capacitor is optimized. With a separate die, the DRAM can be made using the best or lowest cost techniques available for DRAM without regard to the logic circuitry. Nevertheless, there are still high off- state leakages that limit the retention times of the corresponding memory cell. Therefore, constant refresh cycles are required to retain the state stored in the memory. The refresh cycles require power so that DRAM also requires constant power and generates significant heat.
BRIEF DESCRIPTION OF THE DRAWINGS
Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.
Figure 1 is a circuit diagram of a two transistor memory cell according to an
embodiment.
Figure 2 is a diagram of a two transistor memory cell array according to an embodiment. Figure 3 is a cross-sectional side view diagram of a memory cell in metal layers above silicon logic according to an embodiment. Figure 4 is a cross-sectional side view diagram of an alternative memory cell in metal layers above silicon logic according to an embodiment.
Figure 5 is a cross-sectional side view diagram of another alternative memory cell in metal layers above silicon logic according to an embodiment.
Figure 6 is a process flow diagram of fabricating a two transistor memory cell according to an embodiment.
Figure 7 is a block diagram of a computing device incorporating a die with a memory cell array according to an embodiment. DETAILED DESCRIPTION
As described herein a low off-state leakage write transistor such as an metal oxide semiconductor (AOS), such as IGZO (Indium Gallium Zinc Oxide), transistor may be fabricated for use in a memory cell. This may be paired with higher mobility but low leakage metal oxide semiconductors, such as IZO (Indium Zinc Oxide) or ITO (Indium Tin Oxide), as a faster read transistor. Non-Si based transistors such as metal oxide or amorphous oxide semiconductors (AOS) with high mobility and low off-state leakage current are suitable for use in very high speed memory applications, such as those normally reserved for SRAM. In addition, these oxide semiconductor materials can be deposited in the back end layers of a silicon die stack to allow for vertical; 3-D integration. Stacking the memory over other logic increases the scaling density of the die. The metal oxides may be amorphous, crystalline, or polycrystalline.
Embedded memory becomes increasingly important in efforts to reduce the total number of dies and also to increase speed. A reduced overall memory array footprint helps reduce aerial density scaling and cost. This is particularly true of memory which comes in large arrays and with traditional SRAM that uses six transistors. A 3-D vertical 2T memory array that can be created in the back end layers presents real benefits. The described fabrication of 2T memory can replace 6T SRAM for certain on-die memory applications, thereby allowing for higher density and lower costs.
2T memory cells are used in some high speed memory applications and offer a speed in between that of SRAM and DRAM. In a 2T cell, the gate capacitance of one of the transistors is used as the storage element and the gate capacitance of the other transistor is used as the charging element. The retention time of the memory cell is limited by the total leakage in the OFF state. Moreover, the current in the sensing transistor varies by orders of magnitude between a "0" or OFF state and the "1" or ON state, providing wide read margins. The read speed depends at least on part on the speed of the sensing transistor. Figure 1 is a circuit diagram of a single 2T memory cell 102. It has a charging transistor 104 with a source coupled to a write bitline WBL and a gate coupled to a write word line WWL. The drain is coupled to the gate of a read or sensing transistor 106. The source of the sensing transistor is coupled to a read bit line RBL and the drain is coupled to a read word line RWL. As mentioned above, there is an inherent capacitance 108 between the drain of the charging transistor and the gate of the sensing transistor. There may also be a physical actual capacitor in this location.
The charging or write transistor may be formed with a very low off-state leakage using an amorphous oxide semiconductor, AOS, such as IGZO as the channel material. The sense or read transistor may be fabricated with a high mobility low leakage amorphous oxide semiconductor, AOS, such as IZO, or ITO channel. This provides for a fast read transistor. The charge may then be stored in the channel of the charging transistor very quickly for fast write times. The charge may be read quickly using the sensing transistor for fast read time. While the materials will be referred to generally herein as AOS or amorphous, other metal oxide semiconductor materials whether amorphous, crystalline, or polycrystalline may be used.
The AOS channel construction allows the transistors to be fabricated in metal and dielectric without doped silicon wells. This is indicated with various contacts of the transistors being labeled by a metal layer indicator from M0 to M3. These are provided as examples.
Different metal layers may be used to suit different implementations. In addition, memory cells may be stacked over each other so that one memory cell may use metal layers M1-M4 and another uses M6-M9 or any other desired pattern to suit the intended memory array design.
Figure 2 is an example of a 2T memory cell array 122 with rows across the horizontal direction and columns down the vertical direction. The rows share bitlines and the columns share word lines. Each 2T grouping provides one bit of storage as ON or OFF. Considering one of the cells 124 in position (0,1) labeled as transistor A, it is shown as storing a "1" or ON state. This state was written by activating or setting to ON or high WBL1 and WWL0 for as long as it takes to store a sufficient charge.
In order to read the same cell, RBL1 is charged to "1" for a precharge phase. Next RWL0 is pulled to "0" to select cell (1,0). The other RWL remain at "1." The ON or "1" state of transistor A is then sensed on RWL0 through the sense transistor.
Figure 3 is a cross-sectional side view diagram of a 3D vertical configuration for a memory cell 202 in metal layers over silicon logic circuitry. The 2T memory cell is formed as embedded memory in a die that contains other logic. The other logic may be for a central processor chip, a graphics processor chip, an image processing chip, a digital signal processor, or any of a variety of other types of logic and processing circuitry. The die is built on a substrate 204, such as a silicon substrate and logic circuitry 206 is formed on the front side of the substrate. This typically referred to as FEOL (Front End of the Line).
The application of the metal layers alternating with dielectric layers is typically referred to as the BEOL (Back End of the Line) and is used to provide connections between the logic components transistors, capacitors, resistors, etc. of the FEOL. The BEOL also uses vias through the dielectric between metal layers to provide connections from the logic to pads for external connections. The dielectric layers are sometimes referred to as ILD (Interlayer Dielectric) with numbers to indicate the number of layers.
In the illustrated example there is a bottom metal layer 208 applied over one or more metal and dielectric (ILD) layers over the logic circuitry 206. The bottom metal layer may be copper, aluminum, tungsten or any other suitable metal material. This layer is indicated as the seventh metal layer, M7, but may be any other layer. A dielectric layer 210 is applied over the bottom metal layer. The dielectric may be formed of any of a variety of different materials including Sn02, ITO, or IZO. A second metal layer, M8, 212 is applied over the first dielectric 210. Another dielectric layer 214 is applied over the second metal layer 212 and a top metal layer, M9, 216 is applied over the second dielectric. While three metal layers are sufficient to form the memory cell, there may be more layers for other purposes above and below the memory cell.
The memory cell is formed of a sensing transistor 221 and a charging transistor 231 coupled together with a via 232 between the first 208 and second 212 metal layers. A source 220 and drain 224 are formed of the metal in the bottom metal layer 208. The source and drain may also serve as contacts for the RBL and RWL and connect to control circuitry and other memory cells in an array. In this way the bottom metal layer serves as connection lines and terminals for the sensing transistor 221.
The gate and channel of the sensing transistor are formed in the dielectric layer 210 above the first metal layer. First a layer 226 of an AOS is applied. This AOS layer forms a channel and is formed of a material that is suited to the metal, dielectric layer environment and that allows for fast reads and low leakage such as ITO or IGO. For a typical memory cell, this layer may be 6-8nm thick and is in direct electrical contact with the source and drain. The first AOS layer 226 is covered with a high K dielectric layer 228 of e.g. 5-10nm thick, which is then covered with a metal layer 230 to form a gate over the AOS channel. The thickness of the dielectric may be selected based on a balance of leakage and electrostatics for the device. A conductive via 232 such as a filled copper via is formed over the gate to connect to the next metal layer 212 through the dielectric layer 210 in which the gate has been formed.
The charging transistor 231 has a source 234 and a drain 236 in the next or second metal layer 212. The source 234 connects to the via 232 from the gate of the sensing transistor. A second AOS layer 240 is formed as a channel in the dielectric layer 214 and between the source and the drain. As in the sensing transistor, the charging transistor has an AOS layer 240 to serve as a channel, a high K dielectric layer 242 over the AOS layer and a metal layer 246 over the high K dielectric to form the gate. For this transistor a different AOS material may be selected such as IGZO for still lower leakage.
The charging transistor stores charge in the connection 232 between the source of the charging transistor and the gate of the sensing transistor. In this example, the connection is a via through the dielectric. By using a very low leakage gate in the charging transistor, the stored charge is maintained longer for a lower refresh rate.
The metal gate 246 above the storage node 232 is coupled through another via 248 to a connection pad 250 on the metal layer 216 above the gate. This connection pad serves as the gate electrode for connection to the WWL. The metal layer is used for routing the WWL, connecting to other memory cells, and connecting to the write circuitry and controllers. These controllers may be in the logic circuitry 206 below the metal layers or in another location. Other vias 252 may be used to connect other components to form the memory array. Addressing, refresh, and read circuity may be formed in the logic circuitry 206 below the memory array and be connected to the metal layers using vertical vias 252.
This all AOS memory cell allows for a stackable memory array in the backend for 3D vertical embedded circuit integration that is compatible with logic processes. The higher mobility AOS will also allow for faster reading of the memory value stored in the storage node.
Figure 4 is a cross-sectional side view diagram of an alternative structure for the all AOS
2T memory cell of Figure 3. The structure is similar in that the source and drain contacts for the two transistors 262, 264 are formed in metal layers of the BEOL. Metal gates 266, 272 are formed in the dielectric layers between the metal layers. An AOS channel 270, 276 is formed over the source and drain and is isolated from the metal gate by a high K dielectric 268, 274.
In the example of Figure 4, the AOS channel and the high K dielectric are in horizontal layers only. In the example of Figure 3, both the AOS channel 226, 240 and the high K dielectric 228, 242 wrap around the sides of the metal gate. The bottom of the gate over the source and drain and the sides of the gate within the dielectric layer are covered by these two layers. This is an example of a Damascene-like approach. Rather than using subtractive methods, the films are deposited include a pre-formed trench between the source and the drain. As a result the IGZO channel is deposited without any damage to the film.
Figure 5 is a cross-sectional side view diagram of another alternative 3D vertical configuration for a memory cell in metal layers over silicon logic circuitry (not shown), a bottom metal layer Ml is applied over one or more metal and dielectric (ILD) layers over the logic circuitry. This layer is indicated as Ml, but may be any other layer. A dielectric layer is applied over the bottom metal layer, then another metal layer M2, then ILD, then another metal layer M3. There may be more layers for other purposes above and below the memory cell.
The memory cell is formed of a sensing transistor 282 and a charging transistor 280 coupled together with a via between the first Ml and second M2 metal layers. A source 292 and drain 293 for the sensing transistor 282 are formed of the metal in the top metal layer M3. The source and drain may also serve as contacts for the RBL and RWL and connect to control circuitry and other memory cells in an array.
The gate and channel of the sensing transistor are formed in the dielectric layer above the second metal layer. First the metal gate 288 is deposited over M2. The metal gate is covered with a high K dielectric layer which is then covered in a high mobility metal oxide layer to form the channel. This oxide layer allows for fast reads and low leakage using a material such as ITO or IGO. Conductive vias such as filled copper vias are formed over the gate channel to connect to the source and drain of the sensing transistor in M3. The vias are formed after the gate has been formed and then the source and drain are formed by patterning the metal layer M3 over the vias.
The charging transistor 280 has a source 287 and a drain 291 formed by patterning the second metal layer M2. The metal gate 288 of the sensing transistor is formed directly over the source 287 of the charging transistor although there may be a via formed in between depending on the particular design needs. As a result the storage node for the charging transistor 280 is in this source node 287 and a via between the source node and the charging transistor gate channel 285.
The gate electrode 290 of the charging transistor is formed in the first metal layer Ml and the charging transistor gate is formed directly over and in contact with this electrode. As with the sensing transistor gate, there may be a via (not shown) in between the two to suit particular transistor designs and dimension. The charging transistor gate may be formed by first depositing the gate metal 283 over the patterned gate 290 in Ml, then a high K dielectric 284 over the metal and a metal oxide semiconductor 285 as a channel over the dielectric. The oxide channels for both transistors may be covered in an oxynitride or other protective layer 286 before being covered in the ILD up to the next metal layer. Vias are formed over the channel through the ILD up to the next metal layer M2. The source 287 and drain 291 of the charging transistor are formed in the next metal layer M2 over these vias.
The charging transistor channel may be formed of a different metal oxide semiconductor material, such as IGZO, for still lower leakage. By using a very low leakage gate in the charging transistor, the stored charge is maintained in the source node 287 longer for a lower refresh rate.
The gate electrode 290 in the first metal layer serves as a connection pad for connection to the WWL. The first metal layer is used for routing the WWL, connecting to other memory cells, and connecting to the write circuitry and controllers which may be in the logic circuitry below the metal layers or in another location.
Figure 6 is a process flow diagram for forming a 2T memory cell array in BEOL layers as shown in Figures 3, 4 and 5. At 502 the bottom layer metal lines are patterned to form the source and drain for the read transistor and the RBL and RWL for the memory array. This may be done using a damascene process or any other desired approach. The particular metal lines for the source and drain may depend on the particular implementation as mentioned above. The
RBL and RWL may be at the same layer or at a layer below the source and drain layers and then connected using vias. This is followed at 504 with a CMP (chemical metal planarization) over the metal layers.
At 506 a nitride etch stop layer is applied over the planarized metal and the first dielectric layer is formed over the metal lines. At 508 the dielectric is patterned and etched to form openings for the sensing transistor gate. At 510 the gate layers are deposited into the openings. First, the high speed AOS material, such as IGO or ITO is deposited as a channel. This may be done using CVD (Chemical Vapor Deposition) or in any of a variety of other ways. Next at 512 the high K dielectric which may be applied using ALD (Atomic Layer Deposition) or in any of a variety of other ways is deposited, then at 514 the opening is filled with the metal. A damascene approach may be used. The deposit may be only on the bottom of the opening as shown in Figure 4 or also on the sidewalls as shown in Figure 3. In any case the deposits are blanket layer deposition and the AOS material is in contact with the source and the drain.
At 516, a CMP is applied over the metal fill for the gate layer and then a further layer of nitride etch stop and dielectric is applied over the rest of the gate opening. Another CMP is performed over the second ILD.
At 518, a via is formed over the metal gate by etching openings into the planarized ILD and then filling the opening with copper or another suitable conductor. The next metal layer is then patterned and applied at 520 over the via and the rest of the dielectric to form the source and drain areas of the charging transistor. At 522, the next layer of dielectric is applied over the second metal layer. The metal may first be planarized and protected with a nitride etch stop layer before the next layer of ILD is applied.
At 524 as with the previous metal gate, the dielectric is etched to open areas for the AOS channel and metal gate. In this operation as at 508, the ILD and nitride etch stop layer are removed to expose the metal lines corresponding to the source and drain.
With the gate opening made at 526 a blanket AOS deposition is made using e.g. CVD so that the AOS is in contact with the source and drain of the charging transistor. For the charging transistor, an AOS with a low off state leakage, such as IGZO is chosen to reduce the refresh rate of the memory cell. This is followed at 528 by a blanket high K ALD, which is followed by the metal gate deposition at 530.
At 532 CMP is used again to planarize the metal of the gate. A nitride etch stop deposition is performed over the gate metal at 534 then ILD is deposited to form the level of the next metal layer. The ILD is planarized and then the via to the metal gate is formed.
At 536 openings are etched for vias to the metal gate and to the lower metal layers for any other desired connections and at 538 these are filled with a conductor. Finally at 540 the next metal layer with a gate electrode and any other routing such as WWL and WBL are formed in the next metal layer. These operations may be performed simultaneously for thousands or millions of memory cells in the same layers at the same time to produce a memory array that is very close to the logic circuitry and which does not add to the area of the die, only the height. If the array is formed in metal layers that are otherwise required, then the height also is not increased.
At 542 after the metal layers and ILD have been formed with an embedded memory array and any other components, then the die is finished with routing layers, contact pads, solder balls and any other desired components. Additional operations may also be applied to the back side of the die, such as thinning, applying heat spreaders and other operations.
Figure 7 illustrates a computing device 11 in accordance with one implementation. The computing device 11 houses a board 2. The board 2 may include a number of components, including but not limited to a processor 4 and at least one communication chip 6. The processor 4 is physically and electrically coupled to the board 2. In some implementations the at least one communication chip 6 is also physically and electrically coupled to the board 2. In further implementations, the communication chip 6 is part of the processor 4.
Depending on its applications, computing device 11 may include other components that may or may not be physically and electrically coupled to the board 2. These other components include, but are not limited to, volatile memory (e.g., DRAM) 8, non-volatile memory (e.g., ROM) 9, flash memory (not shown), a graphics processor 12, a digital signal processor (not shown), a crypto processor (not shown), a chipset 14, an antenna 16, a display 18 such as a touchscreen display, a touchscreen controller 20, a battery 22, an audio codec (not shown), a video codec (not shown), a power amplifier 24, a global positioning system (GPS) device 26, a compass 28, an accelerometer (not shown), a gyroscope (not shown), a speaker 30, a camera 32, and a mass storage device (such as hard disk drive) 10, compact disk (CD) (not shown), digital versatile disk (DVD) (not shown), and so forth). These components may be connected to the system board 2, mounted to the system board, or combined with any of the other components.
The communication chip 6 enables wireless and/or wired communications for the transfer of data to and from the computing device 11. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 6 may implement any of a number of wireless or wired standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, Ethernet derivatives thereof, as well as any other wireless and wired protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 11 may include a plurality of communication chips 6. For instance, a first communication chip 6 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second
communication chip 6 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
In some implementations, the integrated circuit die of the processor, memory devices, communication devices, or other components are fabricated to include two transistor memory cells with an AOS as described herein. The described memory cells may be embedded as memory for other components in a CMOS or other logic processing die or a standalone memory array may be made on its own die. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
In various implementations, the computing device 11 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 11 may be any other electronic device that processes data including a wearable device.
Embodiments may be implemented as a part of one or more memory chips, controllers, CPUs (Central Processing Unit), microchips or integrated circuits interconnected using a motherboard, an application specific integrated circuit (ASIC), and/or a field programmable gate array (FPGA).
References to "one embodiment", "an embodiment", "example embodiment", "various embodiments", etc., indicate that the embodiment(s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Further, some embodiments may have some, all, or none of the features described for other embodiments.
In the following description and claims, the term "coupled" along with its derivatives, may be used. "Coupled" is used to indicate that two or more elements co-operate or interact with each other, but they may or may not have intervening physical or electrical components between them.
As used in the claims, unless otherwise specified, the use of the ordinal adjectives "first", "second", "third", etc., to describe a common element, merely indicate that different instances of like elements are being referred to, and are not intended to imply that the elements so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.
The drawings and the forgoing description give examples of embodiments. Those skilled in the art will appreciate that one or more of the described elements may well be combined into a single functional element. Alternatively, certain elements may be split into multiple functional elements. Elements from one embodiment may be added to another embodiment. For example, orders of processes described herein may be changed and are not limited to the manner described herein. Moreover, the actions of any flow diagram need not be implemented in the order shown; nor do all of the acts necessarily need to be performed. Also, those acts that are not dependent on other acts may be performed in parallel with the other acts. The scope of embodiments is by no means limited by these specific examples. Numerous variations, whether explicitly given in the specification or not, such as differences in structure, dimension, and use of material, are possible. The scope of embodiments is at least as broad as given by the following claims.
The following examples pertain to further embodiments. The various features of the different embodiments may be variously combined with some features included and others excluded to suit a variety of different applications. Some embodiments pertain to a memory cell structure that includes a sensing transistor having a source and a drain in a first metal layer and a gate between the source and the drain, wherein the gate has a channel between and coupled to the source and the drain, the channel formed of an metal oxide semiconductor material, a charging transistor having a source and a drain in a second metal layer and a gate between the source and the drain, wherein the gate has a channel between and coupled to the source and the drain, the channel formed of metal oxide semiconductor material, wherein the source of the charging transistor is coupled to the gate of the sensing transistor, and a gate electrode in a third metal layer coupled to the gate of the charging transistor.
In further embodiments the metal oxide semiconductor material of the sensing transistor is selected as a high speed material.
In further embodiments the metal oxide semiconductor material of the sensing transistor is an indium gallium oxide or an indium tin oxide.
In further embodiments the metal oxide semiconductor material of the charging transistor is selected as a low off state leakage material.
In further embodiments the metal oxide semiconductor material of the charging transistor is an indium gallium zinc oxide.
Further embodiments include an interlayer dielectric between the first metal layer and the second metal layer and wherein the gate of the sensing transistor is in the interlayer dielectric.
Further embodiments include a conductive via through the interlayer dielectric coupled to the gate of the sensing transistor and to the source of the charging transistor, the via forming a storage node of the charging transistor.
Further embodiments include a conductive via over the charging transistor gate, wherein the gate of the charging transistor further comprises a dielectric over the metal oxide
semiconductor and a metal over the dielectric, and wherein the gate electrode is coupled to the metal of the gate through the conductive via.
In further embodiments the first metal layer on a semiconductor die over logic circuitry of the die, wherein the second metal layer is over the first metal layer, and wherein the third metal layer is over the second metal layer.
Further embodiments include a read bit line and a read word line in the first metal layer and a write bit line and a write word line in the third metal layer.
Some embodiments pertain to a method that includes patterning a first metal layer to form a source and a drain, of a sensing transistor over logic circuitry on a semiconductor die, applying a first interlayer dielectric (ILD) over the first metal layer, depositing a high speed amorphous oxide semiconductor metal oxide semiconductor material into an opening in the first ILD as a sensing transistor gate channel, depositing a metal over the metal oxide semiconductor as a gate, forming a via over the gate, patterning a second metal layer to form a source and a drain of a charging transistor over the gate of the sensing transistor wherein the source of the charging transistor is coupled to the via, applying a second ILD over the second metal layer; depositing a low off state leakage metal oxide semiconductor material in an opening in the second ILD as charging transistor gate channel, depositing a metal over the charging transistor gate channel as a gate, forming a second via over the charging transistor gate, and patterning a third metal layer with a gate electrode coupled to the second via.
In further embodiments the high speed metal oxide semiconductor OS material is an indium gallium oxide or an indium tin oxide.
In further embodiments the low off state leakage metal oxide semiconductor material is an indium gallium zinc oxide.
Further embodiments include depositing a high K dielectric over the high speed metal oxide semiconductor material before depositing the metal.
In further embodiments depositing a low off state leakage metal oxide semiconductor material comprises a damascene process to deposit the metal oxide semiconductor material in a pre-formed trench between the source and drain.
Some embodiments pertain to a computing system that includes a memory having instructions stored thereon, and a processor coupled to the memory to execute the instructions, the processor having silicon logic circuitry formed on a silicon substrate and embedded memory, the embedded memory having a sensing transistor having a source and a drain in a first metal layer and a gate between the source and the drain, wherein the gate has a channel between and coupled to the source and the drain, the channel formed of a metal oxide semiconductor material, a charging transistor having a source and a drain in a second metal layer and a gate between the source and the drain, wherein the gate has a channel between and coupled to the source and the drain, the channel formed of a metal oxide semiconductor material, wherein the source of the charging transistor is coupled to the gate of the sensing transistor, and a gate electrode in a third metal layer coupled to the gate of the charging transistor.
Further embodiments include an interlayer dielectric between the first metal layer and the second metal layer and wherein the sensing transistor gate channel is formed of indium gallium oxide or indium tin oxide is in the interlayer dielectric.
Further embodiments include a conductive via through the interlayer dielectric coupled to the gate of the sensing transistor and to the source of the charging transistor, the via forming a storage node of the charging transistor. Further embodiments include a read word line coupled to the first metal layer, a write bit line in the second metal layer and a write word line in the third metal layer and wherein the read word line, the write bit line and the write word line are each coupled to the logic circuitry.
In further embodiments the embedded memory comprises a plurality of sensing transistors and charging transistors in an array coupled to a shared write bit line and a shared write word line.

Claims

1. A memory cell comprising:
a sensing transistor having a source and a drain in a first metal layer and a gate between the source and the drain, wherein the gate has a channel between and coupled to the source and the drain, the channel formed of an metal oxide semiconductor material;
a charging transistor having a source and a drain in a second metal layer and a gate between the source and the drain, wherein the gate has a channel between and coupled to the source and the drain, the channel formed of metal oxide semiconductor material, wherein the source of the charging transistor is coupled to the gate of the sensing transistor; and
a gate electrode in a third metal layer coupled to the gate of the charging transistor.
2. The memory cell of Claim 1, wherein the metal oxide semiconductor material of the sensing transistor is selected as a high speed material.
3. The memory cell of Claim 1 or 2, wherein the metal oxide semiconductor material of the sensing transistor is an indium gallium oxide or an indium tin oxide.
4. The memory cell of any one or more of claims 1-3, wherein the metal oxide semiconductor material of the charging transistor is selected as a low off state leakage material.
5. The memory cell of any one or more of claims 1-4, wherein the metal oxide semiconductor material of the charging transistor is an indium gallium zinc oxide.
6. The memory cell of any one or more of claims 1-5, further comprising an interlayer dielectric between the first metal layer and the second metal layer and wherein the gate of the sensing transistor is in the interlayer dielectric.
7. The memory cell of Claim 6, further comprising a conductive via through the interlayer dielectric coupled to the gate of the sensing transistor and to the source of the charging transistor, the via forming a storage node of the charging transistor.
8. The memory cell of any one or more of claims 1-7, further comprising a conductive via over the charging transistor gate, wherein the gate of the charging transistor further comprises a dielectric over the metal oxide semiconductor and a metal over the dielectric, and wherein the gate electrode is coupled to the metal of the gate through the conductive via.
9. The memory cell of any one or more of claims 1-8, wherein the first metal layer on a semiconductor die over logic circuitry of the die, wherein the second metal layer is over the first metal layer, and wherein the third metal layer is over the second metal layer.
10. The memory cell of any one or more of claims 1-9, further comprising a read bit line and a read word line in the first metal layer and a write bit line and a write word line in the third metal layer.
11. A method comprising:
patterning a first metal layer to form a source and a drain, of a sensing transistor over logic circuitry on a semiconductor die;
applying a first interlayer dielectric (ILD) over the first metal layer;
depositing a high speed amorphous oxide semiconductor metal oxide semiconductor material into an opening in the first ILD as a sensing transistor gate channel;
depositing a metal over the metal oxide semiconductor as a gate;
forming a via over the gate;
patterning a second metal layer to form a source and a drain of a charging transistor over the gate of the sensing transistor wherein the source of the charging transistor is coupled to the via;
applying a second ILD over the second metal layer;
depositing a low off state leakage metal oxide semiconductor material in an opening in the second ILD as charging transistor gate channel;
depositing a metal over the charging transistor gate channel as a gate;
forming a second via over the charging transistor gate; and
patterning a third metal layer with a gate electrode coupled to the second via.
12. The method of Claim 11, wherein the high speed metal oxide semiconductor OS material is an indium gallium oxide or an indium tin oxide.
13. The method of Claim 11 or 12, wherein the low off state leakage metal oxide semiconductor material is an indium gallium zinc oxide.
14. The method of any one or more of claims 11-13, further comprising depositing a high K dielectric over the high speed metal oxide semiconductor material before depositing the metal.
15. The method of any one or more of claims 11-14, wherein depositing a low off state leakage metal oxide semiconductor material comprises a damascene process to deposit the metal oxide semiconductor material in a pre-formed trench between the source and drain.
16. A computing system comprising:
a memory having instructions stored thereon; and
a processor coupled to the memory to execute the instructions, the processor having silicon logic circuitry formed on a silicon substrate and embedded memory, the embedded memory having a sensing transistor having a source and a drain in a first metal layer and a gate between the source and the drain, wherein the gate has a channel between and coupled to the source and the drain, the channel formed of a metal oxide semiconductor material, a charging transistor having a source and a drain in a second metal layer and a gate between the source and the drain, wherein the gate has a channel between and coupled to the source and the drain, the channel formed of a metal oxide semiconductor material, wherein the source of the charging transistor is coupled to the gate of the sensing transistor, and a gate electrode in a third metal layer coupled to the gate of the charging transistor.
17. The computing system of Claim 16, further comprising an interlayer dielectric between the first metal layer and the second metal layer and wherein the sensing transistor gate channel is formed of indium gallium oxide or indium tin oxide is in the interlayer dielectric.
18. The memory cell of Claim 17, further comprising a conductive via through the interlayer dielectric coupled to the gate of the sensing transistor and to the source of the charging transistor, the via forming a storage node of the charging transistor.
19. The computing system of any one or more of claims 16-18, further comprising a read word line coupled to the first metal layer, a write bit line in the second metal layer and a write word line in the third metal layer and wherein the read word line, the write bit line and the write word line are each coupled to the logic circuitry.
20. The computing system of Claim 19, wherein the embedded memory comprises a plurality of sensing transistors and charging transistors in an array coupled to a shared write bit line and a shared write word line.
PCT/US2016/040764 2016-07-01 2016-07-01 Two transistor memory cell using high mobility metal oxide semiconductors WO2018004667A1 (en)

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