HRP20170015T1 - Integrirani mram cache modul - Google Patents

Integrirani mram cache modul Download PDF

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Publication number
HRP20170015T1
HRP20170015T1 HRP20170015TT HRP20170015T HRP20170015T1 HR P20170015 T1 HRP20170015 T1 HR P20170015T1 HR P20170015T T HRP20170015T T HR P20170015TT HR P20170015 T HRP20170015 T HR P20170015T HR P20170015 T1 HRP20170015 T1 HR P20170015T1
Authority
HR
Croatia
Prior art keywords
mram
main memory
memory
integrated circuit
module
Prior art date
Application number
HRP20170015TT
Other languages
English (en)
Inventor
Xiangyu DONG
Jung Pill Kim
Jungwon Suh
Original Assignee
Qualcomm Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Publication of HRP20170015T1 publication Critical patent/HRP20170015T1/hr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5643—Multilevel memory comprising cache storage devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)
  • Semiconductor Memories (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Claims (15)

1. Integralni krug (200) koji sadrži: procesor (202a, 202b, 202c, 202d) magnetorezistivni (MRAM) memorijski modul sa slučajnim pristupom (218, 318) koji sadrži MRAM cache (208a, 208b, 308a, 308b) posljednje razine i MRAM glavnu memoriju (212, 312); naznačen time, što je procesor (202a, 202b, 202c, 202d) integriran na prvom čipu (216) dok je MRAM modul integriran na drugom čipu (218) sa sučeljem (214) između prvog čipa (216) i drugog čipa (218), gdje je sučelje (214) konfigurirano tako da poveže procesor (202a, 202b, 202c, 202d) i MRAM modul (218, 318).
2. Integralni krug prema Zahtjevu 1, naznačen time što MRAM modul dalje sadrži logiku memorijskog kontrolera.
3. Integralni krug prema Zahtjevu 1, naznačen time što je MRAM modul proizveden u vidu monolitnog paketa.
4. Integralni krug prema Zahtjevu 1, naznačen time što je MRAM modul proizveden kao veći broj paketa.
5. Integralni krug prema Zahtjevu 1, naznačen time što MRAM cache memorija posljednje razine i MRAM glavna memorija sadrže STT-MRAM (Spin Transfer Torque MRAM) bit ćelije.
6. Integralni krug prema Zahtjevu 1, naznačen time što je MRAM glavna memorija podijeljena u dva ili više stogova glavne memorije i gdje je MRAM cache memorija posljednje razina podijeljena u dva ili više stogova cache memorije posljednje razine, i gdje su dva ili više stogova cache memorije posljednje razine formirani u vidu ekstenzije dva ili više stogova glavne memorije.
7. Integralni krug prema Zahtjevu 1, naznačen time što je MRAM modul formiran u dvodimenzionalnoj (2D) arhitekturi koja sadrži MRAM glavnu memoriju u središnjem dijelu i MRAM cache memoriju posljednje razine formiranu na prvoj vanjskom rubu MRAM glavne memorije.
8. Integralni krug prema Zahtjevu 7, koji dalje sadrži logički sloj formiran u drugom vanjskom rubu MRAM glavne memorije.
9. Integralni krug prema Zahtjevu 1, naznačen time što je MRAM modul formiran u trodimenzionalnoj (3D) homogenoj arhitekturi koja sadrži MRAM glavnu memoriju formiranu u jednoj ili više ravnina glavne memorije i MRAM cache memoriju posljednje razine koja je integrirana u jednoj ili u više ravnina glavne memorije.
10. Integralni krug prema Zahtjevu 7, koji dalje sadrži logički sloj formiran u ravnini logičkog sloja koja je paralelna u odnosu na jednu ili više ravnina glavne memorije.
11. Integralni krug prema Zahtjevu 1, naznačen time što je MRAM modul formiran u trodimenzionalnoj (3D) heterogenoj arhitekturi koja sadrži MRAM glavnu memoriju formiranu u jednoj ili više ravnina glavne memorije, i gdje su MRAM cache memorija posljednje razine i logički sloj integrirani u heterogenoj ravnini paralelnoj u odnosu na jednu ili više ravnina glavne memorije.
12. Integralni krug prema Zahtjevu 1, integriran u uređaj, odabran iz grupe koja sadrži set-top uređaje, muzičke plejere, video plejere, jedinice za zabavu, navigacijske uređaje, komunikacijske uređaje, PDA uređaje, jedinice sa podacima na fiksnim lokacijama i računala.
13. Postupak formiranja integralnog kruga (200), gdje postupak sadrži: integriranje procesora (202a, 202b, 202c, 202d); i integriranje MRAM modula (218, 318) koji sadrži MRAM cache memoriju (208a, 208b, 308a, 308b) posljednje razine i MRAM glavnu memoriju (212, 312); naznačen time, što se integriranje procesora (202a, 202b, 202c, 202d) vrši na prvom čipu (216) a MRAM modula (218, 318) koji sadrži MRAM cache memoriju (208a, 208b, 308a, 308b) posljednje razine i MRAM glavnu memoriju (212, 312) na drugom čipu; i formiranje sučelja (214) između prvog čipa (216) i drugog čipa (218), gdje sučelje (214) povezuje procesor (202a, 202b, 202c, 202d) i MRAM modul (218, 318).
14. Postupak prema Zahtjevu 13, koji dalje sadrži integriranje logike memorijskog kontrolera i cache kontrolera na drugom čipu.
15. Postupak prema Zahtjevu 13, naznačen time što MRAM cache memorija posljednje razine i MRAM glavna memorija sadrže STT-MRAM (Spin Transfer Torque MRAM) bit ćelije.
HRP20170015TT 2012-12-20 2017-01-05 Integrirani mram cache modul HRP20170015T1 (hr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/721,092 US9378793B2 (en) 2012-12-20 2012-12-20 Integrated MRAM module
EP13822034.8A EP2936493B1 (en) 2012-12-20 2013-12-20 Integrated mram cache module
PCT/US2013/076994 WO2014100619A1 (en) 2012-12-20 2013-12-20 Integrated mram cache module

Publications (1)

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HRP20170015T1 true HRP20170015T1 (hr) 2017-02-24

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Application Number Title Priority Date Filing Date
HRP20170015TT HRP20170015T1 (hr) 2012-12-20 2017-01-05 Integrirani mram cache modul

Country Status (8)

Country Link
US (1) US9378793B2 (hr)
EP (1) EP2936493B1 (hr)
JP (1) JP6096929B2 (hr)
CN (1) CN104871248B (hr)
HR (1) HRP20170015T1 (hr)
RS (1) RS55452B1 (hr)
SM (1) SMT201700040B (hr)
WO (1) WO2014100619A1 (hr)

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Also Published As

Publication number Publication date
CN104871248A (zh) 2015-08-26
JP2016502223A (ja) 2016-01-21
US20140177325A1 (en) 2014-06-26
EP2936493A1 (en) 2015-10-28
WO2014100619A1 (en) 2014-06-26
EP2936493B1 (en) 2016-10-12
CN104871248B (zh) 2017-10-20
SMT201700040B (it) 2017-03-08
RS55452B1 (sr) 2017-04-28
JP6096929B2 (ja) 2017-03-15
US9378793B2 (en) 2016-06-28

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