CN104409360A - 薄膜晶体管与其形成方法 - Google Patents
薄膜晶体管与其形成方法 Download PDFInfo
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- CN104409360A CN104409360A CN201410742453.1A CN201410742453A CN104409360A CN 104409360 A CN104409360 A CN 104409360A CN 201410742453 A CN201410742453 A CN 201410742453A CN 104409360 A CN104409360 A CN 104409360A
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Classifications
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
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Abstract
本发明提供一种薄膜电晶体晶体管与其形成方法。本发明提供的薄膜晶体管,包括栅极位于基板上。栅极介电层位于栅极与基板上,且源极/漏极位于栅极两侧的栅极介电层上。沟道层位于栅极中间部分的栅极介电层上,且沟道层接触源极/漏极。绝缘盖层覆盖沟道层,其中沟道层包括氧化物半导体。
Description
本申请是2011年1月28日申请的,申请号为201110037245.8,发明名称为“薄膜晶体管与其形成方法”的中国发明专利申请的分案申请
技术领域
本发明是关于薄膜晶体管,更特别关于氧化物半导体作为沟道层的结构及方法。
背景技术
在薄膜晶体管(TFT)的工艺中,氧化物半导体(oxide semiconductor)的开发愈来愈受到重视,在日商与韩商已是列为重点开发项目之一。氧化物半导体可为氧化锌(ZnO)、氧化镓锌(GZO)、氧化铝锌(AZO)、氧化锌锡(ZTO)、氧化铟锌(IZO)、及氧化铟镓锌(IGZO)等等。氧化物半导体用于元件制作上,已有背沟道蚀刻(BCE)五道掩模工艺、倒栅极共平面型五道掩模工艺、与采用蚀刻停止层的六道掩模工艺。上述工艺中,六道掩模工艺的蚀刻停止层可保护沟道层,所得到的元件特性表现皆较五道掩模者为佳,但需多一道掩模。以五道掩模工艺而言,倒栅极共平面型五道掩模工艺可独立定义各层,较不受蚀刻选择特性限制,对面板制造商而言所需进行的变更最少,较具量产优势。但以未来大面积面板所需的铜金属工艺搭配氧化物半导体技术组合,在保护层覆盖铜金属层前,需以还原气氛的等离子(如氢气等离子)将金属表面的氧化物还原为铜。然而氧化物半导体对于还原气氛等离子极为敏感,将造成元件失效。
综上所述,目前亟需一种新颖工艺,在不增加掩模数目的情况下,有效保护沟道层不受后续工艺如还原等离子损害。
发明内容
本发明一实施例提供一种薄膜晶体管的形成方法,包括形成栅极于基板上;形成栅极介电层于栅极与基板上;形成源极/漏极于栅极两侧的栅极介电层上;形成氧化物半导体层于源极/漏极与栅极介电层上;形成绝缘层于氧化物半导体层上,该绝缘层是一无机材料,且形成该绝缘层的方法包括直接沉积该无机材料于该氧化物半导体层上;图案化绝缘层与氧化物半导体层,形成绝缘盖层覆盖沟道层;形成一保护层于该绝缘盖层、该源极/漏极、与该栅极介电层上,且该保护层接触该绝缘盖层的上表面;形成一接触孔穿过该保护层以露出部分该漏极;以及形成一导电图案于该保护层上以作为一像素电极,且该导电图案经该接触孔接触该漏极,其中该源极/漏极的材质包括铜,且在形成该绝缘盖层覆盖该沟道层的步骤后与形成该保护层的步骤前,进行一还原该源极/漏极的步骤。
本发明另一实施例提供一种薄膜晶体管,包括:栅极,位于基板上;栅极介电层,位于栅极与基板上;源极/漏极,位于栅极两侧的栅极介电层上;沟道层,位于栅极中间部分的栅极介电层上,且沟道层接触源极/漏极;绝缘盖层,覆盖沟道层,该绝缘盖层包括一有机材料或一无机材料,该无机材料包括氧化硅、氮化硅、氮氧化硅、氧化铝、氧化钛、氧化铪、或氮化铝;一保护层,位于该绝缘盖层、该源极/漏极、与该栅极介电层上,且该保护层接触该绝缘盖层的上表面;一接触孔,穿过该保护层以露出部分该漏极;以及一导电图案,位于该保护层上以作为一像素电极,且该导电图案经该接触孔接触该漏极;其中该源极/漏极的材料包括铜,该沟道层包括氧化物半导体。
附图说明
为让本发明的上述目的、特征和优点能更明显易懂,以下结合附图对本发明的具体实施方式作详细说明,其中:
图1A-1B、2A-2B、3A-3C、4A-4D、5A及6A是本发明某些实施例中,薄膜晶体管的工艺剖视图;以及
图1C、2C、3D、5B及6B是本发明某些实施例中,薄膜晶体管的工艺上视图。
主要元件符号说明:
A-A’~剖面线;
10~基板;
12~图案化金属层;
14~栅极介电层;
16~金属层;
16A~源极;
16B~漏极;
18、36~图案化光阻层;
32~氧化物半导体层;
34~绝缘层;
37~绝缘盖层;
38~沟道层;
54~接触孔;
62~导电图案。
具体实施方式
下列说明中的实施例将描述如何形成并使用薄膜晶体管。必需理解的是,这些实施例提供多种可行的发明概念,并可应用于多种特定内容中。特定实施例仅用以说明形成及使用实施例的特定方式,并非用以局限本发明的范围。
如图1A所示,形成图案化金属层12于基板10上。基板10可为透光(如玻璃、石英、或类似物)或不透光(如晶片、陶瓷、或类似物)的刚性无机材质,亦可为塑胶、橡胶、聚酯、或聚碳酸酯等可挠性有机材质。在某些实施例中的基板10采用透光材质,最后形成的薄膜晶体管可应用于穿透式、半穿反、或反射式液晶显示器。在其他实施例中的基板10采用不透光或透光性不佳的材质,最后形成的薄膜晶体管只能应用于反射式液晶显示器,或自发光显示器上。
上述图案化金属层12的材质可为金属、合金、或上述的多层结构。在某些实施例中,图案化金属层12为钼、铝、铜、钛等单层或多层组合的金属或合金。图案化金属层12的形成方法可为形成金属层于基板10上,再以光刻图案化工艺搭配蚀刻法形成图案化金属层12。金属层的形成方法可为物理气相沉积法(PVD)、溅镀法、或类似方法。光刻图案化工艺可为下述步骤:涂布光阻如旋涂法、软烘烤、对准掩模、曝光、曝光后烘烤、显影、冲洗、干燥如硬烘烤、其他合适工艺、或上述的组合。此外,光刻的曝光工艺可改用其他方法如无掩模光刻、电子束直写、或离子束直写。蚀刻工艺可为干蚀刻、湿蚀刻、或上述的组合。虽然在后述的图1C中,图案化金属层12只作为薄膜晶体管的栅极以及与的相连的栅极线,但图案化金属层12亦可作为接触垫、储存电容的下电极、或其他元件,端视需要而定。
如图1B所示,接着形成介电层14于图案化金属层12上。介电层14的组成可为有机材质如有机硅氧化合物,或无机材质如氮化硅、氧化硅、氮氧化硅、碳化硅、氧化铝、氧化铪、或上述材质的多层结构。介电层14的形成方法可为化学气相沉积法(CVD)如等离子增强式CVD(PECVD)、低压CVD(LPCVD)、次常压CVD(SACVD)、物理气相沉积(PVD)、或类似技术。虽然在后述的图1C中,介电层14仅作为薄膜晶体管栅极介电层,但介电层14亦可作为储存电容的电容介电层或其他元件,视需要而定。可以理解的是,图1C中剖面线A-A’的剖视图即图1B所示的结构。
如图2A所示,形成另一金属层16于介电层14上。金属层16的材质可为金属、合金、或上述的多层结构。在某些实施例中,金属层16为铜或铜合金。在其他实施例中,金属层16不含铜,比如钼/铝/钼的多层结构、或钼/铝/钛多层或单层金属或合金。金属层16的形成方法可为电镀法、无电电镀法、PVD、溅镀法、或类似方法。
如图2B所示,形成图案化光阻层18于金属层16上,其形成方法可为光刻图案化工艺如上述,在此不赘述。以图案化光阻层18作遮罩蚀刻金属层16,即形成源极16A与漏极16B。蚀刻方法可为干蚀刻、湿蚀刻、或上述的组合。之后可移除图案化光阻层18,移除方法可为湿式去光阻剥膜液去除或光阻灰化。虽然在后述的图2C中,金属层16在图案化后作为薄膜晶体管的源极/漏极16A/16B与源极线,但亦可作为其他线路或其他元件,视需要而定。可以理解的是,图2C中剖面线A-A’的剖视图即图2B移除图案化光阻层18后所示的结构。
如图3A所示,形成氧化物半导体层32于图2B移除图案化光阻层18后的结构上,再形成绝缘层34于氧化物半导体层32上。在一实施例中,氧化物半导体层32的组成可为氧化锌、氧化铟、铟镓锌氧化物、或氧化锡。在其他实施例中,氧化物半导体层32可为氧化锌、氧化铟、铟镓锌氧化物、氧化锡、氧化镓、氧化铝、及氧化钛中至少两者的组合。氧化物半导体层32的形成方法可为CVD如PECVD、LPCVD、SACVD、物理与气相沉积(PVD)、溶液合成方式沉积、或类似方法。在本发明一实施例中,绝缘层34的组成可为有机材料如压克力系材料,其形成方法可为旋转涂布法、狭缝涂布法、浸泡法、或其他类似方法。在本发明另一实施例中,绝缘层34的组成可为无机材料如氧化硅、氮化硅、氮氧化硅、氧化铝、氧化钛、氧化铪、或氮化铝,其形成方法可为溅镀法、CVD如PECVD、LPCVD、或SACVD、或类似沉积方法。在其他实施例中,绝缘层34的组成为钝化金属层如氧化铝、氧化钛、氮化钛、或其他氧化或氮化的金属层,其形成方法是先形成金属层于氧化物半导体体层32上,再以氧气或氮气钝化金属层。不过值得注意的是,钝化金属层需考虑到物质本性。举例来说,氧化铝与氮化铝均为绝缘材料,因此铝的钝化方式可为氧化或氮化。另一方面,氧化钛为绝缘材料但氮化钛仍为导电材料,因此钛的钝化方式只能采用氧化而不能采用氮化。上述步骤需于等压如真空中进行。在本发明一实施例中,形成氧化物半导体层32与绝缘层34的步骤均位于同一反应腔中进行。在本发明其他实施例中,形成氧化物半导体层32与绝缘层34的步骤是于等压系统中的不同反应腔中进行。
如图3B所示,形成图案化光阻层36于绝缘层34上,其形成方法可为光刻图案化工艺如上述,在此不赘述。接着以一段蚀刻工艺移除未被图案化光阻层36覆盖的绝缘层34与氧化物半导体层32,形成绝缘盖层37覆盖沟道层38。上述的一段蚀刻工艺可为干蚀刻如烷类、氢气、氩气、与卤酸等混合气体,或湿蚀刻如氢氟酸。最后移除图案化光阻层36,即形成第3C图所示的结构。
图4A至4D与图3A至3C的工艺类似,唯一差异在于图4A至4D形成绝缘盖层37与沟道层38的蚀刻工艺为分段蚀刻工艺而非一段蚀刻工艺。举例来说,可先进行第一道蚀刻工艺,移除未被图案化光阻层36遮罩的绝缘层34以形成绝缘盖层37,如图4C所示。接着再进行第二道蚀刻工艺,移除未被图案化光阻层36遮罩的氧化物半导体层32以形成沟道层38,再移除图案化光阻层36如图4D所示。第一道蚀刻工艺与第二道蚀刻工艺可针对氧化物半导体层32与绝缘层34的蚀刻选择性,分别采用不同的干蚀刻或湿蚀刻条件。举例来说,可采用一般蚀刻氧化物的气体干蚀刻绝缘层34,再采用草酸或铝酸湿蚀刻氧化物半导体层32。不论采用一段或分段蚀刻工艺,最后都应形成绝缘盖层37覆盖沟道层38的结构。可以理解的是,图3D的剖面线A-A’的剖视图即图3C或图4D所示的结构。
在图3C及图4D的结构中,绝缘盖层37的下表面与沟道层38的上表面两者的宽度实质上相等。但在其他实施例中,绝缘盖层37的上表面宽度可略大于或略小于沟道层38的下表面宽度,且两者的宽度差距约介于0μm至2μm之间。不论如何,绝缘盖层37的下表面较佳与沟道层38的上表面的宽度一致。若宽度差距若超过2μm,将不利后续工艺。
接着可形成保护层52于图3C(或图4D)的结构上。保护层52的组成可为氮化硅、氧化硅、氮氧化硅、碳化硅、氧化铝、氧化钛、氧化铪、或上述材质的多层结构,其形成方式可为CVD、PECVD、或PVD。在本发明一实施例中,在形成保护层52之前,会先以还原性等离子(如氢气等离子)处理图3C(或图4D)的结构表面,以增加保护层52的接着性。特别是在源极/漏极16A/16B的组成含铜时,沟道层38的形成步骤如光刻及蚀刻会氧化源极/漏极16A/16B的表面,因此更需以还原工艺如氢气使源极/漏极16A/16B表面的氧化铜还原为铜。若沟道层38上方未覆盖绝缘盖层37,上述的还原性等离子及/或还原工艺均会还原沟道层38的氧化物半导体,使其形成导体并破坏元件功能。
接着以光刻图案化工艺形成图案化光阻(未图示),再以图案化光阻为遮罩进行蚀刻工艺,即形成接触孔54如图5A所示。可以理解的是,图5B的剖面线A-A’的剖视图即图5A所示的结构。
如图6A所示,形成导电图案62于图5A所示的结构上。导电图案62是形成于保护层52上作为像素电极,并经由接触孔54电性连接至漏极16B。导电图案62的形成方法为先形成导电层后,再以光刻图案化工艺与蚀刻工艺图案化导电层,至此完成薄膜晶体管。若薄膜晶体管是应用于穿透式LCD中,导电图案62的组成可为铟锡氧化物(ITO)、铟锌氧化物(IZO)、铝锌氧化物(AZO)、镉锡氧化物(CTO)、氧化锡(SnO2)、或氧化锌(ZnO)等透明导电材料。若薄膜晶体管应用于反射式LCD中,导电图案62的组成可为铝、金、锡、银、铜、铁、铅、铬、钨、钼、钕、上述的氮化物、上述的氧化物、上述的氮氧化物、上述的合金、或上述的组合。此外,反射式的导电图案62的表面呈现凹凸状,以增加光线的反射及散射的效果。若薄膜晶体管是应用于半穿反LCD中,则分别采用透明组成或反射组成于穿透区或反射区中。
虽然本发明已以较佳实施例揭示如上,然其并非用以限定本发明,任何本领域技术人员,在不脱离本发明的精神和范围内,当可作些许的修改和完善,因此本发明的保护范围当以权利要求书所界定的为准。
Claims (9)
1.一种薄膜晶体管的形成方法,包括:
形成一栅极于一基板上;
形成一栅极介电层于该栅极与该基板上;
形成一源极/漏极于该栅极两侧的该栅极介电层上;
形成一氧化物半导体层于该源极/漏极与该栅极介电层上;
形成一绝缘层于该氧化物半导体层上,该绝缘层是一无机材料,且形成该绝缘层的方法包括直接沉积该无机材料于该氧化物半导体层上;
图案化该绝缘层与该氧化物半导体层,形成一绝缘盖层覆盖一沟道层;
形成一保护层于该绝缘盖层、该源极/漏极、与该栅极介电层上,且该保护层接触该绝缘盖层的上表面;
形成一接触孔穿过该保护层以露出部分该漏极;以及
形成一导电图案于该保护层上以作为一像素电极,且该导电图案经该接触孔接触该漏极,
其中该源极/漏极的材质包括铜,且在形成该绝缘盖层覆盖该沟道层的步骤后与形成该保护层的步骤前,进行一还原该源极/漏极的步骤。
2.如权利要求1所述的薄膜晶体管的形成方法,其特征在于,该绝缘层是一有机材料,且形成该绝缘层的方法包括旋转涂布法、狭缝涂布法、或浸泡法。
3.如权利要求1所述的薄膜晶体管的形成方法,其特征在于,形成该氧化物半导体层于该源极/漏极与该栅极介电层上的步骤与形成该绝缘层于该氧化物半导体层上的步骤是于同一反应腔中进行,或者于等压系统中的不同反应腔中进行。
4.如权利要求1所述的薄膜晶体管的形成方法,其特征在于,图案化该绝缘层与该氧化物半导体层的步骤为一段蚀刻或分段蚀刻。
5.如权利要求4所述的薄膜晶体管的形成方法,其特征在于,该一段蚀刻包括干式蚀刻或湿式湿刻。
6.如权利要求4所述的薄膜晶体管的形成方法,其特征在于,该分段蚀刻包括气体置换的干式蚀刻、蚀刻液置换的湿式蚀刻、或者气体置换的干式蚀刻与蚀刻液置换的湿式蚀刻的组合。
7.一种薄膜晶体管,包括:
一栅极,位于一基板上;
一栅极介电层,位于该栅极与该基板上;
一源极/漏极,位于该栅极两侧的该栅极介电层上;
一沟道层,位于该栅极中间部分的栅极介电层上,且该沟道层接触该源极/漏极;
一绝缘盖层,覆盖该沟道层,该绝缘盖层包括一有机材料或一无机材料,该无机材料包括氧化硅、氮化硅、氮氧化硅、氧化铝、氧化钛、氧化铪、或氮化铝;
一保护层,位于该绝缘盖层、该源极/漏极、与该栅极介电层上,且该保护层接触该绝缘盖层的上表面;
一接触孔,穿过该保护层以露出部分该漏极;以及
一导电图案,位于该保护层上以作为一像素电极,且该导电图案经该接触孔接触该漏极;
其中该源极/漏极的材料包括铜,该沟道层包括一氧化物半导体。
8.如权利要求7所述的薄膜晶体管,其特征在于,该有机材料包括压克力系材料。
9.如权利要求7所述的薄膜晶体管,其特征在于,该绝缘盖层的下表面与该沟道层的上表面两者之间的宽度差距介于0μm至2μm之间。
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KR20140132878A (ko) * | 2013-05-08 | 2014-11-19 | 삼성디스플레이 주식회사 | 박막 트랜지스터 표시판 및 그 제조 방법 |
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2010
- 2010-11-17 TW TW99139500A patent/TWI471946B/zh not_active IP Right Cessation
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2011
- 2011-01-28 CN CN201410742453.1A patent/CN104409360A/zh active Pending
- 2011-01-28 CN CN2011100372458A patent/CN102468340A/zh active Pending
- 2011-11-03 US US13/288,579 patent/US8890145B2/en active Active
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2014
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- 2014-09-05 US US14/478,124 patent/US9076872B2/en active Active
- 2014-09-05 US US14/478,148 patent/US9368631B2/en active Active
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US20140374750A1 (en) | 2014-12-25 |
US20120119211A1 (en) | 2012-05-17 |
US9601519B2 (en) | 2017-03-21 |
CN102468340A (zh) | 2012-05-23 |
US9362408B2 (en) | 2016-06-07 |
US9076872B2 (en) | 2015-07-07 |
US20140377906A1 (en) | 2014-12-25 |
US8890145B2 (en) | 2014-11-18 |
US9368631B2 (en) | 2016-06-14 |
TWI471946B (zh) | 2015-02-01 |
US20140374751A1 (en) | 2014-12-25 |
US20160260748A1 (en) | 2016-09-08 |
TW201222676A (en) | 2012-06-01 |
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