CN104347579A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN104347579A
CN104347579A CN201410374171.0A CN201410374171A CN104347579A CN 104347579 A CN104347579 A CN 104347579A CN 201410374171 A CN201410374171 A CN 201410374171A CN 104347579 A CN104347579 A CN 104347579A
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CN
China
Prior art keywords
transistor
wiring
conductive pattern
upper conductive
unit
Prior art date
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Application number
CN201410374171.0A
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English (en)
Inventor
松本明
三浦喜直
中柴康隆
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Renesas Electronics Corp
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Renesas Electronics Corp
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Publication of CN104347579A publication Critical patent/CN104347579A/zh
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Abstract

本发明公开了一种半导体装置，其中减小了产生自布线的电阻分量。以第一方向(图中y方向)并排地排列多个晶体管单元，多个晶体管单元的每一个具有多个晶体管。所述晶体管的栅极以第一方向延伸。第一源极布线在第一晶体管单元和第二晶体管单元之间延伸，而第一漏极布线在第二晶体管单元和第三晶体管单元之间延伸。第二漏极布线在第一晶体管单元的与第一源极布线延伸的一侧相反的一侧上延伸；而第二源极布线在第三晶体管单元的与第二源极布线延伸的一侧相反的一侧上延伸。

Description

半导体装置
相关申请的交叉引用
通过引用将2013年7月31日提交的日本专利申请No.2013-158833包括其说明书、附图及摘要完整合并至此。
技术领域
本发明涉及半导体装置，更具体地，涉及适用于包括例如晶体管和布线的半导体装置的技术。
背景技术
一种类型的半导体装置具有用于功率控制的晶体管。例如，在日本未审专利公开No.2001-77206中描述了这样的半导体装置。上述未审专利描述了彼此并列的多个晶体管单元。具体地，在每一个晶体管单元中，彼此并列地提供多个晶体管。从每一个晶体管引出漏极布线和源极布线以使其取向在彼此相反的方向。要耦接至漏极布线的部件和要耦接至源极布线的部件两者都布置在晶体管单元之间。
另一方面，近来在发展使用化合物半导体层作为沟道的晶体管。这种晶体管具有导通电阻低的特性。
概述
在具有晶体管的半导体装置中，需要减小导通电阻。该导通电阻包括产生自晶体管的分量和产生自布线的分量。本发明的发明人已经研究了如何降低产生自布线的电阻分量。从本说明书的描述和附图中，其它问题和新颖的特征将变得清楚。
根据一个实施例，一种半导体装置包括第一晶体管单元、第二晶体管单元和第三晶体管单元。这些晶体管单元以该顺序以第一方向并排地排列，每一个晶体管单元具有其栅电极以第一方向延伸的多个晶体管。第一布线在第一晶体管单元和第二晶体管单元之间延伸，并且第二布线在第一晶体管单元的与第一布线所延伸的一侧相反的一侧上延伸；而第三布线在第二晶体管单元和第三晶体管单元之间延伸，并且第四布线在第三晶体管单元的与第三布线所延伸的一侧相反的一侧上延伸。第一布线耦接至第一晶体管单元中的晶体管的源电极，并耦接至第二晶体管单元中的晶体管的源电极。第二布线耦接至第一晶体管单元中的晶体管的漏电极。第三布线耦接至第二晶体管单元中的晶体管的漏电极，并耦接至第三晶体管单元中的晶体管的漏电极。第四布线在第二方向上延伸，并耦接至第三晶体管单元中的晶体管的源电极。
根据实施例，可以降低具有晶体管的半导体装置中的产生自布线的电阻分量。
附图说明
图1是示出根据第一实施例的半导体装置的配置的平面图；
图2是示出晶体管单元的配置的平面图；
图3是示出图2中A-A’剖面的第一例子的图；
图4是示出图2中A-A’剖面的第二例子的图；
图5是示出图2中A-A’剖面的第三例子的图；
图6是示出图2中A-A’剖面的第四例子的图；
图7是沿着图2中的线B-B’截取的剖面图；
图8是示出根据第二实施例的半导体装置的配置的平面图；
图9是图8中示出的半导体装置的剖面图；
图10是示出图8的变体的图；
图11是示出图8的变体的图；
图12是示出包括半导体装置SD的电子装置的配置的图；以及
图13是示出根据第三实施例半导体装置的配置的图；
具体实施方式
下面，将参考附图描述优选的实施例。由相似的附图标记指示在每一个附图中示出的相同或相似的组件，并将适当地省略重复性的描述。
(第一实施例)
图1是示出根据第一实施例的半导体装置SD的配置的平面图。在该图中示出的半导体装置SD包括多个晶体管单元TRU(第一晶体管单元(TRU1)、第二晶体管单元(TRU2)以及第三晶体管单元(TRU3))，多个漏极布线DRI(第二布线和第三布线)，以及多个源极布线(第一布线和第四布线)。
晶体管单元TRU在第一方向(图中的Y方向)并排地排列，每个晶体管单元具有多个晶体管TR(下面将详细描述)。例如，晶体管TR是用于功率控制的晶体管，并且其栅电极(将参考图2描述)以第一方向延伸。
漏极布线DRI和源极布线SOI交替地位于晶体管单元TRU之间，并且以与第一方向交叉的方向(第二方向：图中的X方向)延伸，例如，以与第一方向垂直的方向。换言之，在晶体管单元TRU之间的每隔一个的间隔中形成漏极布线DRI，并在晶体管单元TRU之间的剩余间隔中形成源极布线SOI。换言之，第一源极布线SOI1(第一布线)在第一晶体管单元TRU1和第二晶体管单元TRU2之间延伸，而第一漏极布线DRI1(第三布线)在第二晶体管单元TRU2和第三晶体管单元TRU3之间延伸。第二漏极布线DRI2(第二布线)在第一晶体管单元TRU1的与第一布线SOI1所延伸的一侧相反的一侧上延伸，并且第二源极布线SOI2(第四布线)在第三晶体管单元TRU3的与第一漏极布线DRI1所延伸的一侧相反的一侧上延伸。
包括在第一晶体管单元TUR1中的晶体管TR的源电极SOE和包括在第二晶体管单元TUR2中的晶体管TR的源电极SOE都耦接至第一源极布线SOI1。包括在第一晶体管单元TRU1中的晶体管TR的漏电极DRE耦接至第二漏极布线DRI2。包括在第二晶体管单元TUR2中的晶体管TR的漏电极DRE和包括在第三晶体管单元TUR3中的晶体管TR的漏电极DRE都耦接至第一漏极布线DRI1。包括在第三晶体管单元TRU3中的晶体管TR的源电极SOE耦接至第二源极布线SOI2。
在图中所示的例子中，半导体装置SD仅包括三个晶体管单元TRU，但其也可以包括四个或更多个晶体管单元TRU。在这种情况中，包括在位于第一晶体管单元TRU1旁边的晶体管单元TRU(未示出)中的晶体管TR的漏电极也耦接至第二漏极布线DRI2。另外，包括在位于第三晶体管单元TRU3旁边的晶体管单元TRU(未示出)中的晶体管TR的源电极也耦接至第二源极布线SOI2。
图2是示出晶体管单元TRU的配置的平面图。通过使用衬底SUB形成半导体装置SD。在衬底SUB中形成元件隔离区域EI。元件隔离区域EI将其中形成晶体管TR的区域(此后称为元件形成区域)与其它区域隔离。元件隔离区域EI是例如通过将高浓度的B引入到阻挡层BAR(稍后将参照图3描述)以及沟道层CNL(稍后将参照图3描述)中而提高其电阻的区域。元件隔离区域EI的下端位于缓冲层BUF的表面层之上。
在每一个晶体管单元TRU中提供元件形成区域。在元件形成区域中形成晶体管TR。晶体管TR以第二方向(X方向)排列。晶体管TR中的每一个具有栅电极GE。这些栅电极以第一方向(Y方向)相互平行地延伸。尤其是，元件形成区域可以具有矩形形状。栅电极GE与元件形成区域的短边平行地延伸。由包含例如Au或Al的金属形成栅电极GE。
栅电极GE的两端都位于元件隔离区域EI之上。栅电极的一个端部通过栅极布线GEI耦接至栅极板GEP。在元件隔离区域EI之上形成栅极布线GEI，并且栅极布线GEI以第二方向(X方向)延伸。即，将栅电极GE形成梳状形状。
提供源电极SOE和漏电极DRE交替地设置在栅电极GE之间。换言之，在元件形成区域中，源电极SOE、栅电极GE、漏电极DRE以及栅电极GE以该顺序沿着第二方向(X方向)重复地排列。源电极SOE通过源极布线SOI彼此并联地耦接，而漏电极DRE通过漏极布线DRI耦接到一起。
因为源极布线SOI与源电极SOE是一体的，因此其可以被称为是源电极SOE的一部分。类似地，因为漏极布线DRI与漏电极DRE是一体的，因此其可以被称为是漏电极DRE的一部分。即，在本实施例中，源电极SOE和漏电极DRE分别形成梳状形状。源电极SOE和漏电极DRE分别包括例如Al。
在源极布线SOI延伸的方向(即，图中的X方向)，包括在彼此相邻的两个晶体管单元TRU中的源极布线SOI交替地排列，并且包括在彼此相邻的两个晶体管单元TRU中的漏极布线DRI也交替地排列。
图3是示出图2中A-A’剖面的第一例子的图。衬底SUB具有如下的配置，其中缓冲层BUF、沟道层CNL以及阻挡层BAR以该顺序在衬底SUB2之上外延生长。衬底SUB2是例如P+型体硅衬底。缓冲层BUF是沟道层CNL和衬底层SUB之间的缓冲。缓冲层BUF是化合物半导体层，例如氮化物半导体层，其中重复地层叠AlN/GaN。沟道层CNL是在缓冲层BUF之上外延地生长的层。沟道层CNL包括例如GaN，但也可以包括包含AlGaN等的其他氮化物半导体层。阻挡层BAR由晶格常数与沟道层CNL不同的材料形成。阻挡层BAR包括例如AlGaN。随着形成了阻挡层BAR，在沟道层CNL中产生用作为载流子的二维电子气。
在阻挡层BAR之上形成漏电极DRE和源电极SOE。此外，在，在漏电极DRE和源电极SOE之间的阻挡层BAR的区域之上形成绝缘膜INS2和栅电极GE。在该图所示的例子中，绝缘膜INS2兼作为栅极绝缘膜。在该图所示的例子中，绝缘膜INS2包括例如非晶态的Al2O3或SiO2。在该图所示的例子中，为了确保栅极和漏极之间的耐受电压，栅电极GE和漏电极DRE之间的距离比栅电极GE和源电极SOE之间的距离大。
图4是示出图2中A-A’剖面的第二例子的图。在该图所示的例子中，晶体管TR是MIS-HJ-FET(金属-绝缘体-半导体异质结场效应晶体管)。具体地，栅电极GE的一部分嵌入在绝缘膜INS2中，以通过绝缘膜INS1耦接至阻挡层BAR。绝缘膜INS1还形成在绝缘膜INS2之上，以及绝缘膜INS2和栅电极GE之间。在该图所示的例子中，绝缘膜INS1兼作栅极绝缘膜。在该图所示的例子中，绝缘膜INS2是例如SiN膜。绝缘膜INS1包括例如非晶态的Al2O3或SiO2。在该结构中，形成在沟道层CNL中的二维电子气在栅电极GE下的部分中中断。因此，在将小于阈值的电压施加到栅电极GE的状态下，电流流过沟道层CNL。而当将电压施加到栅电极GE时，电流不流过沟道层CNL。
图5是示出图2中A-A’剖面的第三例子的图。在该图所示的例子中，晶体管TR是MIS-FET(金属-绝缘体-半导体场效应晶体管)，并且是常断(normally-off)型晶体管。具体地，栅电极的一部分穿透绝缘膜INS2以及阻挡层BAR达到沟道层CNL。在绝缘膜INS2、阻挡层BAR和沟道层CNL中的每一个与栅电极GE之间形成绝缘膜INS1。绝缘膜INS1和INS2的配置与图4中的第二例子的配置相同。绝缘膜INS1也兼作栅极绝缘膜。在沟道层CNL中形成的二维电子气被栅电极GE分开。因此，在没有电压施加到栅电极GE的状态下，没有电流流过沟道层CNL。而当将电压施加到栅电极GE时，电流流过沟道层CNL。
图6是示出图2中A-A’剖面的第四例子的图。在该图所示的例子中，晶体管TR是J-FET(结型场效应晶体管)，并且是常断型晶体管。具体地，在阻挡层BAR和栅电极GE之间形成第一导电类型的层SEM。第一导电类型的层SEM包括例如AlGaN。
图7是沿图2中的线B-B’截取的剖面图。绝缘膜INS2还形成在元件隔离区域EI之上。栅极布线GEI位于绝缘膜INS2之上。在绝缘膜INS2和栅极布线GEI之上形成层间绝缘膜INSL1。层间绝缘膜INSL由例如SiN膜形成不在元件形成区域之上形成层间绝缘膜INSL1。在层间绝缘膜INSL1之上形成源极布线SOI和漏极布线DRI。
随后，将描述制造半导体装置SD的方法的例子。首先，在衬底SUB2之上顺序外延生长缓冲层BUF、沟道层CNL以及阻挡层BAR。随后，在阻挡层BAR和沟道层CNL中形成元件隔离区域EI。
随后，通过使用例如CVD方法，在阻挡层BAR和元件隔离区域EI之上形成绝缘膜INS2。随后，通过溅射法在绝缘膜INS2之上形成作为栅电极GE、栅极布线GEI以及栅极板GEP的膜。随后，选择性地去除该膜。从而，形成栅电极GE、栅极布线GEI以及栅极板GEP。随后，通过CVD方法在栅电极GE和绝缘膜INS2之上形成层间绝缘膜INSL1。
随后，在层间绝缘膜INSL1之上形成掩模图案，之后通过利用该掩模图案作为掩模刻蚀层间绝缘膜INSL1。因此，去除层间绝缘膜INSL1位于元件形成区域中的一分。随后，移除掩模图案。
随后，使用例如溅射方法，在层间绝缘膜INSL1以及位于元件形成区域中的阻挡层BAR之上，形成用作为源电极SOE、源极布线SOI、漏电极DRE以及漏极布线DRI的金属膜。随后，选择性地移除该金属膜。从而形成源电极SOE、源极布线SOI、漏电极DRE以及漏极布线DRI。
下面将描述本实施例的优点。根据该实施例，第一源极布线SOI耦接至包括在第一晶体管单元TRUI中的源电极SOE和包括在第二晶体管单元TRU2中的源电极SOE两者。第一漏极布线DRI耦接至包括在第二晶体管TRU2中的漏电极DRE和包括在第三晶体管单元TRU3中的漏电极DRE。因此，在彼此相邻的两个晶体管单元之间可以仅提供漏极布线DRI和源极布线SOI之一。因此，与将两个布线都布置在彼此相邻的两个晶体管单元TRU之间的情况相比，由于不再需在彼此相邻的漏极布线DRI和源极布线SOI之间的空间，因此，可以增大漏极布线DRI或源极布线SOI的宽度。因此，可以减小半导体装置中产生的寄生电阻中的由布线产生的电阻分量。
由其是，在本实施例中在沟道层CNL中形成晶体管TR的沟道。沟道层CNL是化合物半导体层，其电阻低于硅的电阻。在此类情况中，如果布线电阻高，那么即使在减小了晶体管TR的寄生电阻，使用化合物半导体层的意义也变得很小。在本实施例中，因为可以减小由布线产生的电阻分量，所以对于晶体管TR的沟道层使用化合物半导体层的作用变得很大。
(第二实施例)
图8是示出根据第二实施例的半导体装置SD的配置的平面图，并且，图9是图8中示出的半导体装置的剖面图。图8和图9分别对应于第一实施例中的图1和图7。根据本实施例的半导体装置SD包括：多个漏极盘(pad)电极DRP(第二上层导电图案和第三上层导电图案)、多个漏极触点DRC(第二耦接部件和第三耦接部件)、多个源极盘电极SOP(第一上层导电图案和第四上层导电图案)、多个源极触点SOC(第一耦接部件和第四耦接部件)。
在漏极布线DRI和源极布线SOI上方的层中形成源极盘电极SOP和漏极盘电极DRP的每一个，并且源极盘电极SOP和漏极盘电极DRP的每一个的宽度比漏极布线DRI和源极布线SOI的宽度宽。源极盘电极SOP和漏极盘电极DRP以第二方向(图中的X方向)延伸。
如图8中所示出的，源极盘电极SOP的至少部分与源极布线SOI重叠，并且漏极盘电极DRP的至少部分与漏极布线DRI重叠。源极触点SOC位于源极盘电极SOP与源极布线SOI彼此重叠的区域。漏极触点DRC位于漏极盘电极DRP与漏极布线DRI彼此重叠的区域。源极触点SOC将源极布线SOI耦接至源极盘电极SOP，漏极触点DRC将漏极布线DRI耦接至漏极盘电极DRP。提供源极盘电极SOP以减小源极布线SOI的表面电阻，而提供漏极盘电极DRP以降低漏极布线DRI的表面电阻。
如在图9中示出的，在源极布线SOI、漏极布线DRI以及层间绝缘膜INSL1之上形成层间绝缘膜INSL2。层间绝缘膜INSL2是例如氧化硅膜。在层间绝缘膜INSL2之上形成源极盘电极SOP和漏极盘电极DRP，并且源极触点SOC和漏极触点DRC嵌入在层间绝缘膜INSL2中。源极触点SOC可以与源极盘电极SOP一体地形成。类似地，漏极触点DRC可以与漏极盘电极DRP一体地形成。源极盘电极SOP和漏极盘电极DRP由金属(例如Al)形成。
如图8所示，当平面地看时，耦接至第一漏极布线DRI1的漏极盘电极DRP(第一漏极盘电极DRP1)的部分与第一晶体管单元TRU1重叠。耦接至第一源极布线SOI1的源极盘电极SOP(第一源极盘电极SOP1)的一部分与第一晶体管单元TRU1和第二晶体管单元TRU2中的至少一个重叠。耦接至第二漏极布线DRI2的第二漏极盘电极DRP2的一部分与第二晶体管单元TRU2和第三晶体管单元TRU3中的至少一个重叠。另外，耦接至第二源极布线SOI2的第二源极盘电极SOP2的一部分与第三晶体管单元TRU3重叠。以这样的配置，在不增加半导体装置SD的平面形状的情况下，通过增大漏极盘电极DRP和源极盘电极SOP的平面形状可以进一步减小源电极SOE和漏电极DRE的表面电阻。
在该图所示的例子中，所述第一源极盘电极SOP1的一部分与第一晶体管单元TUR1重叠，而其另一部分与第二晶体管单元TUR2重叠。所述第一源极盘电极SOP1的所述部分(与第一晶体管单元TUR1重叠的部分)的宽度与所述第一源极盘电极SOP1的所述另一部分(与第二晶体管单元TUR2重叠的所述另一部分)的宽度几乎彼此相等。所述第二漏极盘电极DRP2的一部分与第二晶体管单元TUR2重叠，而其另一部分与第三晶体管单元TUR3的至少一边重叠。所述第二漏极盘电极DRP2的所述部分(与第二晶体管单元TUR2重叠的部分)的宽度与其所述另一部分(与第三晶体管单元TUR3重叠的所述另一部分)的宽度几乎彼此相等。
然而，如图10中所示，所述第一源极盘电极SOP1的所述部分(与第一晶体管单元TUR1重叠的部分)的宽度与所述第一源极盘电极SOP1的所述另一部分(与第二晶体管单元TUR2重叠的所述另一部分)的宽度可以彼此不同。另外，所述第二漏极盘电极DRP2的所述部分(与第二晶体管单元TUR2重叠的部分)的宽度与所述第二漏极盘电极DRP2的所述另一部分(与第三晶体管单元TUR3重叠的所述另一部分)的宽度可以彼此不同。
另外，如图11中所示，第一漏极盘电极DRP1可以仅与第二晶体管单元TRU2重叠，并且第二源极盘电极SOP2可以仅与第三晶体管单元TRU3重叠。
如图8、10及11中示出的，在与源极盘电极SOP和漏极盘电极DRP相同的层中形成栅极盘极(gate pad pole)GEP。通过嵌入在层间绝缘膜INSL2中的栅极触点GEC将栅极盘电极GEP2耦接至栅极板GEP。
图12是示出根据本实施例的包括半导体装置SD的电子装置ED的配置的图。在该图所示的例子中，半导体装置SD安装在保持部件HLD上。保持部件HLD是例如半导体封装的引线框架，并包括栅极端子GET、源极端子SOT和漏极端子DRT。栅极端子GET通过接合线WIR2耦接至栅极盘电极GEP2。源极端子SOT通过接合线WIR1(第一接合部件和第四接合部件)耦接至源极盘电极SOP，而漏极端子DRT通过接合线WIR3(第二接合部件和第三接合部件)耦接至漏极盘电极DRP。以这样的配置，不须将接合线WIR1和WIR3所耦接的盘与源极盘电极SOP和漏极盘电极DRP分开提供，并因此可以抑制半导体装置SD尺寸上的增长。另外，接合线WIR1在多个点接合到源极盘电极SOP，并且接合线WIR3在多个点接合到漏极盘电极DRP。因此，可以从多个位置向源极盘电极SOP或漏极盘电极DRP提供电压。源极盘电极SOP或漏极盘电极DRP的电阻通常比接合线WIR1及接合线WIR3的电阻高。因此，以前述的配置，源极盘电极SOP和漏极盘电极DRP占电流路径的比例变小，并因此可以减小该电流路径的电阻。
替代地，因为源极盘电极SOP和漏极盘电极DRP的宽度较宽，因此可以采用带状接合线(接合带)作为接合线WIR1和WIR3。在这种情况下，也可以减小产生自接合线WIR1和WIR3的电阻分量。另外，可以分别增加接合线WIR1和源极盘电极SOP之间的接触面积及接合线WIR3和漏极盘电极DRP之间的接触面积，并因此也可以减小它们各自之间的耦接电阻。
如上所述的，在本实施例中也可以获得与在第一实施例中相同的优点。另外，因为提供源极盘电极SOP和漏极盘电极DRP，所以可以减小源极电极SOE和漏极电极DRE的表面电阻。
(第三实施例)
图13是示出根据第三实施例的半导体装置SD的配置的图。根据本实施例的半导体装置SD除了以下几点外，与第二实施例的半导体装置的配置相同。
首先，漏极盘电极DRP和源极盘电极SOP沿着与源极布线SOI交叉的方向(即，第二方向)延伸。分别在漏极盘电极DRP与每一个漏极布线DRI之间的交叉点处提供漏极触点DRC，分别在源极盘电极SOP与每一个源极布线SOI之间的交叉点处提供源极触点SOC。换言之，通过彼此不同的漏极触点DRC将漏极电极DRE耦接至同一漏极盘电极DRP，而通过彼此不同的源极触点SOC将源极电极SOE耦接至同一源极盘电极SOP。
在本实施例中也可以获得与在第二实施例中的相同的优点。
以上已经基于优选的实施例具体地描述了由本发明人做出的发明，但是本发明不应限于优选的实施例，并且无用说，可以在不脱离本发明的主旨的范围内对本发明做出各种改变。

Claims (8)

1.一种半导体装置，包括：
第一晶体管单元、第二晶体管单元，和第三晶体管单元，以该顺序在第一方向排列，
其中，第一晶体管单元、第二晶体管单元和第三晶体管单元中的每一个具有栅电极以第一方向延伸的多个晶体管，并且
其中，所述半导体装置还包括：
第一布线，其以与第一方向交叉的第二方向，在第一晶体管单元和第二晶体管单元之间延伸，并且所述第一布线耦接至第一晶体管单元中的晶体管的源电极和第二晶体管单元中的晶体管的源电极；
第二布线，其位于第一晶体管单元的与第一布线所位于的一侧相反的一侧上，并以第二方向延伸，并且所述第二布线耦接至第一晶体管单元中的晶体管的漏电极；
第三布线，其以第二方向在第二晶体管单元和第三晶体管单元之间延伸，并且所述第三布线耦接至第二晶体管单元中的晶体管的漏电极和第三晶体管单元中的晶体管的源电极；和
第四布线，其位于第三晶体管单元的与第三布线所位于的一侧相反的一侧上，并以第二方向延伸，并且所述第四布线耦接至第三晶体管单元中的晶体管的源电极。
2.根据权利要求1所述的半导体装置，包括：
第一上层导电图案，其设置在第一布线上方的层中，在宽度上大于第一布线，并且其以第二方向延伸；
第一耦接部件，其将第一布线耦接至第一上层导电图案；
第二上层导电图案，其设置在第二布线上方的层中，在宽度上大于第二布线，并且其以第二方向延伸；
第二耦接部件，其将第二布线耦接至第二上层导电图案；
第三上层导电图案，其设置在第三布线上方的层中，在宽度上大于第三布线，并且其以第二方向延伸；
第三耦接部件，其将第三布线耦接至第三上层导电图案；
第四上层导电图案，其设置在第四布线上方的层中，并且在宽度上大于第四布线，并且其以第二方向延伸，和
第四耦接部件，其将第四布线耦接至第四上层导电图案。
3.根据权利要求2所述的半导体装置，其中，当平面地看时：
所述第一上层导电图案的一部分与第一晶体管单元重叠；
所述第二上层导电图案的一部分与第一晶体管单元和第二晶体管单元中的至少一个重叠；
所述第三上层导电图案的一部分与第二晶体管单元和第三晶体管单元中的至少一个重叠；并且
所述第四上层导电图案的一部分与第三晶体管单元重叠。
4.根据权利要求3所述的半导体装置，其中：
所述第二上层导电图案的所述一部分与第一晶体管单元重叠，所述第二上层导电图案的另一部分与第二晶体管单元重叠；
所述第三上层导电图案的所述一部分与第二晶体管单元重叠；并且
所述第二上层导电图案的另一部分与第三晶体管单元重叠。
5.根据权利要求2所述的半导体装置，包括：
第一接合部件，其将第一上层导电图案耦接至第一外部端子；
第二接合部件，其将第二上层导电图案耦接至第二外部端子；
第三接合部件，其将第三上层导电图案耦接至所述第二外部端子；和
第四接合部件，其将第四上层导电图案耦接至所述第一外部端子。
6.根据权利要求1所述的半导体装置，包括：
第一上层导电图案和第二上层导电图案，其设置在第一布线上方的层中，并且在宽度上大于第一布线、第二布线、第三布线以及第四布线，并且其以第一方向延伸，并且当平面地看时，其与第一晶体管单元、第二晶体管单元和第三晶体管单元重叠；
第一耦接部件，其将第一布线耦接至所述第一上层导电图案；
第二耦接部件，其将第二布线耦接至所述第二上层导电图案；
第三耦接部件，其将第三布线耦接至所述第二上层导电图案，和
第四耦接部件，其将第四布线耦接至所述第一上层导电图案。
7.根据权利要求1所述的半导体装置，
其中，所述晶体管是用于功率控制的晶体管。
8.根据权利要求1所述的半导体装置，
其中，所述晶体管的沟道形成在化合物半导体层中。
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