CN106449727B - 防雪崩的准垂直hemt - Google Patents

防雪崩的准垂直hemt Download PDF

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CN106449727B
CN106449727B CN201610629469.0A CN201610629469A CN106449727B CN 106449727 B CN106449727 B CN 106449727B CN 201610629469 A CN201610629469 A CN 201610629469A CN 106449727 B CN106449727 B CN 106449727B
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layer
drift
lateral surfaces
conduction type
region
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CN106449727A (zh
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G·库拉托拉
R·西明耶科
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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Abstract

本申请涉及防雪崩的准垂直HEMT。半导体器件包括：半导体本体，所述半导体本体包括第一横向表面和第二横向表面。第一器件区域包括第一导电类型的漂移区域和第二导电类型的漂移电流控制区域，所述漂移电流控制区域通过所述漂移区域与所述第二横向表面隔开。第二器件区域包括阻挡层和缓冲层，所述缓冲层具有与所述阻挡层不同的带隙，使得沿着所述缓冲层和所述阻挡层之间的界面出现二维电荷载流子气沟道。导电衬底接触件形成所述二维电荷载流子气沟道与所述漂移区域之间的低欧姆连接。栅极结构被配置用于控制所述二维电荷载流子气的传导状态。所述漂移电流控制区域被配置用于经由空间电荷区域来阻止所述漂移区域中的垂直电流。

Description

防雪崩的准垂直HEMT
技术领域
本申请涉及功率晶体管，并且更特别地涉及具有高击穿电压额定值的高电子迁移率功率晶体管。
背景技术
半导体晶体管、特别是场效应受控开关器件在各种各样的应用中被使用，场效应受控开关器件诸如MISFET(金属绝缘体半导体场效应晶体管)和HEMT(高电子迁移率场效应晶体管)，MISFET在下面也称为MOSFET(金属氧化物半导体场效应晶体管)，HEMT也称为异质结构FET(HFET)和调制掺杂FET(MODFET)。HEMT是在具有不同带隙的两种材料诸如GaN和AlGaN之间具有结的晶体管。
在基于GaN/AlGaN的HEMT中，二维电子气(2DEG)出现在AlGaN阻挡层和GaN缓冲层之间的界面处。在HEMT中，2DEG形成器件的沟道，而代替在传统MOSFET器件中形成沟道的掺杂区域。可以利用类似的原理来选择形成二维空穴气(2DHG)的缓冲层和阻挡层作为器件的沟道。2DEG或2DHG统称为二维载流子气。在无需其它措施的情况下，异质结配置带来自导通、即常通的晶体管。典型地，必须采取措施来防止HEMT的沟道区域在没有正栅极电压的情况下处于导通状态。
HEMT被视为功率晶体管应用的极具吸引力的候选。功率晶体管是能够切换与高功率应用相关联的显著电压和/或电流的器件。例如，可能需要功率晶体管阻止至少200V、400V、600V或更大的电压。此外，可能需要功率晶体管在正常操作期间传导范围在几安培、数十安培或数百安培的电流。由于异质结配置中二维载流子气的高电子迁移率，HEMT与许多传统半导体晶体管设计相比提供高导通和低损耗，并且因此更好地适于这些大操作电流。
已知的HEMT设计具有很多限制，这些限制不利地影响其对于功率晶体管应用的适用性。GaN技术的一个限制涉及基于GaN/AlGaN的HEMT的击穿强度。传统上，基于GaN/AlGaN的HEMT的击穿强度可以通过增加GaN缓冲层的厚度来改善。然而，该技术引入制造工艺的成本和复杂度。在HEMT设计中的其它问题包括较差的动态导通电阻、电流崩塌和可靠性问题，例如由于HEMT的固有横向结构导致的在器件表面处的源极指状物和漏极指状物之间的高电场而引起。
发明内容
公开了一种半导体器件。根据实施例，半导体器件包括半导体本体，该半导体本体包括第一横向表面和与第一横向表面相反的第二横向表面。第一器件区域延伸到第二横向表面，并且包括第一导电类型的漂移区域和第二导电类型的漂移电流控制区域，该第二导电类型与第一导电类型相反，漂移电流控制区域通过漂移区域与第二横向表面隔开。第二器件区域延伸到第一横向表面，并且包括阻挡层和缓冲层，缓冲层具有与阻挡层不同的带隙，使得沿着缓冲层和阻挡层之间的界面出现二维电荷载流子气沟道。导电衬底接触件形成二维电荷载流子气沟道与漂移区域之间的低欧姆连接。栅极结构被配置用于控制二维电荷载流子气的传导状态。漂移电流控制区域被配置用于经由在漂移电流控制区域与漂移区域之间的pn结处出现的空间电荷区域来阻止漂移区域中的垂直电流。
公开了一种晶体管装置。根据实施例，晶体管装置包括半导体本体，该半导体本体包括第一横向表面和与第一横向表面相反的第二横向表面。晶体管装置还包括垂直JFET，垂直JFET包括第一导电类型的漂移区域和第二导电类型的漂移电流控制区域，该第二导电类型与第一导电类型相反。晶体管装置还包括横向高电子迁移率晶体管，该横向高电子迁移率晶体管包括阻挡层和缓冲层，缓冲层具有与阻挡层不同的带隙，使得沿着缓冲层和阻挡层之间的界面出现二维电荷载流子气。导电衬底接触件形成二维电荷载流子气沟道与漂移区域之间的欧姆连接。HEMT栅极被配置用于控制二维电荷载流子气沟道中的横向电流。JFET栅极被配置用于控制漂移区域中的垂直电流。
公开了一种在半导体本体中形成半导体器件的方法，该半导体本体包括第一横向表面和与第一横向表面相反的第二横向表面。根据实施例，该方法包括形成第一器件区域，该第一器件区域包括第一导电类型的漂移区域和第二导电类型的漂移电流控制区域，该第二导电类型与第一导电类型相反，漂移电流控制区域通过漂移区域与第二横向表面隔开。在第一器件区域上形成第二器件区域。该第二器件区域包括阻挡层和缓冲层，缓冲层具有与阻挡层不同的带隙，使得沿着缓冲层和阻挡层之间的界面出现二维电荷载流子气沟道。在半导体本体中形成导电衬底接触件。该导电衬底接触件形成二维电荷载流子气沟道与漂移区域之间的欧姆连接。在半导体本体上形成栅极结构，该栅极结构被配置用于控制二维电荷载流子气的传导状态。第一器件区域邻接第二横向表面，并且第二器件区域邻接第一横向表面。漂移电流控制区域被形成为使得在漂移电流控制区域与漂移区域之间的pn结处出现的空间电荷区域被配置用于阻止漂移区域中的垂直电流。
公开了一种电路。根据实施例，该电路包括JFET、高电子迁移率晶体管以及被连接在JFET和高电子迁移率晶体管的输出端子之间的二极管。高电子迁移率晶体管的漏极被连接到JFET的源极。JFET的栅极被连接到高电子迁移率晶体管的源极。JFET的夹断电压低于高电子迁移率晶体管的击穿电压。
通过阅读下面的详细描述和附图，本领域技术人员将认识到附加的特征和优势。
附图说明
附图中的元件不一定相对彼此按比例绘制。相同的参考标号标示对应的类似部分。各种所示实施例的特征可以被组合，除非它们彼此排斥。实施例在附图中被描绘并在下面的描述中被详述。
图1图示了根据一个实施例的包括垂直JFET和横向高电子迁移率晶体管的准垂直晶体管。
图2图示了根据一个实施例的包括垂直JFET和常关横向高电子迁移率晶体管的准垂直晶体管。
图3图示了根据另一实施例的包括垂直JFET和常关横向高电子迁移率晶体管的准垂直晶体管。
图4图示了根据另一实施例的包括垂直JFET和常关横向高电子迁移率晶体管的准垂直晶体管。
图5图示了根据一个实施例的包括垂直JFET和具有集成的肖特基二极管的横向高电子迁移率晶体管的准垂直晶体管。
图6图示了根据另一实施例的包括垂直JFET和横向高电子迁移率晶体管的准垂直晶体管。
图7示意性地图示了根据一个实施例的包括JFET和横向高电子迁移率晶体管的电路，其中JFET和横向高电子迁移率晶体管以级联配置连接。
具体实施方式
这里所描述的实施例包括由横向HEMT和垂直JFET形成的功率晶体管，该横向HEMT和垂直JFET被集成在单个衬底中。功率晶体管形成在复合衬底中，该复合衬底包括理想地适用于这两种晶体管器件的材料层。例如，垂直JFET层可以形成在SiC区域中，而横向HEMT器件可以形成在GaN区域中。在功率晶体管的输出端子(例如源极端子和漏极端子)被布置在衬底的相反侧上并且功率晶体管控制在它们二者之间流动的电流的意义上而言，功率晶体管是“垂直”器件。在存在横向电流路径和垂直电流路径二者的意义上而言，功率晶体管是“准垂直的”。HEMT控制横向电流路径，该横向电流路径沿着与半导体本体的第一横向表面平行的异质结而延伸。JFET控制垂直电流路径，该垂直电流路径在半导体本体的垂直方向上延伸穿过漂移层。
该功率晶体管设计与传统的基于GaN的功率晶体管设计和/或传统的基于SiC的功率晶体管设计相比提供许多优势。一个明显优势在于独立地调整HEMT和JFET的参数的能力。JFET可以被定制以实现高反向电压额定值。由于JFET包括形成器件的漂移层的较厚SiC区域，所以JFET的材料参数使雪崩击穿缓解并且因此实现非常高的反向阻止能力(例如600V或更大)。同时，可以针对正向导通性能来优化HEMT器件的物理参数(例如缓冲层厚度、掺杂浓度等)，而无需经受关于反向电压额定值的折中。此外，可以用于形成JFET的SiC提供用于形成HEMT的GaN材料的外延生长的高质量衬底材料的优势。与诸如硅之类的其它衬底材料相比，用于HEMT的GaN材料的质量和缺陷密度得到很大改善。此外，GaN层本身的生长工艺是容易的。此外，可以使用非常薄的GaN层(例如小于1μm)作为缓冲层，这与传统600V额定器件中使用的5-6μm的厚度相比提供成本效益。
JFET的栅极区域可以设置在HEMT缓冲层正下方，使得也将HEMT器件屏蔽以免于可以跨漂移区域形成的大电场，该JFET的栅极区域与漂移区域相反掺杂。雪崩击穿如果发生则将出现在JFET的栅极区域内。这改善了器件的防雪崩性。这显著改善了器件的电流崩塌和动态RDSON行为。鉴于下面的描述，更多优势对于本领域技术人员而言将变得显而易见。
参照图1，描绘了半导体器件100。半导体器件100由半导体本体102形成，半导体本体102具有第一横向表面104和第二横向表面106，第二横向表面106与第一横向表面104隔开并相反。
半导体本体102包括第一器件区域108和第二器件区域110。第一器件区域108和第二器件区域110彼此垂直层叠。第一器件区域108延伸到第二横向表面106。也就是，第一器件区域108的下侧在第二横向表面106处与半导体本体102形成公共边界。第二器件区域110延伸到第一横向表面104。也就是，第二器件区域110的上侧在第一横向表面104处与半导体本体102形成公共边界。根据一个实施例，第一器件区域108和第二器件区域110在半导体本体102内的横向界面处彼此直接邻接。
第一器件区域108包括第一导电类型的漂移区域112和第二导电类型的漂移电流控制区域114，该第二导电类型与第一导电类型相反。例如，漂移区域112可以是N型区域并且漂移电流控制区域114可以是P型区域。漂移电流控制区域114通过漂移区域112与第二横向表面106隔开。也就是，漂移区域112插入在漂移电流控制区域114与第二横向表面106之间。
第二器件区域110包括阻挡层116和缓冲层118。缓冲层118由具有与用于形成阻挡层106的半导体材料不同带隙的半导体材料形成。也就是，第二器件区域110包括异质结。在两种材料之间存在压电和/或自发偏振电荷导致沿着缓冲层118与阻挡层116之间的界面出现的二维电荷载流子气沟道120。根据一个实施例，缓冲层118是GaN层，并且阻挡层116为AlGaN层。
半导体器件100包括导电衬底接触件122。根据一个实施例，衬底接触件122从第一横向表面104延伸穿过第二器件区域110(即，穿过阻挡层116和缓冲层118)并到达第一器件区域108中。导电衬底接触件122由导电材料形成，诸如多晶硅、铜、铝、钛或任意合适合金。衬底接触件122形成二维电荷载流子气沟道122与漂移区域112之间的低电阻连接。例如，衬底接触件122可以直接邻接二维电荷载流子气沟道122和漂移区域112，从而提供这两者之间的低欧姆连接。第一导电类型的重掺杂接触区域124可以插入在衬底接触件122与第一器件区域108之间，从而降低衬底接触件122与漂移区域112之间的接触电阻。此外，可以在衬底接触件122与漂移区域112之间提供硅化物以改善接触电阻。
半导体器件100还包括导电栅极电极126、第一导电输出接触件128和第二导电输出接触件130。第二导电类型的重掺杂接触区域125可以插入在第一导电输出接触件128与漂移电流控制区域114之间，从而降低第一导电输出接触128件与漂移电流控制区域114之间的接触电阻。
栅极电极126以及第一输出接触件128和第二输出接触件130由导电材料形成，诸如多晶硅、铜、铝、钛或各种合金材料中的任意一种(Au、TiN、TaN、Ti、Ni、Mo、W和任意合适组合)。栅极电极126和第一输出接触件128形成在第一横向表面104上，并且第二输出接触件130形成在第二横向表面106上。如图1所示，栅极电极126布置在第一横向表面104之上，而第一输出接触件128穿透到半导体本体102中。这是一个示例性配置，并且可以实施各种各样的接触件配置来实现所需的电连接性。根据一个实施例，第一输出接触件128与二维电荷载流子气沟道120和漂移电流控制区域114欧姆接触。如图1所示，第一输出接触件128可以形成在延伸到半导体本体102中的凹部(例如刻蚀的开口)中，使得导电衬底接触件122直接接触二维电荷载流子气沟道120和漂移电流控制区域114二者。
现在将讨论由图1的半导体器件100形成的准垂直晶体管的工作原理。第一输出接触件128和第二输出接触件130可以分别形成准垂直晶体管的源极端子和漏极端子。准垂直晶体管利用两个串联连接的晶体管来控制第一输出接触件128和第二输出接触件130之间的电流流动。
第一晶体管由布置在第一器件区域108中的垂直JFET形成。垂直JFET通过漂移区域112的第一垂直部分132和漂移电流控制区域114形成。漂移区域112的第一垂直部分132与漂移电流控制区域114横向相邻。此外，漂移区域112的第一垂直部分132通过直接物理接触或通过可选的接触区域124来与衬底接触件122欧姆接触。空间电荷区域(即，耗尽区域)出现在漂移电流控制区域114与漂移区域112之间的pn结134处。可以调制在漂移区域112的第一垂直部分132中形成的空间电荷区域，以控制漂移区域112中的载流子的流动。施加到该pn结134的足够数量的反向偏压将引起空间电荷区域跨漂移区域112的第一垂直部分132横向扩展并且中断在漂移区域112中的电流流动。以此方式，漂移电流控制区域114提供垂直JFET的栅极。第一垂直部分132可以具有与漂移区域112的下侧部分133相同的掺杂浓度。备选地，第一垂直部分132可以具有为漂移区域112的下侧部分133的掺杂浓度的至少两倍高的掺杂浓度。该较高的掺杂浓度增强了第一垂直部分132的电流扩展能力并且因而降低了垂直JFET的通态电阻。
第二晶体管由布置在第二器件区域110中的横向HEMT形成。该横向HEMT的栅极由栅极电极126提供。栅极电极126布置在二维电荷载流子气沟道120正上方，使得二维电荷载流子气沟道120的传导状态可以受栅极电极126影响。施加到栅极电极126的适当偏压将完成或中断第一输出接触件128与衬底接触件122之间的传导路径。在这种意义下，衬底接触件122提供横向HEMT的“漏极”。可选地，如图1所示，器件100可以被配置有公共漏极配置的两个横向HEMT。
准垂直晶体管因而被配置用于通过上述两个不同的晶体管器件(即，垂直JFET和横向HEMT)来控制在第一输出接触件128与第二输出接触件130之间的电流流动。该准垂直晶体管中的电流由横向HEMT的栅极和垂直JFET的栅极共同控制。准垂直晶体管仅在垂直JFET和横向HEMT二者都“导通”时“导通”(即，提供在第一输出接触件128和第二输出接触件130之间的导电连接)。
现在将讨论用于形成图1的半导体器件100的方法。根据该方法，第一器件区域108完全或部分地通过外延生长工艺形成。外延生长工艺的一个实施例包括提供第一导电类型的衬底136。衬底136可以由体半导体材料提供，或备选地，可以由外延生长层形成。随后，在衬底136上外延生长第一导电类型的场停止层138。场停止层138具有比衬底136低的掺杂浓度。随后，在场停止层138上外延生长第一导电类型的漂移层140。漂移层140具有比场停止层138低的掺杂浓度。漂移层140和场停止层138共同形成半导体本体102内的第一复合外延层，即，两个或更多不同外延层的叠置。
用于形成第一器件区域108的层的半导体材料可以是具有宽带隙的半导体材料或者具有与第二器件区域110的半导体材料类似的带隙的任意半导体材料。根据一个实施例，衬底136、场停止层138和漂移层140均由SiC形成。
在形成第一器件区域108之后，漂移电流控制区域114可以形成在漂移层140的与衬底136相反的顶表面144处。根据一个实施例，第二导电类型的掺杂阱142形成在漂移层140中。掺杂阱142可以通过例如在顶表面144中引入掺杂剂(例如通过注入)来形成。根据一个实施例，掺杂阱142的整体掺杂剂浓度高于第一垂直部分132的整体掺杂剂浓度。整体掺杂剂浓度在与顶表面平行的横向方向上测量。这允许第一垂直部分132中的电流被夹断，并因而提供可控制的JFET器件。可选地，也可以将第一导电类型的掺杂剂注入到顶表面144中，使得形成具有比漂移区域112的下侧部分高的掺杂浓度的第一垂直部分132。
在形成第一器件区域108之后，第二器件区域110可以通过其中在第一器件区域108上外延生长半导体材料的另一外延生长工艺形成。根据一个实施例，在第一器件区域108的SiC材料上形成成核层145。成核层145包括能够在其上实现外延生长III型半导体氮化物材料(例如GaN)的金属氮化物材料(例如AlN)。随后，在成核层145上形成第二器件区域110。本外延生长工艺的一个实施例包括在成核层145上外延生长半导体材料的本征(即，未掺杂)层。该本征层形成缓冲层118。随后，在本征层上外延生长半导体材料的掺杂层。该掺杂层形成阻挡层116。半导体材料的本征层和掺杂层共同形成半导体本体102的第二复合外延层。
第二器件区域110可以由适于制造半导体器件的各种各样的半导体材料中的任意半导体材料制成，特别是适于制造高电子迁移率半导体器件的材料制成。根据一个实施例，缓冲层118是未掺杂GaN的外延层。备选地，缓冲层118可以是例如利用碳或铁特意掺杂的，以增加总体击穿强度并使泄漏最小化。阻挡层116可以是例如AlGaN的外延层。
通常，使用诸如GaN的III-V半导体材料来形成高电子迁移率半导体器件。利用GaN技术，偏振电荷和应变效应的存在导致实现二维电荷载流子气，该二维电荷载流子气是以非常高的载流子密度和载流子迁移率为特征的二维电子或空穴反型层。诸如2DEG(二维电子气)或2DHG(二维空穴气)的二维电荷载流子气形成器件的沟道区域。例如1nm-2nm的薄AlN层可以设置在GaN缓冲层118与合金阻挡层116之间，以使得合金散射最小化并增强2DEG迁移率。如本领域已知的那样，可以使用III-V半导体材料的其它组合以便形成2DEG或2DHG沟道区域。通常，可以使用任意异质结构，其中能带阶跃是器件概念的原因。例如，在AlGaAs系统中，没有压电效应，但涉及布置用于限制沟道区域的量子阱的限制概念是可能的。
在形成第二器件区域110之后，可以在半导体本体102的第一横向表面104上形成附加层。例如，可以在第一横向表面104上形成一个或多个钝化层119。钝化层119可以由各种各样的介电绝缘体中的任意介电绝缘体形成，诸如氧化物材料或基于氮化物的电介质。
衬底接触件122和第一输出接触件128可以通过刻蚀和沉积的序列来形成。根据一个实施例，在钝化层119上提供掩膜(未示出)。随后，执行掩蔽刻蚀技术以定义接触孔，该接触孔用于形成衬底接触件122和第一输出接触件128。可以执行刻蚀工艺使得这些接触孔延伸穿过阻挡层116和缓冲层118。作为结果，形成衬底接触件122的接触孔的底部布置在漂移层140中，并且形成第一输出接触件128的接触孔的底部布置在漂移电流控制区域114中。重掺杂接触区域124可以例如通过将掺杂剂注入到形成衬底接触件122的接触孔的底部中来形成。由于与掺杂剂激活相关联的高温，该注入步骤可以在第二器件区域110的外延生长之前完成。可以执行类似的工艺来提高第一输出接触件128的接触电阻。衬底接触件122和第一输出接触件128可以通过在接触孔中沉积诸如金属或多晶硅的导电材料来形成。
栅极电极126和第二输出接触件130可以根据包括但不限于沉积、电镀和掩蔽刻蚀的各种已知技术中的任意技术来形成。
图2至图4描绘了半导体器件100的附加实施例。在每种情况下，半导体器件100可以与图1的半导体器件100相同，除了横向HEMT的栅极配置。图1的HEMT被配置为“常通”或负阈值电压器件。也就是，在不存在施加到栅极电压126的任何偏压的情况下，二维电荷载流子气沟道120是导电的，因为如下事实：在未偏置条件下二维电荷载流子气自动地存在于阻挡层116和缓冲层118之间。在图2至图4的半导体器件100中，横向HEMT被配置为“常关”或正阈值电压器件。也就是，HEMT被配置使得当半导体器件100处于零栅极偏压时二维电荷载流子气沟道120处于非传导状态。栅极偏压是指在栅极电极126与第一输出接触件128之间测量的电势。该“常关”方面可以通过例如将特征并入到HEMT的栅极结构中来实现。
参照图2，HEMT的栅极结构包括插入在栅极电极126和二维电荷载流子气沟道120之间的半导体材料的掺杂区域146。在其中阻挡层116和缓冲层118分别由GaN和AlGaN形成的实施例中，掺杂区域146可以是例如p型GaN(或AlGaN)的层。掺杂区域146的掺杂浓度和隔开距离(掺杂区域146相对于二维电荷载流子气沟道120的隔开距离)可以被定制，使得二维电荷载流子气沟道120由于由掺杂区域146产生的电场而在零栅极偏压下是非传导的。
参照图3，HEMT被配置有凹入的栅极结构。更具体地，在半导体本体102的第一横向表面104中(例如通过掩蔽刻蚀)已经形成凹部。凹部延伸穿过钝化层119并到达阻挡层116中。凹部可以部分地或完全地延伸穿过阻挡层116。阻挡层116的一部分的缺乏局部地阻断在凹部正下方的区域中的二维电荷载流子气沟道120。诸如氧化物的介电绝缘体148插入在栅极电极126与二维电荷载流子气沟道120之间。可以通过施加跨介电绝缘体148的电场(即，施加栅极-源极偏压)来使HEMT导通，以将载流子引至二维电荷载流子气沟道120的耗尽区域中并因此完成第一输出接触件128和衬底接触件122之间的电连接。
参照图4，HEMT的栅极结构包括压电区域150。压电区域150在二维电荷载流子气沟道120上方形成在第一横向表面104处或第一横向表面104附近。代替通过电场机制控制二维电荷载流子气沟道120的传导状态，如在大多数HEMT设计中的情况中那样，图5的栅极结构利用机械应力来影响二维电荷载流子气沟道120。在未偏置状态下，压电区域150可以根据压电区域150的配置来向半导体本体102施加机械应力。该机械应力传播到二维电荷载流子气沟道120并阻断第一输出接触件128与衬底接触件122之间的本征导电连接。HEMT可以通过向压电区域150施加电场而被导通，这去除了由压电区域150施加的机械应力并且重新建立在第一输出接触件128与衬底接触件122之间的电连接。
图5描绘了半导体器件100的另一实施例。半导体器件100可以与图1的半导体器件100相同，除了漂移电流控制区域114的配置和几何形状。在图1的实施例中，漂移电流控制区域114完全跨第一输出接触件128的底侧延伸。因而，在第一输出接触件128与漂移区域112之间没有直接接触。在图5的实施例中，漂移电流控制区域114仅部分地跨第一输出接触件128的底侧延伸，使得第一输出接触件128的一部分直接接触漂移区域112。在该配置中，漂移区域112的第二垂直部分152延伸到第一输出接触件128。漂移区域112的第二垂直部分152与第一输出接触件128形成肖特基结。因而，低正向偏置的肖特基二极管154被连接在准垂直晶体管的源极电极和漏极电极之间。
现在将讨论这里描述的准垂直晶体管的优势中的一些优势。准垂直晶体管的一个明显优势在于大多数反向阻止能力归因于垂直JFET，而不是横向HEMT。当器件100处于反向阻止模式中时，大多数电势跨漂移区域112分布。由衬底接触件122提供的横向HEMT的“漏极”被遮蔽免于在漂移区域112中出现的电场。例如，根据一个实施例，漂移电流控制区域114在第二器件区域110下方延伸至少二维电荷载流子气沟道120的横向长度的50％。由漂移电流控制区域114产生的该遮蔽效果保护缓冲层118免于在大反向偏压下可以出现在漂移区域112中的潜在破坏性的电场。因而，横向HEMT不需要被设计为耐受大阻止电压。与此同时，可以利用横向HEMT的有利特性来提供具有快速切换时间、低RDSON和抗电流崩塌性的功率半导体器件100。HEMT器件的这些属性优于例如常规SiC MOSFET，因为SiC技术由于沿器件的SiO2-SiC界面形成的反型沟道中载流子的相对较低迁移率而遭受相对较高RDSON的缺陷。
用于形成JFET的SiC材料的有利物理特性和相对较厚的漂移区域112产生能够耐受相当大电压的器件。JFET可以在经历雪崩击穿条件之前耐受被设计用于例如大约600V或更高的任意电压，该雪崩击穿条件是关于电压阻止能力的基本限制因素。此外，JFET的参数可以被定制用于最佳反向阻止能力，而无需对横向HEMT的参数的任何修改。影响反向阻止能力的JFET的示例参数包括漂移区域112的厚度、漂移电流控制区域114的掺杂浓度、形成漂移电流控制区域114的阱142的深度(如图1所示的(D1))以及例如在漂移电流控制区域114的相邻区域之间的隔开距离(如图1所示的(D2))。
器件100的另一优势涉及可扩展性。例如，可以通过简单地调整JFET的参数，而无需对横向HEMT的任何修改，来实现具体应用要求(例如，反向电压额定值、RDSON等)。也就是，可以扩展JFET，而横向HEMT的特征和对应性能保持不变。因此该设计提供在最小设计成本下适于各种不同应用的成本有效的模版。
由于准垂直晶体管的整个反向阻止能力归因于JFET，所以可以优化横向HEMT用于其它考虑，诸如通态性能和成本。例如，与在硅或碳化硅衬底上按照公知方式生长的相当反向阻止额定值的HEMT相比，可以大大减小缓冲层118的厚度。根据一个实施例，缓冲层118具有少于2μm、诸如1μm的厚度(如在垂直方向上测量)。在本实施例中，可以定制JFET的参数来实现用于至少600V的准垂直晶体管的总体反向阻止额定值。通过比较，传统横向HEMT中的相当反向阻止额定值要求大约6μm的缓冲层118的厚度，传统横向HEMT即不包括以这里所述方式结合到衬底中的基于SiC的JFET结构的横向HEMT。该缓冲层118的厚度的减小也有利地减少了制造该器件的时间和代价。
可以容易地制造准垂直晶体管以包括具有低正向电压降的本体二极管。如参照图5的实施例所说明的那样，在第一输出接触件128与漂移层140的第二垂直部分152之间的整流结提供用于该器件的肖特基二极管154。该肖特基二极管154提供在准垂直晶体管的源极和漏极之间的低正向偏置的内建二极管。由于漂移层140的低掺杂浓度和SiC的特性，正向电压降可以在例如约1V的范围内。通过对比，在常规HEMT器件中形成的本体二极管通常具有至少3V的正向电压降。
图6描述了根据另一实施例的半导体器件100。半导体器件100被相同地配置为图1的半导体器件100，除了半导体器件100中的最下层的掺杂类型。在图6的半导体器件100中，第二导电类型的层137(例如p型层)被布置在漂移层140和最下输出接触件131之间。第二导电类型的层137延伸到第二横向表面106，并因而直接接触最下输出接触件131。(除了第一导电类型的衬底136或代替第一导电类型的衬底136)通过在半导体器件100中结合第二导电类型的层137，可以实现双极晶体管器件，其中第二导电类型的层137提供器件的集电极侧，并且最下输出接触件131提供集电极端子。
图7示意性地示出了根据一个实施例的包括HEMT 202和JFET 204的电路200。电路200可以由根据这里所述实施例中的任一实施例的半导体器件100形成，其中HEMT 202由横向HEMT提供，并且JFET 204由集成在同一衬底中的垂直JFET提供。在图7的电路200中，HEMT202和JFET 204以级联配置来布置。也就是，电路200具有由例如横向HEMT提供的公共发射极或公共源极级，其与由例如JFET提供的公共基极或公共栅极级组合。电路200还包括被连接在JFET 204和高电子迁移率晶体管202的输出端子之间的本体二极管206。本体二极管206可以通过这里所述的低正向偏置的肖特基二极管154提供。
JFET 204的夹断电压低于HEMT 202的击穿电压。这防止HEMT 202进入雪崩条件，并因而电路200的击穿电压的可控性高。此外，HEMT 202的沟道中的载流子的迁移率大于JFET 204的沟道中的载流子的迁移率。而且，HEMT 202的泄漏电流高于JFET 204的泄漏电流。这些特性归因于用于形成JFET 204和HEMT 202(例如分别为SiC和GaN)的材料的固有特性和/或JFET 204和HEMT 202的物理特性的适当参数化(例如掺杂浓度、层厚度、间隔距离等)。在JFET 204和HEMT 202可以进入阻止状态之前，这两个器件的输出电容都必需充电。每个器件的泄漏是与这些输出电容并联的等效电阻。一旦输出电容被充分充电，HEMT 202的输出电压就将升高。在这种状态下，可以容易地达到HEMT 202的击穿电压，这损害HEMT202。有利地，HEMT可以被配置有相对较大的泄漏电流，使得避免该击穿条件。
术语HEMT也统称为HFET(异质结构场效应晶体管)、MODFET(调制掺杂FET)和MESFET(金属半导体场效应晶体管)。术语HEMT、HFET、MESFET和MODFET在这里互换使用，以指代任何基于III族氮化物的复合半导体晶体管，其并入具有不同带隙的两种材料之间的结(即，异质结)作为沟道。例如，GaN可以与AlGaN或InGaN结合以形成电子气反型区域作为沟道。复合半导体器件可以具有AlInN/AlN/GaN阻挡层/间隔层/缓冲层118结构。通常，可以使用诸如GaN的任意适合III族氮化物技术来实现常关复合半导体晶体管，其由于压电效应而允许形成相反极性的反型区域。
术语“欧姆接触”或“电连接”或“电接触”描述具有线性电流-电压(I-V)特性的两个导体之间的永久非整流电结，如欧姆定律一样。相比之下，术语“电耦合”是指在电耦合元件之间提供被配置为以一些有形的方式影响电信号的一个或多个中间元件。这些中间元件包括诸如晶体管的有源元件以及诸如电感器、电容器、二极管、电阻器等的无源元件。
本说明书中使用的术语“横向”旨在描述与半导体衬底或本体的第一或主表面基本平行的定向。这可以例如是晶片或裸片的表面。
本说明书中使用的术语“垂直”旨在描述与半导体衬底或本体的第一表面基本布置成垂直、即与第一表面的法线方向平行的定向。
在本说明书中，半导体本体的半导体衬底的第二表面被视为由下表面或背侧表面形成，而第一表面被视为由半导体衬底的上表面、正表面或主表面形成。因此考虑到该定向，本说明书中使用的术语“之上”和“之下”描述结构特征相对于另一结构特征的相对位置。
在本说明书中，n掺杂称为第一导电类型，而p掺杂称为第二导电类型。备选地，半导体器件可以形成有相反掺杂关系，使得第一导电类型可以是p型而第二导电类型可以是n型。此外，一些图通过在掺杂类型附近指示“-”或“+”来图示相对掺杂浓度。例如，“n-”是指低于“n”掺杂区域的掺杂浓度的掺杂浓度，而“n+”具有比“n”掺杂区域的掺杂浓度高的掺杂浓度。然而，除非另外陈述，否则指示相对掺杂浓度并不意味着同一相对掺杂浓度的掺杂区域必需具有相同的绝对掺杂浓度。例如，两个不同的n+掺杂区域可以具有不同的绝对掺杂浓度。这同样适用于例如n+掺杂区域和p+掺杂区域。
本说明书中使用的术语“功率半导体器件”旨在描述具有高电压和/或高电流切换能力的单个芯片上的半导体器件。换言之，功率半导体器件具有通常在一安培或多安培的范围内的高电流和/或通常在100V以上、更通常在400V以上的高电压。
为便于描述，使用诸如“下方”、“之下”、“下”、“上方”、“上”等的空间相对术语来说明一个元件相对于第二元件的定位。除了与图中描述的定向不同的定向之外，这些术语用于涵盖器件的不同定向。此外，诸如“第一”、“第二”等的术语也被用于描述各种元件、区域、部分等并且也不用于进行限制。贯穿说明书，相同的术语指代相同的元件。
如这里所使用的，术语“具有”、“包含”、“包括”、“含有”等是开放式术语，其指示所述元件或特征的存在，但并不排除附加元件或特征。除非上下文另外明确指示，否则冠词“一个”、“一”和“该”用于包括复数以及单数。
考虑到变化和应用的上述范围，应理解到，本发明并不受前面描述的限制，也不受附图的限制。相反，本发明仅受以下权利要求及其合法等同物限制。

Claims (27)

1.一种半导体器件，包括：
半导体本体，所述半导体本体包括第一横向表面和与所述第一横向表面相反的第二横向表面；
第一器件区域，延伸到所述第二横向表面，并且包括：第一导电类型的漂移区域和第二导电类型的漂移电流控制区域，所述第二导电类型与所述第一导电类型相反，所述漂移电流控制区域通过所述漂移区域与所述第二横向表面隔开；
第二器件区域，延伸到所述第一横向表面，并且包括：阻挡层和缓冲层，所述缓冲层具有与所述阻挡层不同的带隙，并且在所述缓冲层和所述阻挡层之间的界面处具有二维电荷载流子气沟道；
导电衬底接触件，形成所述二维电荷载流子气沟道与所述漂移区域之间的低欧姆连接；以及
栅极结构，被配置用于控制所述二维电荷载流子气的传导状态，
其中所述漂移电流控制区域被配置用于经由在所述漂移电流控制区域与所述漂移区域之间的pn结处出现的空间电荷区域来阻止所述漂移区域中的垂直电流。
2.根据权利要求1所述的半导体器件，其中所述导电衬底接触件从所述第一横向表面延伸穿过所述第二器件区域并到达所述第一器件区域中，其中所述漂移区域的与所述漂移电流控制区域横向相邻的第一垂直部分与所述导电衬底接触件欧姆接触，并且其中所述漂移电流控制区域和所述漂移区域之间的所述pn结邻接所述漂移区域的所述第一垂直部分，使得所述空间电荷区域跨所述漂移区域的所述第一垂直部分而横向延伸。
3.根据权利要求2所述的半导体器件，其中所述第一垂直部分的掺杂浓度为所述漂移区域的下侧部分的掺杂浓度的至少两倍。
4.根据权利要求2所述的半导体器件，其中所述第一器件区域包括：
所述第一导电类型的衬底，邻接所述第二横向表面；以及
第一复合外延层，形成在所述衬底上，并且包括：
所述第一导电类型的掺杂场停止层；以及
所述第一导电类型的掺杂漂移层，形成在所述掺杂场停止层上，
其中所述漂移电流控制区域是从所述漂移层的与所述第二横向表面相反的第一侧延伸的掺杂阱。
5.根据权利要求4所述的半导体器件，其中所述第二器件区域包括：
第二复合外延层，形成在所述第一器件区域上，并且包括：
成核层，形成在所述第一器件区域上；
第一层半导体材料，形成在所述成核层上；以及
第二层半导体材料，形成在所述第一层半导体材料上。
6.根据权利要求5所述的半导体器件，其中所述衬底、所述场停止层和所述漂移层均由SiC形成，其中所述第一层半导体材料由GaN形成，并且其中所述第二层半导体材料由AlGaN形成。
7.根据权利要求2所述的半导体器件，还包括：
第一导电输出接触件，布置在所述第一横向表面上并且与所述二维电荷载流子气和所述漂移电流控制区域欧姆接触；以及
第二导电输出接触件，布置在所述第二横向表面上并且与所述漂移区域欧姆接触。
8.根据权利要求7所述的半导体器件，其中所述漂移电流控制区域在所述第二器件区域下方延伸所述二维电荷载流子气的横向长度的至少50％。
9.根据权利要求7所述的半导体器件，其中所述漂移区域的第二垂直部分与所述第一导电输出接触件欧姆接触，并且与所述第一导电输出接触件形成整流结。
10.根据权利要求7所述的半导体器件，其中所述栅极结构包括导电栅极电极，并且其中所述栅极电极被配置用于当所述半导体器件处于零栅极偏压时将所述二维电荷载流子气沟道置于非传导状态，所述栅极偏压是在所述栅极电极与所述第一导电输出接触件之间测量的。
11.根据权利要求10所述的半导体器件，还包括插入在所述栅极电极与所述二维电荷载流子气沟道之间的半导体材料的掺杂区域，其中所述掺杂区域被配置用于产生电场，所述电场在零栅极偏压下将所述二维电荷载流子气沟道置于所述非传导状态。
12.根据权利要求10所述的半导体器件，其中所述栅极结构包括插入在所述栅极电极与所述二维电荷载流子气沟道之间的绝缘区域，并且其中所述栅极电极形成在所述阻挡层的凹入部分中。
13.根据权利要求10所述的半导体器件，其中所述栅极结构包括被配置用于响应于所述栅极偏压而向所述第二器件区域施加机械力的压电区域，并且其中所述压电区域在零栅极偏压下施加机械力以将所述二维电荷载流子气沟道置于所述非传导状态。
14.根据权利要求2所述的半导体器件，其中所述第一器件区域包括：
所述第二导电类型的衬底层，邻接所述第二横向表面；以及
第一复合外延层，形成在所述衬底层上，并且包括：
所述第一导电类型的掺杂场停止层；以及
所述第一导电类型的掺杂漂移层，形成在所述掺杂场停止层上。
15.一种晶体管装置，包括：
半导体本体，所述半导体本体包括第一横向表面和与所述第一横向表面相反的第二横向表面；
垂直JFET，所述垂直JFET包括：第一导电类型的漂移区域和第二导电类型的漂移电流控制区域，所述第二导电类型与所述第一导电类型相反；
横向HEMT，所述横向HEMT包括：阻挡层和缓冲层，所述缓冲层具有与所述阻挡层不同的带隙，使得沿着所述缓冲层和所述阻挡层之间的界面出现二维电荷载流子气沟道；
导电衬底接触件，形成所述二维电荷载流子气沟道与所述漂移区域之间的欧姆连接；
所述横向HEMT的栅极，被配置用于控制所述二维电荷载流子气沟道中的横向电流；以及
所述垂直JFET的栅极，被配置用于控制所述漂移区域中的垂直电流。
16.根据权利要求15所述的晶体管装置，其中所述垂直JFET的夹断电压低于所述横向HEMT的击穿电压。
17.根据权利要求15所述的晶体管装置，还包括：
第一导电输出接触件，布置在所述第一横向表面上并且与所述二维电荷载流子气沟道和所述漂移电流控制区域欧姆接触；以及
第二导电输出接触件，布置在所述第二横向表面上并且与所述漂移区域欧姆接触，
其中所述横向HEMT的栅极布置在所述第一横向表面上，
其中所述垂直JFET的栅极包括所述漂移电流控制区域。
18.根据权利要求15所述的晶体管装置，还包括肖特基二极管，所述肖特基二极管电连接在所述第一导电电极和所述第二导电电极之间。
19.根据权利要求15所述的晶体管装置，其中所述缓冲层具有小于或等于1μm的厚度，并且其中所述晶体管具有至少600V的反向阻止额定值。
20.根据权利要求15所述的晶体管装置，还包括：
二极管，被连接在所述垂直JFET的漏极和所述横向HEMT的源极之间，
其中所述横向HEMT的漏极被连接到所述垂直JFET的源极，
其中所述垂直JFET的栅极被连接到所述横向HEMT的源极，以及
其中所述垂直JFET的夹断电压低于所述横向HEMT的击穿电压。
21.根据权利要求20所述的晶体管装置，其中所述横向HEMT的沟道中的载流子的迁移率高于所述垂直JFET的沟道中的载流子的迁移率。
22.根据权利要求20所述的晶体管装置，其中所述横向HEMT的泄漏电流高于所述垂直JFET的泄漏电流。
23.一种在半导体本体中形成半导体器件的方法，所述半导体本体包括第一横向表面和与所述第一横向表面相反的第二横向表面，所述方法包括：
形成第一器件区域，所述第一器件区域包括：第一导电类型的漂移区域和第二导电类型的漂移电流控制区域，所述第二导电类型与所述第一导电类型相反，所述漂移电流控制区域通过所述漂移区域与所述第二横向表面隔开；
在所述第一器件区域上形成第二器件区域，所述第二器件区域包括：阻挡层和缓冲层，所述缓冲层具有与所述阻挡层不同的带隙，并且在所述缓冲层和所述阻挡层之间的界面处出现二维电荷载流子气沟道；
在所述半导体本体中形成导电衬底接触件，所述导电衬底接触件形成所述二维电荷载流子气沟道与所述漂移区域之间的欧姆连接；以及
在所述半导体本体上形成栅极结构，所述栅极结构被配置用于控制所述二维电荷载流子气的传导状态，
其中所述第一器件区域邻接所述第二横向表面，并且所述第二器件区域邻接所述第一横向表面，以及
其中所述漂移电流控制区域被形成为使得在所述漂移电流控制区域与所述漂移区域之间的pn结处出现的空间电荷区域被配置用于阻止所述漂移区域中的垂直电流。
24.根据权利要求23所述的方法，其中形成所述第一器件区域包括：
提供第一导电类型的衬底；以及
在所述衬底上生长第一复合外延层，其中生长所述第一复合外延层包括：
在所述第一导电类型的衬底上外延生长重掺杂的第一导电类型的场停止层；以及
在所述重掺杂的第一导电类型的场停止层上外延生长轻掺杂的第一导电类型的漂移层，以及
其中通过在所述漂移层的直接邻接所述缓冲层的第一侧处形成掺杂阱，来在所述漂移层中形成所述漂移电流控制区域。
25.根据权利要求24所述的方法，其中形成所述第二器件区域包括：
在所述第一器件区域上生长半导体材料的第二复合外延层，其中生长所述第二复合外延层包括：
在所述漂移层上外延生长半导体材料层；以及
在所述半导体材料层上外延生长材料的掺杂层。
26.根据权利要求24所述的方法，其中所述衬底、所述场停止层和所述漂移层均由SiC形成，其中所述半导体材料层由GaN形成，并且其中所述半导体材料的掺杂层由AlGaN形成。
27.根据权利要求23所述的方法，其中在所述半导体本体中形成所述导电衬底接触件包括：刻蚀延伸穿过所述缓冲层和所述阻挡层的接触孔，使得所述接触孔的底部邻接所述漂移区域，以及在所述接触孔中沉积导电材料。
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