發明説明（i ) 本發明係有關於一種供放大功率的半導體裝置，尤有 關於功率電晶體之主動區域及電極的排列設置。 使用複合半導體材料之功率半導體裝置，乃可供各種 用返，例如行動電話之地區基地台的應用，而須要高速操 作及低功率消耗等之特性。第1A與1B係分別為一習知功率 半^體衣置之一單元電晶體區域中的頂視圖及咅彳視圖。以 下’在各圖式中相同的標號乃代表相同的元件。如第1A圖 與1B圖所不，一供功率放大之習知場效應電晶體（或一功率 FET)係包含一單元電晶體u的平行陣列，設在一例如砷化 鎵(GaAs)之複合半導體基材15上的主動區域1〇中，該各單 元電晶體11乃具有一閘極指！、一汲極指2，及一源極指3。 一閘極桿4會將所有的閘極指丨並聯於一閘極接墊5，一汲極 杯_6會將所有的汲極指2並聯於一汲極接墊7,及有一源極桿 8會將所有的源極指3並聯於一源極接墊9。在此構造的功率 FET中，其通道寬度必須增加才能增加放大功能。但是， 通迢見度的增加須要該等間極指！、沒極指2、及源極指3 等之長度亦相對地增加，惟此將會由於各指的内電阻增加 而使其裝置特性變差。為,避免此問題，亦可以增加平㈣ 設之電晶體的數目，而保持通道寬度不變，如此則其功率 放大率將可提升，而不會增加内電阻；但單純地增加沿通 運長度方向的主動區域來增加平行電晶體的數目，將會增 加各桿條的長度，而產生一不良的作用，即由一接墊至該 各電晶體的距離會有差異，因為該距離乃視各電晶體至^ 接塾的相對位置而定。為此原因，該較大的距離差：： 533579 五、發明説明（2 會使高速平行操作更為困難。 故本發明之-目的即為提供一種供功率放大的半導體 裝置，其可獲得-所須的功率放大率，而不會劣化上 裝置特性。 依據本發明之第-特徵，一半導體裝置係包含多數的 主動區域等，乃沿垂直於間極、汲極、源極電極指之長度 的方向來形成，而沿平行於間極、沒極、源極電極指之長 度的方向，多數重複地列設在該半導體基材的正面上，^ 一上導電層係跨越覆設著一絕緣膜之該等主動區域上方， 而曰以董子應電位來供應該等間極、汲極、源極電極中之 至y者’其中㈣閘極、沒極、源極電極係被設在各主 動區域中。 訂 依據本發明的第二特徵，該等主動區域係為互相電分 離的。 依據本發明的第三特徵，該上導電層係以-接墊來連DESCRIPTION OF THE INVENTION (i) The present invention relates to a semiconductor device for amplifying power, and more particularly to an active area of a power transistor and an arrangement of electrodes. Power semiconductor devices using composite semiconductor materials are available for various applications, such as mobile base station base stations, which require high-speed operation and low power consumption. Sections 1A and 1B are a top view and a side view, respectively, of a unit transistor region of a conventional power half body suit. In the following, the same reference numerals in the drawings represent the same elements. As shown in Figures 1A and 1B, a conventional field effect transistor (or a power FET) for power amplification is a parallel array of a single unit of transistor u, which is set in a compound such as gallium arsenide (GaAs) In the active region 10 on the semiconductor substrate 15, each unit transistor 11 has a gate finger! , A drain refers to 2, and a source refers to 3. A gate pole 4 connects all gate fingers in parallel to a gate pad 5, a drain cup_6 connects all drain fingers 2 in parallel to a drain pad 7, and a source pole 8 connects all the source fingers 3 in parallel to a source pad 9. In this structured power FET, the channel width must be increased to increase the amplification function. However, the increase in general visibility requires such extreme guidance! The lengths of the electrode fingers 2, the electrode fingers 2, and the source electrode 3 also increase relatively, but the device characteristics will deteriorate due to the increase of the internal resistance of each finger. In order to avoid this problem, you can also increase the number of transistors that are designed and keep the channel width unchanged. In this way, the power amplification rate will be increased without increasing the internal resistance; To increase the number of parallel transistors, it will increase the length of each rod, and has an adverse effect, that is, the distance from a pad to the transistors will be different, because the distance depends on the The relative position of the crystal to ^ is determined. For this reason, the larger distance difference is: 533579 5. Description of the invention (2 will make high-speed parallel operation more difficult. Therefore, the purpose of the present invention is to provide a semiconductor device for power amplification, which can be obtained by- According to the first feature of the present invention, a semiconductor device includes most active regions, etc., which is perpendicular to the length of the fingers of the intermediate electrode, the drain electrode, and the source electrode. It is formed in a direction parallel to the lengths of the inter electrode, non-electrode, and source electrode fingers. Most of them are repeatedly arranged on the front surface of the semiconductor substrate. An upper conductive layer is covered with an insulating film. Above the active areas, the Dong electrode should be used to supply the intermediate electrode, the drain electrode, and the source electrode to y. Among them, the gate, non-electrode, and source electrodes are provided in each active region. According to the second feature of the present invention, the active areas are electrically separated from each other. According to the third feature of the present invention, the upper conductive layer is connected by a -pad.
接該等閘極、汲極、源極電極中之至少一者，而對其供應 對應電位。 ;依據本發明的第四待徵，各閘極、源極、没極桿係被 σ又在σ亥半導體基材正面上—與該等主動區域電分離的區域 中’亚分別連接於該等閑極、源極、沒極電極，而對其供 應各自的共同電位。 依據本發明的第五特徵，該上導電層係連接於該等問 ^原極；及極#中之至少_者，而對其供應對應的共同 迅位。依據本發明的第六特徵，該閘極桿係被設在該等主 本紙張尺細中 A7Connect at least one of the gate, drain, and source electrodes and supply a corresponding potential to them. According to the fourth claim of the present invention, each of the gate, source, and non-pole rods is σ on the front surface of the semiconductor substrate of σ—the regions electrically separated from the active regions are respectively connected to the leisure Electrode, source electrode, and non-electrode electrode, and supply their respective common potentials. According to a fifth feature of the present invention, the upper conductive layer is connected to at least one of the original poles and at least one of the poles, and a corresponding common bit is supplied to it. According to the sixth feature of the present invention, the gate pole system is provided in the main paper size A7
動區域之間’並共同地連接於所對叙_對主輕域上的 各間極指。 依據本發明的第七特徵，該問極桿會在其交叉汲極或 源極電極的各點處，通過該錄或源極電極的底下。 依據本發明的第八特徵’該等主動區域係沿著垂直於 該等電極指的長度之方向來列設。 依據本發明的第九特徵，有一貫穿該半導體基材的貫 孔’乃被設在由平行及垂直於該等電極指之長度方向來列 設之四個相鄰主動區域所圍繞之一區域中。 依據本發明的第十特徵，該貫孔内係被塞裝一電極， 而可傳送該半導體基材的正面與背面之間的電位。 、依據本發明的第十-特徵，被塞裝在貫孔内的電極係 連接於該等閘極、源極、汲極電位中之一者。 圖式之簡單說明 本發明將可由以下說明配合所附圖式等而更清楚瞭 解，其中： 第1A圖為習知技術之一功率ρΕτ的頂視圖。 第1B圖為第！圖中之該功率ρΕτ中一單元電晶體區域 的剖視圖。 第2圖為本發明第一實施例之功率的頂視圖。 第3圖為本發明第二實施例之功率的頂視圖。 第4圖為本發明第三實施例之功率的頂視圖。 第5圖為沿第4圖之A-A，線的剖視圖。 第6圖為沿第4圖之B-B，線的剖視圖。 533579 五、發明説明（4 ) 第7圖為沿第4圖之C-C，線的剖視圖。 第8圖為沿第4圖之D-D，線的剖視圖。 第9圖為本發明第4實施例之功率fet的頂視圖。 [實施例1] 第2圖為本發明第一實施例之功率fet的頂視圖。 如第2圖所不，有一對平行的矩形主動區域10形成於該 土材15的正面J!平行電晶體的陣列會被設在該各主動 區域中。該各閘極、汲極及源極指等，會沿其指長的方方 縱列排設在該對主動區域上。由於此構造可避免該各閘 極、汲極及源極桿的長度增加，而得抑止該各接墊至所有 對應的電極指之距離差異增加其係依各電晶體在一有效區 域中的位置而定，故該各閘極、汲極、源極桿等將能幾乎 在同時提供-相同的電位於所有之各對應電極指。該各桿 係沿垂直於對應電極指的方向來延伸，且各桿與對應電極 指係由相同的導電層所製成。另一方面，該各桿接係以一 上導電層12經由一絕緣層的貫孔13來電連接於對應的接 塾。該上導電層12會交叉通過該各桿上，而以該絕緣層中 介其間。故，由於單-的.桿能提供相同的電位給在平行成 對之主動區域10中的各對應電極指等，因此該各接墊將能 以最短的路徑來電連接於該各對應電極指等。 [第二實施例] 第3圖為本發明第二實施例之功率fet的頂視圖。 如第3圖所示，-電晶體區亦可藉將及極桿與源極桿分 別列設在汲極指與源極指上而來形成，其中各桿與電極指 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） 533579The moving regions are connected to each other on the main light domain of the pair of Syrian pairs. According to a seventh feature of the invention, the interrogator rod passes under the recording or source electrode at each point where it crosses the drain or source electrode. According to the eighth feature of the present invention, the active regions are arranged along a direction perpendicular to the length of the electrode fingers. According to the ninth feature of the present invention, a through-hole 'penetrating through the semiconductor substrate is provided in an area surrounded by four adjacent active areas arranged parallel to and perpendicular to the length direction of the electrode fingers. . According to a tenth feature of the present invention, an electrode is plugged in the through hole, and the potential between the front surface and the back surface of the semiconductor substrate can be transmitted. According to the tenth feature of the present invention, the electrode plugged in the through hole is connected to one of the gate, source, and drain potentials. Brief Description of the Drawings The present invention will be more clearly understood from the following description in conjunction with the attached drawings, etc., where: Figure 1A is a top view of a power pEτ, one of the conventional techniques. Picture 1B is the first! A cross-sectional view of a unit transistor region in the power pEτ in the figure. Figure 2 is a top view of the power of the first embodiment of the present invention. Figure 3 is a top view of the power of the second embodiment of the present invention. Fig. 4 is a top view of the power of the third embodiment of the present invention. Fig. 5 is a sectional view taken along line A-A of Fig. 4; Fig. 6 is a sectional view taken along line B-B of Fig. 4; 533579 V. Description of the invention (4) Figure 7 is a sectional view taken along line C-C of Figure 4. Fig. 8 is a sectional view taken along line D-D, in Fig. 4; Fig. 9 is a top view of a power fet according to a fourth embodiment of the present invention. [Embodiment 1] Fig. 2 is a top view of a power fet according to the first embodiment of the present invention. As shown in Fig. 2, a pair of parallel rectangular active regions 10 are formed on the front surface of the earth material 15! An array of parallel transistors will be provided in the active regions. The gate, drain, and source fingers are arranged on the pair of active areas along the square of their finger length. Because this structure can prevent the length of the gate, drain and source rods from increasing, the distance difference between each pad and all corresponding electrode fingers can be suppressed from increasing, and it depends on the position of each transistor in an effective area. Depending on this, the gates, drains, source rods, etc. will be able to be provided at almost the same time-the same electricity is located at all the corresponding electrode fingers. Each rod system extends in a direction perpendicular to the corresponding electrode finger, and each rod and the corresponding electrode finger are made of the same conductive layer. On the other hand, each rod connection is electrically connected to the corresponding connection via an upper conductive layer 12 via a through hole 13 of an insulating layer. The upper conductive layer 12 crosses each of the rods and is interposed therebetween by the insulating layer. Therefore, since the single-rod. Can provide the same potential to the corresponding electrode fingers and the like in the active area 10 in parallel pairs, the pads can be electrically connected to the corresponding electrode fingers and the like in the shortest path. . [Second Embodiment] Fig. 3 is a top view of a power fet according to a second embodiment of the present invention. As shown in Figure 3, the -transistor region can also be formed by placing the pole and source poles on the drain and source fingers, respectively, where each pole and electrode finger is suitable for the Chinese country. Standard (CNS) A4 specification (210X297 mm) 533579
^間的連接係以貫孔來達成。雖在第2與第3圖中所示的 :施例僅示出有一對閘極指縱列排設，但三個或比一對更 多的多數列設方式亦包含於本發明的範圍内。 [實施例3] 第4圖為本發明之第三實施例的功率FET之頂視圖，具 口之係為一二維的單片微波積體電路。 苐5 8圖刀別為沿第4圖之α·α，，B-B，，C-C，，D-D，等 各截線之該功率FET的剖視圖。 如第4圖所示’有一矩形主動區域1 〇乃互相平行地列設 在一半絕緣GaAs基材15上，且各閘極指丨係被設在對應的 主動區域10上’而以一共同的閘極桿4來互相連接。沒極指 2及源極指3係交又地覆設在該閘極桿4上方，而以一絕緣層 14介於其間，如第5圖所示。該閘極桿4及一閘極接墊$係以 一設在該絕緣層14上之上導電層12來連接，如第6圖所示。 又該上‘屯層12儀重疊一源極指3，而以該絕緣層μ介於 其間。未與源極指等重疊的閘極桿4部份係直接設在該基材 15上，如第7圖所示；且若該基材15覆設一鈍化層例如氮化 矽膜時，則該部份的閘極桿4將會被設於該鈍化層上。在各 主動區域10上的各；;及極指2會互相連接而交又通過閘極桿* 的上方，如第8圖所示。該等源極指亦同樣如此（未示出 因為延伸於主動區域H)上方的上導電層12,會將閘極電位 供至閘極桿4,故在各電晶體n間之閘極信號的延遲時間之 差異將會被抑止。由於閘極桿4係被設在最下層，而汲極指 2及源極指3乃交叉覆設在閘極桿4上，故該閘極桿與閘極指 閲 讀 背· 之 注 意 事 項The connection between ^ is achieved through holes. Although shown in the second and third figures: the embodiment only shows that a pair of gate fingers are arranged in a row, but three or more than a pair of most arrangements are also included in the scope of the present invention. . [Embodiment 3] Fig. 4 is a top view of a power FET according to a third embodiment of the present invention, and a mouthpiece is a two-dimensional monolithic microwave integrated circuit. Fig. 58 and Fig. 8 are cross-sectional views of the power FET along the lines α · α, B-B, C-C, D-D, and so on in Fig. 4. As shown in Fig. 4, "a rectangular active region 10 is arranged in parallel with each other on a half-insulating GaAs substrate 15 and each gate finger is provided on the corresponding active region 10" with a common The gate poles 4 are connected to each other. The pole finger 2 and the source finger 3 are alternately overlaid on the gate pole 4 with an insulating layer 14 in between, as shown in FIG. 5. The gate pole 4 and a gate pad $ are connected by a conductive layer 12 provided on the insulating layer 14, as shown in FIG. Furthermore, a source finger 3 is overlapped on the upper layer 12 and the insulating layer μ is interposed therebetween. The part of the gate rod 4 that does not overlap with the source finger is directly disposed on the substrate 15 as shown in FIG. 7; and if the substrate 15 is covered with a passivation layer such as a silicon nitride film, The part of the gate pole 4 will be disposed on the passivation layer. Each of the active areas 10; and the pole fingers 2 will be connected to each other and pass through the gate pole *, as shown in FIG. 8. The source fingers are also the same (not shown because it extends over the active area H), the upper conductive layer 12 will supply the gate potential to the gate rod 4, so the gate signal between the transistors n The difference in delay time will be suppressed. Since the gate pole 4 is located at the lowest level, and the drain finger 2 and the source finger 3 are cross-overlaid on the gate pole 4, the gate pole and the gate finger are read on the back.
f 訂 %f order%
533579 五、發明説明（6 ) 頁 等^能以對裝置特性最敏感得最短路徑來互相電連接。在 本貝細例中，該上導電層僅被用來供應該間極電位，但其 亦可被用來供應該等間極、源極與没極電位中之一或一者 =上。又’假使該上導電層僅為—導電層而不足以供用於 γ Μ 5虎則其亦可被設計成一高頻波導。當該源極電位 係為接地電位時（在本實施例中係供應至源極指3等），藉著 將該上導電層設計成重疊該等源極指而以該絕緣層介於其 ]則將可开y成问頻波導的條帶線路。再者，藉著適當 選擇該絕緣層的材料或厚度，及上導電層的寬度等等，: 可獲得任何所須的傳送特性。 [實施例4 ] 訂 第九圖為本發明第四實施例之功率FET的頂視圖。雖 各閘極、源極、汲極的指狀電極未被示於該圖中，但各指 狀電極係平行於各主動區域的寬度方向來列設其上。 本貝施例的最大特徵係，該等主動區域1〇不僅橫向而 且縱向地互相平行並列排設。如第9圖所示，各主動區域ι〇 會設有一閘極接墊101來供應閘極電位，且跨越沿寬度方向 平行排列之一對主動區域，10來相對之閘極接墊等，係以該 上導電層12來互相連接。一閘極桿4會被列設在該沿寬度方 向平行排列的一對主動區域10之間，並在一交叉連接於該 上導電層12。有一對汲極接墊2〇1係跨越沿長度方向平行排 列之一對主動區域10來相對列設，並各沿著以寬度方向平 行排列之一對主動區域10的較短外側來延伸。有一對沒極 桿6係由各汲極接墊2 01沿著以寬度方向平行列之一對主動 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） 533579533579 V. Description of the Invention (6) page etc. can be electrically connected to each other by the shortest path that is most sensitive to the characteristics of the device. In this detailed example, the upper conductive layer is only used to supply the inter-electrode potential, but it can also be used to supply one or one of the inter-electrode, source, and non-electrode potentials. Also, if the upper conductive layer is only a conductive layer and is not enough for the γ M 5 tiger, it can also be designed as a high-frequency waveguide. When the source potential is a ground potential (in this embodiment, it is supplied to the source finger 3, etc.), the insulating layer is interposed therebetween by designing the upper conductive layer to overlap the source fingers] Then the strip line which can be turned into a frequency waveguide can be opened. Furthermore, by properly selecting the material or thickness of the insulating layer, the width of the upper conductive layer, etc., any desired transmission characteristics can be obtained. [Embodiment 4] The ninth figure is a top view of a power FET according to a fourth embodiment of the present invention. Although the finger electrodes of the gate, source, and drain electrodes are not shown in the figure, the finger electrodes are arranged parallel to the width direction of each active region. The biggest feature of this Bebe example is that the active areas 10 are arranged side by side in parallel with each other not only horizontally but also vertically. As shown in FIG. 9, each active area ι0 will be provided with a gate pad 101 to supply the gate potential, and spans a pair of active areas arranged in parallel in the width direction, and the gate pads 10 are opposite to each other. The upper conductive layers 12 are connected to each other. A gate pole 4 is arranged between the pair of active regions 10 arranged in parallel in the width direction, and is connected to the upper conductive layer 12 at a cross. A pair of drain pads 201 are arranged oppositely across one pair of active regions 10 arranged in parallel in the length direction, and each extend along the shorter outer side of one pair of active regions 10 arranged in parallel in the width direction. There is a pair of poleless rods 6 series, each of which is connected to each of the sink pads 2 01. One pair of active columns are arranged in parallel in the width direction. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm).
(請先閲讀背面之注意事項再填寫本頁) 區域l 〇的較長外側來平行延伸。一源極接墊3〇丨被設在沿寬 度方向平行排列的兩對主動區域10之間，並沿著該兩對主 動區域10的較短内側延伸。該源極接墊3〇丨會經由一貫孔來 導至该基材的背面。當要在一封裝體上裝設一半導體晶片 日守，通常係有四個閘極接墊與二個汲極接墊會被接線引 出，而導接於各共同的電位，否則，具有共同電位的接墊 將會被互相連接於該晶片上。 訂| -%1 如上述實施例所示，藉著增加該等主動區域的數目， 將可容易地獲得所須的放大率。該貫孔係被設在該四個主 動區域10所包圍的中央區城處，以防止它們所產生的熱會 積貯於該處。由於金屬會被鍍著而塞裝於該貫孔内，故該 貫孔不論該熱如何增加，皆能避免該熱被貯積於該處。該 貫孔亦可被設在閘極或汲極接墊處，而非在源極接墊處。 又，在上述各實施例中，各主動區域係沿長度方向及/或寬 度方向來互相平行地排列在一晶片平面上。然而，所述“沿 長度方向及/或寬度方向，，亦包括斜向排列方式，即該等主 動區域係由該矩形主動區域四邊之一邊沿45度的方向來排 列。上述各實施例有一共同的概念係為：連接紋路的小型 化將會導致因一接墊至平行連接之各電晶體的連接電阻不 同所形成的信號延遲差異增加。為避免此等缺點，故該主 動區域乃被分開設置，俾使連接線路短得足以提供一可容 忍的信號延遲差異。具言之，該主動區域係依據閘極桿的 長度來被分告彳’並使用多層連接技術，使各桿能藉一上導 電層來連接於對應接墊，以達成最短的導接路徑。此等構 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） 10 533579 A7 B7 五、發明説明（8 ) 造特徵將有助於該半導體整合裝置的整體高速操作，而不 必相反地進一步縮小其中之電晶體的微結構。 元件標號對照 1…閘極指 9，301…源極接墊 2…汲極指 10…主動區域 3 ···源極指 11…單元電晶體 4…閘極桿 12…上導電層 5，101···閘極接墊 13 · · · f 孑L 6…沒極桿 14…絕緣層 7，201…汲極接墊 15…半導體基材 8…源極桿 11 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐）(Please read the precautions on the back before filling out this page.) The longer outer side of area 10 extends in parallel. A source pad 30 is provided between two pairs of active regions 10 arranged in parallel in the width direction, and extends along the shorter inner sides of the two pairs of active regions 10. The source pad 30 is guided to the back of the substrate through a through hole. When a semiconductor wafer is installed on a package, usually there are four gate pads and two sink pads which will be led out by wiring and connected to common potentials. Otherwise, they have common potentials. The pads will be connected to each other on the chip. Order |-% 1 As shown in the above embodiment, by increasing the number of such active areas, the required magnification can be easily obtained. The through-hole system is provided at the center of the city surrounded by the four active areas 10 to prevent heat generated by them from being accumulated there. Since the metal is plated and plugged into the through hole, the through hole can prevent the heat from being stored there, regardless of the increase in the heat. The through hole can also be provided at the gate or drain pad, rather than at the source pad. In each of the above embodiments, the active regions are arranged on a wafer plane in parallel with each other along the longitudinal direction and / or the width direction. However, the "along the length direction and / or the width direction also includes an oblique arrangement, that is, the active areas are arranged in a direction of 45 degrees by one of the four sides of the rectangular active area. The above embodiments have one thing in common. The concept is that the miniaturization of the connection pattern will lead to an increase in the difference in signal delay caused by the difference in connection resistance between a pad and the transistors connected in parallel. To avoid these disadvantages, the active area is set separately In order to make the connection line short enough to provide a tolerable difference in signal delay. In other words, the active area is divided according to the length of the gate poles and uses multi-layer connection technology to enable each pole to borrow one. The conductive layer is connected to the corresponding pad to achieve the shortest conductive path. The paper size of these papers conforms to the Chinese National Standard (CNS) A4 (210X297 mm) 10 533579 A7 B7 V. Description of the invention (8) It will contribute to the overall high-speed operation of this semiconductor integrated device without having to further shrink the microstructure of the transistors in the opposite direction. 9,301 ... Source pad 2 ... Drain finger 10 ... Active area 3 ... Source electrode 11 ... Unit transistor 4 ... Gate rod 12 ... Upper conductive layer 5, 101 ... Gate pad 13 · · · F 孑 L 6… No pole 14… Insulation layer 7,201… Drain pad 15… Semiconductor substrate 8… Source pole 11 This paper size applies to China National Standard (CNS) A4 (210X297 mm) )