CN111933616B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN111933616B
CN111933616B CN202010396333.6A CN202010396333A CN111933616B CN 111933616 B CN111933616 B CN 111933616B CN 202010396333 A CN202010396333 A CN 202010396333A CN 111933616 B CN111933616 B CN 111933616B
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Prior art keywords
lead
semiconductor device
semiconductor
semiconductor element
pad
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CN202010396333.6A
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CN111933616A (zh
Inventor
齐藤光俊
坂入宽之
松冈康文
吉持贤一
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Rohm Co Ltd
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Rohm Co Ltd
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Abstract

本发明提供一种半导体装置,对多个半导体元件和控制元件进行一封装化,实现寄生电感、寄生电阻的降低。半导体装置具备:在元件主面(1a)配置有漏电极(11)、源电极(12)及门电极(13)的半导体元件(1);在元件主面(2a)配置有漏电极(21)、源电极(22)及门电极(23)的半导体元件(2);与门电极(13)及门电极(23)导通的控制元件;包括互相分离的多个引线的引线框。多个引线包括搭载半导体元件(1)的引线(4A)、搭载半导体元件(2)的引线(4B)及搭载控制元件的引线(4C),引线(4A)和引线(4B)在x方向观察互相重合,引线(4C)在y方向观察与引线(4A)以及引线(4B)双方重合。

Description

半导体装置
技术领域
本发明涉及搭载了多个半导体元件的半导体装置。
背景技术
以往,已知利用一个树脂部件对多个半导体元件进行模制的半导体装置。该半导体装置被称为系统封装。在专利文献1中公开了将两个开关元件和控制用IC一封装化的半导体装置。控制用IC是控制各开关元件的半导体元件。各开关元件根据来自控制用IC的信号进行开关动作。这种半导体装置例如安装于电子设备等电路基板,用于DC/DC转换器等电源电路。
现有技术文献
专利文献1:日本特开2003-218309号公报
近年来,伴随电子设备的节能化、高性能化,半导体装置要求消耗电力的降低、开关动作的应答性的提高等。在实现消耗电路的降低、开关动作的应答性的提高的基础上,寄生电感的降低、寄生电阻的降低是有效的。
发明内容
本发明是鉴于上述情况进行的,其目的在于提供一种多个半导体元件被一封装化的半导体装置,实现了寄生电感的降低、寄生电阻的降低。
由本发明提供的半导体装置具备:第一半导体元件,其具有在厚度方向上分离的第一主面以及第一背面,在上述第一主面配置有第一漏电极、第一源电极以及第一门电极;第二半导体元件,其具有在上述厚度方向上分离的第二主面以及第二背面,在上述第二主面配置有第二漏电极、第二源电极以及第二门电极;与上述第一门电极以及上述第二门电极导通的控制元件;以及包括互相分离的多个引线的引线框,上述多个引线包括与上述第一背面对置且搭载了上述第一半导体元件的第一引线、与上述第二背面对置且搭载了上述第二半导体元件的第二引线以及搭载了上述控制元件的第三引线,上述第一引线和上述第二引线在与上述厚度方向正交的第一方向上观察互相重合,上述第三引线在与上述厚度方向以及上述第一方向双方正交的第二方向上观察与上述第一引线以及上述第二引线双方重合。
本发明的效果如下。
根据本发明的半导体装置,在多个半导体元件和控制元件被一封装化的半导体装置中,能够降低寄生电感、寄生电阻。
附图说明
图1是表示第一实施方式的半导体装置的立体图。
图2是表示第一实施方式的半导体装置的俯视图。
图3是表示第一实施方式的半导体装置的仰视图。
图4是沿图2的IV-IV线的剖视图。
图5是沿图2的V-V线的剖视图。
图6是沿图2的VI-VI线的剖视图。
图7是表示第一实施方式的半导体元件的电路结构图。
图8是表示第二实施方式的半导体装置的俯视图。
图9是表示第三实施方式的半导体装置的俯视图。
图10是沿图9的X-X线的剖视图。
图11是表示第三实施方式的变形例的半导体装置的剖视图。
图12是表示第四实施方式的半导体装置的俯视图。
图13是表示变形例的半导体装置的立体图。
图14是表示变形例的半导体装置的仰视图。
具体实施方式
关于本发明的半导体装置的优选的实施方式,以下参照附图进行说明。另外,在相同或类似的结构要素上标注相同的符号并省略其说明。
在本发明中,“某物A与某物B在某方向上重合”只要没有特别限定,便包括“在某方向上观察,某物A与某物B的全部重合”以及“在某方向上观察,某物A与某物B的一部分重合”。另外,本发明中的“第一”、“第二”、“第三”等用语简单地作为标签进行使用,未必指对这些对象物标注顺序。
<第一实施方式>
关于第一实施方式的半导体装置A1,参照图1~图7进行说明。半导体装置A1例如用于变流器、变频器等电力转换器。
首先,关于第一实施方式的半导体装置A1的模块构造,参照图1~图6进行说明。半导体装置A1在其模块构造中具备两个半导体元件1、2、控制元件3、引线框4、多个连接部件5以及封闭部件6。另外,在半导体装置A1中,引线框4包括互相分离的多个引线4A~4J。另外,多个连接部件5包括多个金属丝5A~5N。
图1是表示半导体装置A1的立体图,表示从底面侧观察的情况。图2是表示半导体装置A1的俯视图,用想像线(双点划线)表示封闭部件6。图3是表示半导体装置A1的仰视图,用想像线(双点划线)表示封闭部件6。图4是沿图2的IV-IV线的剖视图。图5是沿图2的V-V线的剖视图。图6是沿图2的VI-VI线的剖视图。另外,在图4~图6中,省略多个连接部件5的图示。
为了方便说明,将互相正交的三个方向定义为x方向、y方向、z方向。z方向是半导体装置A1的厚度方向。x方向是半导体装置A1的俯视图(参照图2)中的左右方向。y方向是半导体装置A1的俯视图(参照图2)中的上下方向。另外,将x方向的一方设为x1方向、将x方向的另一方设为x2方向。同样,将y方向的一方设为y1方向、将y方向的另一方设为y2方向,将z方向的一方设为z1方向、将z方向的另一方设为z2方向。在本发明中,也存在将z1方向设为下、将z2方向设为上的情况。x方向、y方向相当于技术方案所记载的“第一方向”、“第二方向”。
半导体装置A1安装于电子设备等的电路基板。半导体装置A1例如是表面安装型的封装构造,在本实施方式中,例如是被称为SON(Small、Outline Non-lead)的封装形式。
两个半导体元件1、2均是发挥半导体装置A1的电气功能的元件。各半导体元件1、2是开关元件,例如是n型MOSFET。另外,各半导体元件1、2未限定为n型MOSFET,可以是p型MOSFET。另外,各半导体元件1、2未限于MOSFET,也可以是包括MISFET(Metal-Insulator-Semiconductor FET)、HEMT(High Electron Mobility Transistor:高电子移动度晶体管)的电场效果晶体管、双极晶体管或IGBT(Insulated Gate Bipolar Transistor)等其他晶体管。
如图2所示,各半导体元件1、2在俯视中(在z方向上观察)例如是矩形状。半导体元件1搭载于引线4A,半导体元件2搭载于引线4B。两个半导体元件1、2如图2以及图4所示,在x方向上排列。各半导体元件1、2的各结构材料例如包括GaN(氮化镓)。另外,各半导体元件1、2的各结构材料未限定于GaN,例如也可以包括SiC(碳化硅)、Si(硅元素)、GaAs(砷化镓)或Ga2O3(氧化镓)。半导体元件1相当于技术方案所记载的“第一半导体元件”,半导体元件2相当于技术方案所记载的“第二半导体元件”。
半导体元件1具有元件主面1a以及元件背面1b。元件主面1a以及元件主面1b在z方向上分离。元件主面1a朝向z2方向,元件背面1b朝向z1方向。元件背面1b与引线4A对置。元件主面1a相当于技术方案所记载的“第一主面”,元件背面1b相当于技术方案所记载的“第一背面”。
半导体元件1是具有三个电极的三端子元件。在本实施方式中,半导体元件1包括漏电极11、源电极12以及门电极13。漏电极11、源电极12以及门电极13配置于元件主面1a。漏电极11相当于技术方案所记载的“第一漏电极”,源电极12相当于技术方案所记载的“第一源电极”,门电极13相当于技术方案所记载的“第一门电极”。
漏电极11包括多个衬垫部111。各衬垫部111是在x方向上延伸的带状。各衬垫部111在半导体元件1的内部与漏区域导通。源电极12包括多个衬垫部121。各衬垫部121是在x方向上延伸的带状。各衬垫部121在半导体元件1的内部与源区域导通。多个衬垫部111以及多个衬垫部121在y方向上排列,交替地配置。门电极13包括两个衬垫部131、132。各衬垫部131、132在半导体元件1的内部与门区域(信道区域)导通。各衬垫部131、132在x方向上配置于距半导体元件2远的一侧的端缘部。两个衬垫部131、132在y方向上分离。在图2所示的示例中,衬垫部131在俯视中配置于x1方向侧且y1方向侧的角部。衬垫部132在俯视中配置于x1方向侧且y2方向侧的角部。两个衬垫部131、132均是同电位。另外,门电极13可以不包括衬垫部132。各衬垫部131、132相当于技术方案所记载的“第一衬垫部”。
半导体元件1从控制元件3输入驱动信号,根据该驱动信号,切换导通状态和遮断状态(进行开关动作)。该驱动信号被输入门电极13。半导体元件1相当于技术方案所记载的“第一半导体元件”。
半导体元件2具有元件主面2a以及元件背面2b。元件主面2a以及元件主面2b在z方向上分离。元件主面2a朝向z2方向,元件背面2b朝向z1方向。元件背面2b与引线4B对置。元件主面2a相当于技术方案所记载的“第二主面”,元件背面2b相当于技术方案所记载的“第二背面”。
半导体元件2是具有三个电极的三端子元件。在本实施方式中,半导体元件2包括漏电极21、源电极22以及门电极23。漏电极21、源电极22以及门电极23配置于元件主面2a。漏电极21相当于技术方案所记载的“第二漏电极”,源电极22相当于技术方案所记载的“第二源电极”,门电极23相当于技术方案所记载的“第二门电极”。
漏电极21包括多个衬垫部211。各衬垫部211是在x方向上延伸的带状。各衬垫部211在半导体元件2的内部与漏区域导通。源电极22包括多个衬垫部221。各衬垫部221是在x方向上延伸的带状。各衬垫部221在半导体元件2的内部与源区域导通。多个衬垫部211以及多个衬垫部221在y方向上排列,交替地配置。门电极23包括两个衬垫部231、232。各衬垫部231、232在半导体元件2的内部与门区域(信道区域)导通。各衬垫部231、232在x方向上配置于距半导体元件1远的一侧的端缘部。两个衬垫部231、232在y方向上分离。在图2所示的示例中,衬垫部231在俯视中配置于x2方向侧且y1方向侧的角部。衬垫部232在俯视中配置于x2方向侧且y2方向侧的角部。两个衬垫部231、232均是同电位。另外,门电极23可以不包括衬垫部232。各衬垫部231、232相当于技术方案所记载的“第二衬垫部”。
半导体元件2从控制元件3输入驱动信号,根据该驱动信号,切换导通状态和遮断状态(进行开关动作)。该驱动信号被输入门电极23。半导体元件2相当于技术方案所记载的“第二半导体元件”。
控制元件3控制两个半导体元件1、2的各开关动作。控制元件3生成用于驱动各半导体元件1、2的驱动信号,将生成的驱动信号分别向半导体元件1、2输出。控制元件3例如是IC(集成电路)。控制元件3是包括半导体材料而构成的半导体元件。控制元件3搭载于引线4C。控制元件3在y方向上观察与各半导体元件1、2的各自的一部分重合。
控制元件3具有元件主面3a以及元件背面3b。元件主面3a以及元件背面3b在z方向上分离,元件主面3a朝向z2方向,元件背面3b朝向z1方向。元件背面3b与引线4C对置。
控制元件3包括元件电极31。元件电极31配置于元件主面3a。元件电极31包括多个衬垫部311~318。多个衬垫部311~318分别是控制元件3中的输入端或输出端。各衬垫部311~318是接合连接部件5的部位。俯视中的各衬垫部311~318的配置未限定于图2所示的例子。
衬垫部311接合金属丝5L的一端,通过该金属丝5L与引线4H导通。衬垫部312接合金属丝5J的一端,通过该金属丝5J与引线4C导通。衬垫部313接合金属丝5M的一端,通过该金属丝5M与引线4I导通。衬垫部314接合金属丝5N的一端,通过该金属丝5N与引线4J导通。衬垫部315接合金属丝5F的一端,通过该金属丝5F与半导体元件1的门电极13(衬垫部131)导通。衬垫部316接合金属丝5H的一端,通过该金属丝5H与半导体元件2的门电极23(衬垫部231)导通。衬垫部317接合金属丝5K的一端,通过该金属丝5K与引线4G导通。衬垫部318接合金属丝5E的一端,通过该金属丝5E与引线4A导通。
引线框4搭载两个半导体元件1、2以及控制元件3。引线框4与多个连接部件5一起构成半导体装置A1的导通路径。引线框4由导电性的材料构成。引线框4的构成材料例如是含有Cu(铜)的金属。另外,该构成材料也可以是Cu以外的其他金属。另外,可以在引线框4的表面适当地实施电镀。如图2所示,引线框4包括互相分离的多个引线4A~4J。各引线4A~4J的一部分从封闭部件6露出,该露出的部分是将半导体装置A1安装于外部的电路基板时的端子。
引线4A搭载半导体元件1。引线4A接合多个金属丝5B的各一端,通过该多个金属丝5B与半导体元件1的源电极12导通。另外,引线4A接合多个金属丝5C的各一端,通过该多个金属丝5C与半导体元件2的漏电极21导通。另外,引线4A接合金属丝5E的一端,通过该金属丝5E与控制元件3的元件电极31(衬垫部318)导通。引线4B搭载半导体元件2。引线4B接合多个金属丝5D的各一端,通过该多个金属丝5D与半导体元件2的源电极22导通。引线4C搭载控制元件3。引线4C接合金属丝5J的一端,通过该金属丝5J与控制元件3的元件电极31(衬垫部312)导通。引线4D接合多个金属丝5A的各一端,通过该多个金属丝5A与半导体元件1的漏电极11导通。引线4E接合金属丝5G的一端,通过该金属丝5G与半导体元件1的门电极13(衬垫部132)导通。引线4F接合金属丝5I的一端,通过该金属丝5I与半导体元件2的门电极23(衬垫部232)导通。引线4G接合金属丝5K的一端,通过该金属丝5K与控制元件3的元件电极31(衬垫部317)导通。引线4H接合金属丝5L的一端,通过该金属丝5L与控制元件3的元件电极31(衬垫部311)导通。引线4I接合金属丝5M的一端,通过该金属丝5M与控制元件3的元件电极31(衬垫部313)导通。引线4J接合金属丝5N的一端,通过该金属丝5N与控制元件3的元件电极31(衬垫部314)导通。
引线4A如图2及图4所示,包括压料垫部411以及接合部412。压料垫部411和接合部412一体地形成。另外,压料垫部411和接合部412也可以分离。
压料垫部411是搭载半导体元件1的部位。半导体元件1通过未图示的接合材料接合半导体元件1。压料垫部411与元件背面1b对置。压料垫部411相当于技术方案所记载的“第一压料垫部”。
接合部412是接合多个连接部件5的任一个的部位。在本实施方式中,在接合部412上接合多个金属丝5B、多个金属丝5C以及金属丝5E的各一端。接合部412通过多个金属丝5B与半导体元件1的源电极12导通,并且通过多个金属丝5C与半导体元件2的漏电极21导通。另外,接合部412通过金属丝5E与控制元件3的元件电极31(衬垫部318)导通。接合部412在俯视中配置于半导体元件1与半导体元件2之间。接合部412相当于技术方案所记载的“第一接合部”。
如图2及图4所示,引线4B包括压料垫部421以及接合部422。压料垫部412和接合部422一体地形成。另外,压料垫部421和接合部422可以分离。
压料垫部421是搭载半导体元件2的部位。半导体元件2通过未图示的接合材料接合半导体元件2。压料垫部421与元件背面2b对置。压料垫部421相当于技术方案所记载的“第二压料垫部”。
接合部422是接合多个连接部件5的任一个的部位。在本实施方式中,在接合部422上接合多个金属丝5D的各一端。接合部422通过多个金属丝5D与半导体元件2的源电极22导通。接合部422相当于技术方案所记载的“第二接合部”。
如图2所示,引线4A以及引线4B均配置于比引线4C靠y2方向。引线4A以及引线4B均在y方向上观察与引线4C重合,并且在x方向上观察不与引线4C重合。另外,引线4A和引线4B在x方向上邻接。引线4A和引线4B在x方向上观察是重合的。
引线4E和引线4F在x方向上观察互相重合。如图2所示,引线4E在俯视中配置于衬垫部132的附近,与其他引线(除了引线4A)相比靠近衬垫部132。如图2所示,引线4F在俯视中配置于衬垫部232的附近,与其他引线(除了引线4B)相比靠近衬垫部132。
引线4D与引线4B的接合部422在x方向上观察互相重合。另外,引线4D、引线4A以及引线4B在x方向上观察互相重合,并且在x方向上以该顺序排列。引线4D与半导体元件1的漏电极11导通,引线4A与半导体元件1的源电极12以及半导体元件2的漏电极21导通,引线4B与半导体元件2的源电极22导通。由此,经由两个半导体元件1、2的从引线4D到引线4B的电流路径沿x方向形成。
引线4E、引线4D、引线4G以及引线4H在y方向上观察互相重合,并且在y方向上以该顺序排列。另外,引线4F、引线4B的接合部422、引线4I以及引线4J在y方向观察互相重合,并且在y方向上以该顺序排列。
引线4G、引线4H、引线4I以及引线4J在x方向上观察分别与引线4C重合。两个引线4G、4H配置于比引线4C靠x1方向,两个引线4I、4J配置于比引线4C靠x2方向。引线4G和引线4I在x方向上观察互相重合。引线4H和引线4J在x方向上观察互相重合。
如图3~图6所示,各引线4A~4J形成有凹部49。在各引线4A~4J中,凹部49是从朝向z1方向的面朝向z2方向凹陷的部分。如图3所示,凹部49在俯视中沿各引线4A~4J的外周缘形成。凹部49被封闭部件6覆盖。在图4~图6所示的例子中,凹部49的壁面弯曲,但也可以不弯曲。凹部49为了防止引线4A~4J脱落而设置。
在本实施方式中,引线4A相当于技术方案所记载的“第一引线”。引线4B相当于技术方案所记载的“第二引线”。引线4C相当于技术方案所记载的“第三引线”。引线4D相当于技术方案所记载的“第四引线”。引线4E相当于技术方案所记载的“第五引线”。引线4F相当于技术方案所记载的“第六引线”。各引线4G~4J分别相当于技术方案所记载的“第七引线”。
多个连接部件5分别导通分离的两个部件。各连接部件5由导电性的材料构成。如图2所示,多个连接部件5包括多个金属丝5A~5N。各金属丝5A~5N是所谓的接合金属丝。各金属丝5A~5N的构成材料例如可以是含有Au(金)的金属、含有Al(铝)的金属或含有Cu的金属等的任一个。
如图2所示,多个金属丝5A分别将一端接合于半导体元件1的漏电极11的衬垫部111,将另一端接合于引线4D。多个金属丝5B分别将一端接合于半导体元件1的源电极12的衬垫部121,将另一端接合于引线4A的接合部412。多个金属丝5C分别将一端接合于半导体元件2的漏电极21的衬垫部211,将另一端接合于引线4A的接合部412。多个金属丝5D分别将一端接合于半导体元件2的源电极22的衬垫部221,将另一端接合于引线4B的接合部422。金属丝5E将一端接合于控制元件3的元件电极31的衬垫部318,将另一端接合于引线4A的接合部412。金属丝5F将一端接合于控制元件3的元件电极31的衬垫部315,将另一端接合于半导体元件1的门电极13的衬垫部131。金属丝5G将一端接合于引线4E,将另一端接合于半导体元件1的门电极13的衬垫部132。金属丝5H将一端接合于控制元件3的元件电极31的衬垫部316,将另一端接合于半导体元件2的门电极23的衬垫部231。金属丝5I将一端接合于引线4F,将另一端接合于半导体元件2的门电极23的衬垫部232。金属丝5J将一端接合于控制元件3的元件电极31的衬垫部312,将另一端接合于引线4C。金属丝5K将一端接合于控制元件3的电子电极31的衬垫部317,将另一端接合于引线4G。金属丝5L将一端接合于控制元件2的元件电极31的衬垫部311,将另一端接合于引线4H。金属丝5M将一端接合于控制元件3的元件电极31的衬垫部313,将另一端接合于引线4I。金属丝5N将一端接合于控制元件3的元件电极31的衬垫部314,将另一端接合于引线4J。
在图2所示的例子中,相对于三个衬垫部111的各个分别接合三个金属丝5A。另外,相对于两个衬垫部121的各个,分别接合三个金属丝5C。另外,相对于两个衬垫部221的各个,分别接合三个金属丝5D。另外,在金属丝5E中,接合于接合部412的部分在x方向上位于各金属丝5B的接合于接合部412的部分和各金属丝5C的接合于接合部412的部分之间。金属丝5A~5N的数量分别未限定于图2所示的数量,可以考虑各衬垫部111、121、131、132、211、221、231、232、311~318的俯视中的面积、各金属丝5A~5N的线径以及在各金属丝5A~5N中流动的电流量等适当改变。
在本实施方式中,金属丝5A相当于技术方案记载的“第一连接部件”。金属丝5B相当于技术方案所记载的“第二连接部件”。金属丝5C相当于技术方案所记载的“第三连接部件”。金属丝5D相当于技术方案所记载的“第四连接部件”。金属丝5E相当于技术方案所记载的“第五连接部件”。金属丝5F相当于技术方案所记载的“第六连接部件”。金属丝5G相当于技术方案所记载的“第七连接部件”。金属丝5H相当于技术方案所记载的“第八连接部件”。金属丝5I相当于技术方案所记载的“第九连接部件”。各金属丝5K~5N相当于技术方案所记载的“第十连接部件”。
封闭部件6是半导体元件1、2以及控制元件3的保护部件。封闭部件6覆盖半导体元件1、2、控制元件3、引线框4的一部分以及多个连接部件5。封闭部件6的构成材料是电绝缘鞋的树脂材料,例如是环氧树脂。封闭部件6例如是俯视矩形状。另外,封闭部件6的形状未限定于图1~图6所示的例子。封闭部件6具有树脂主面61、树脂背面62以及多个树脂侧面631~634。
如图4~图6所示,树脂主面61以及树脂背面62在z方向上分离。树脂主面61朝向z2方向,树脂背面62朝向z1方向。各引线4A~4J的一部分(朝向z1方向的面)从树脂背面62露出。多个树脂侧面631~634的各个在z方向上被树脂主面61以及树脂背面62夹持,并且连接于这两方。树脂侧面631、632在x方向上分离,树脂侧面631朝向x1方向,树脂侧面632朝向x2方向。树脂侧面633、634在y方向上分离,树脂侧面633朝向y1方向,树脂侧面634朝向y2方向。
接着,参照图7说明第一实施方式的半导体装置A1的电路结构。另外,在以下的说明中,存在将基准电位称为接地电压VGND的情况。
图7表示将半导体装置A1适用于同期整流方式的降压型DC/DC转换器的情况的电路图。该DC/DC转换器是使输入电压Vin降压并生成期望的输出电压Vout的电源电路。输出电压Vout被供给到负荷LO。另外,图7所示的电路图是一例。
如图7所示,半导体装置A1在其电路结构中具备多个外部端子T1~T10、两个半导体元件1、2以及控制元件3。另外,如图7所示,半导体装置A1连接有两个外部电源PS1、PS2以及多个分立部件(多个电容C1~C4以及手摇件L1)。另外,多个分立部件的一个以上可以内置于半导体装置A1。
外部电源PS1产生用于驱动控制元件3的电源电压VCC。外部电源PS1的高电位侧的端子连接于外部端子T1。外部电源PS1的低电位侧的端子连接于第一接地端GND1,与基准电位接地。在外部电源PS1上并列地连接有电容器C1。电容器C1是使电源电压VCC稳定的旁路电容器。
外部电源PS2产生输入电压Vin。外部电源PS2的高电位侧的端子与外部端子T3连接。外部电源PS2的低电位侧的端子与第二接地端GND2连接,与基准电位接地。另外,表示第一接地端GND1以及第二接地端GND2均是基准电位的接地端的情况,但也可以使第一接地端GND1的基准电位与第二接地端GND2的基准电位不同。在外部电源PS2上并列地连接有电容器C2。电容器C2是使输入电压Vin稳定的旁路电容器。
手摇件L1的第一端连接于外部端子T7,第二端连接于负荷LO以及电容器C3。电容器C3的第一端连接于手摇件L1,第二端连接于第二接地端GND2。手摇件L1和电容器C3构成LC过滤器电路。电容器C4的第一端连接于外部端子T7,第二端连接于外部端子T8。电容器C4与后述的二极管D1一起构成模拟电路。电容器C4产生引导电压VB。
外部端子T1是电源电压VCC的输入端。外部端子T1连接于外部电源PS1的高电位侧的端子。外部端子T1在半导体装置A1的内部连接于控制元件3(后述的连接端子TC1)。外部端子T1例如与半导体装置A1的模块构造中的引线4H对应。
外部端子T2连接于第一接地端GND1,与基准电位接地。外部端子T2在半导体装置A1的内部连接于控制元件3(后述的连接端子TC2)。外部端子T2例如与半导体装置A1的模块构造中的引线4C对应。
外部端子T3是输入电压Vin的输入端。外部端子T3连接于外部电源PS2的高电位侧的端子。外部端子T3在半导体装置A1的内部连接于半导体元件1的漏极。外部端子T3例如与半导体装置A1的模块构造中的引线4D对应。
外部端子T4连接于第二接地端GND2,与基准电位接地。外部端子T4在半导体装置A1的内部中连接于半导体元件2的源极。外部端子T4例如与半导体装置A1的模块构造中的引线4B对应。
外部端子T5是控制信号SH的输入端。控制信号SH例如是交替地切换高电平和低电平的矩形脉冲波。外部端子T5在半导体装置A1的内部连接于控制元件3(后述的连接端子TC3)。外部端子T5例如与半导体装置A1的模块构造中的引线4I对应。
外部端子T6是控制信号SL的输入端。控制信号SL是用于控制半导体元件2的开关动作的信号。控制信号SL例如是交替地切换高电平和低电平的矩形脉冲波。控制信号SL和控制信号SH的高电平期间和低电平期间交替地反转。外部端子T6在半导体装置A1的内部连接于控制元件3(后述的连接端子TC4)。外部端子T6例如与半导体装置A1的模块构造中的引线4J对应。
外部端子T7是输出电压Vsw的输出端。输出电压Vsw是通过半导体元件1和半导体元件2的各开关动作生成的电压信号。外部端子T7在半导体装置A1的内部连接于半导体元件1的源极与半导体元件2的漏极的连接点。外部端子T7例如与半导体装置A1的模块构造中的引线4A对应。
外部端子T8是引导电压VB的输入端。引导电压VB是由电容器C4以及后述的二极管D1生成的电压信号。外部端子T8连接电容器C4的第二端。外部端子T8在半导体装置A1的内部连接于控制元件3(后述的连接端子TC7)。外部端子T8例如与半导体装置A1的模块构造中的引线4G对应。
外部端子T9是驱动信号GH2的输入端。驱动信号GH2是用于驱动半导体元件1的信号,从未图示的外部设备直接输入。驱动信号GH2例如是交替地切换高电平和低电平的矩形脉冲波。外部端子T9在半导体装置A1的内部连接于半导体元件1的门极。外部端子T9例如与半导体装置A1的模块构造中的引线4E对应。
外部端子T10是驱动信号GL2的输入端。驱动信号GL2是用于驱动半导体元件2的信号,从未图示的外部设备直接输入。驱动信号GL2例如是交替地切换高电平和低电平的矩形脉冲波。驱动信号GH2和驱动信号GL2的高电平期间和低电平期间互相反转。外部端子T10在半导体装置A1的内部连接于半导体元件2的门极。外部端子T10例如与半导体装置A1的模块构造中的引线4F对应。
另外,电路结构中的各外部端子T1~T10、模块构造中的各引线4A~4J的对应关系未限定于上述内容。例如各外部端子T1、T5、T6、T8、各引线4G~4J的对应关系的组合能适当改变。该对应关系的组合只要根据控制元件3的衬垫部311、313、314、317的俯视中的配置适当改变即可。
两个半导体元件1、2如上所述,由n型MOSFET构成。各半导体元件1、2根据输入门极的驱动信号GH1、GH2、GL1、GL2切换导通装置(接通状态)和遮断状态(断开状态)。两个半导体元件1、2构成半桥式电路,半导体元件1是该开关电路的上臂,半导体元件2是该开关电路的下臂。
半导体元件1的漏极连接于外部端子T3,半导体元件1的源极连接于半导体元件2的漏极。半导体元件1的门极连接于控制元件3(后述的连接端子TC5),并且连接于外部端子T9。
半导体元件1通过从控制元件3向门极输入驱动信号GH1,根据该驱动信号GH1进行开关动作。半导体元件1在输入门极的驱动信号GH1为高电平时为导通状态,输入门极的驱动信号GH1为低电平时为遮断状态。另外,半导体元件1通过从外部端子T9向门极输入驱动信号GH2根据该驱动信号GH2进行开关动作。半导体元件1在输入门极的驱动信号GH2为高电平时为导通状态,输入门极的驱动信号GH2为低电平时为遮断状态。另外,半导体元件1为常开类型,但也可以是常闭类型。另外,输入半导体元件1的门极的信号可以是两个驱动信号GH1、GH2的双方,也可以是任一方。
半导体元件2的漏极连接于半导体元件1的源极,半导体元件2的源极连接于外部端子T4。半导体元件2的门极连接于控制元件3(后述的连接端子TC6),并且连接于外部端子T10。
半导体元件2通过从控制元件3向门极输入驱动信号GL1,根据该驱动信号GL1进行开关动作。半导体元件2在输入门极的驱动信号GL1为高电平时为导通状态,输入门极的驱动信号GL1为低电平时为遮断状态。另外,半导体元件2通过从外部端子T10向门极输入驱动信号GL2根据该驱动信号GL2进行开关动作。半导体元件2在输入门极的驱动信号GL2为高电平时为导通状态,输入门极的驱动信号GL2为低电平时为遮断状态。另外,半导体元件2为常开类型,但也可以是常闭类型。另外,输入半导体元件2的门极的信号可以是两个驱动信号GL1、GL2的双方,也可以是任一方。
半导体元件1的源极与半导体元件2的漏极的连接点连接于外部端子T7,并且连接于控制元件3(后述的连接端子TC8)。通过半导体元件1的开关动作和半导体元件2的开关动作向外部端子T7施加输出电压Vsw。
控制元件3主要控制两个半导体元件1、2的开关动作。控制元件3基于控制信号SH、SL生成驱动信号GH1、GH2,将生成的驱动信号GH1、GL1输入半导体元件1、2。控制元件3在其内部电路中包括多个连接端子TC1~TC8、两个驱动电路DR1、DR2以及二极管D1。控制元件3是将两个驱动电路DR1、DR2以及二极管D1一芯片化的IC。
连接端子TC1连接于外部端子T1,是控制元件3中的电源电压VCC的输入端。连接端子TC2连接于外部端子T2,与基准电位接地。连接端子TC3连接于外部端子T5,是控制元件3中的控制信号SH的输入端。连接端子TC4连接于外部端子T6,是控制元件3中的控制信号SL的输入端。连接端子TC5是驱动信号GH1的输出端。连接端子TC5连接于半导体元件1的门极。连接端子TC6是驱动信号GL1的输出端。连接端子TC6连接于半导体元件2的门极。连接端子TC7连接于外部端子T8,是控制元件3中的引导电压VB的输入端。连接端子TC8连接于半导体元件1(源极)与半导体元件2(漏极)的连接点。
驱动电路DR1基于所输入的控制信号SH生成驱动信号GH1。驱动信号GH1是用于使半导体元件1进行开关动作的信号,是将控制信号SH提升至半导体元件1的开关动作所需的电平的信号。驱动电路DR1从连接端子TC5输出所生成的驱动信号GH1。连接端子TC5连接于半导体元件1的门极,因此驱动信号GH1被输入半导体元件1的门极。驱动信号GH1是使引导电压VB为高电平、使半导体元件1的源极电压为低电平的信号。半导体元件1的源极电压通过连接端子TC8被输入驱动电路DR1。半导体元件1的门极电压以半导体元件1的源极电压为基准而被施加。
驱动电路DR2基于所输入的控制信号SL生成驱动信号GL1。驱动信号GL1是用于使半导体元件2进行开关动作的信号,是将控制信号SL提升至半导体元件2的开关动作所需的电平的信号。驱动电路DR2将所生成的驱动信号GL1从连接端子TC6输出。连接端子TC6连接于半导体元件2的门极,因此驱动信号GL1被输入半导体元件2的门极。驱动信号GL1是使电源电压VCC为高电平、使接地电压VGND为低电平的信号。半导体元件2的门极电压以接地电压VGND为基准而被施加。
二极管D1的正极连接于连接端子TC1,阴极连接于连接端子TC7。二极管D1与电容器C4一起构成引导电路。引导电路生成引导电压VB,将该电压供给到驱动电路DR1。另外,二极管D1可以配置于控制元件3的外部。
接着,关于半导体装置A1的动作例进行说明。
半导体装置A1若从外部端子T5、T6向控制元件3输入控制信号SH、SL,则通过控制元件3生成驱动信号GH1、GL1。并且,从控制元件3向半导体元件1、2的各门极输入各驱动信号GH1、GL1。或者,从各外部端子T9、T10向半导体元件1、2的各门极输入各驱动信号GH2、GL2。由此,半导体元件1为导通状态且半导体元件2为遮断状态的第一期间和半导体元件1为遮断状态且半导体元件2为导通状态的第二期间交替地反复。此时,在第一期间中,对外部端子T7施加输入电压Vin。另一方面,在第二期间中,外部端子T7与基准电位接地(对外部端子T7施加接地电压VGND)。因此,从外部端子T7的输出电压Vsw为高电平是输入电压Vin、低电平是接地电压VGND的脉冲波。并且,输出电压Vsw通过利用手摇件L1和电容器C3平滑化而转换为直流电压的输出电压Vout。半导体装置A1通过如上那样进行动作,将输入电压Vin变压(降压)为输出电压Vout。
第一期间和第二期间以预定的周期交替地反复,根据与一周期中的第一期间与第二期间的比率,能够改变降压比。例如,在第一期间为一周期的25%(第二期间为一周期的75%)时,输出电压Vout变压为输入电压Vin的1/4(Vout=Vin×(25/100))。另外,在第一期间与第二期间之间可以设置半导体元件1、2均为遮断状态的空载时间。
如上那样构成的半导体装置A1的作用效果如下。
根据第一实施方式,半导体装置A1具备引线4A、引线4B以及引线4C。引线4A和引线4B在x方向上观察互相重合,引线4C在y方向观察与引线4A以及引线4B的双方重合。引线4A搭载有半导体元件1,引线4B搭载有半导体元件2,引线4C搭载有控制元件3。由此,与专利文献1所记载的半导体装置相比,能够缩短半导体元件1与半导体元件2的分离距离。具体地说,在专利文献1记载的半导体装置中,在俯视中,两个半导体元件(开关元件)配置于夹着控制元件(控制用IC)互相相反侧。因此,需要使两个半导体元件的连接避开控制元件地配线,存在配线距离变长的倾向。另一方面,在半导体装置A1中,由于在半导体元件1与半导体元件2之间未配置控制元件3,因此能够缩短连接半导体元件1和半导体元件2的配线的距离(在本实施方式中,各金属丝5B、5C以及引线4A的一部分的各长度)。因此,半导体装置A1能够实现寄生电感、寄生电阻的降低,因此能实现高效率化以及节能化。
根据第一实施方式,引线4D、引线4A以及引线4B在x方向上重合,并且在x方向上按该顺序排列。另外,半导体元件1、2的各衬垫部111、121、211、221分别是在x方向上延伸的带状。由此,半导体装置A1能够使流经半导体元件1的漏极-源极以及半导体元件2的漏极-源极的电流的路径(动力类电流路径)的配线为直线状。该动力类电流路径是半导体装置A1的电力转换中的电流路径。尤其在半导体元件1、2进行高频驱动的情况下,动力类电流路径的配线也不为直角配线,因此作为干扰对策是有效的。
根据第一实施方式,引线4A包括压料垫部411以及接合部412,这些一体地形成。由此,能够将来自半导体元件1的热量不仅扩散到压料垫部411,还扩散到接合部412。因此,半导体装置A1能够抑制由于半导体元件1的发热而使半导体元件1的结合温度上升。结合温度的上升是半导体元件1损坏的原因。即,半导体装置A1能够抑制半导体元件1的损坏。同样,引线4B包括压料垫部421以及接合部422,这些一体地形成。由此,能够将来自半导体元件2的热量不仅扩散到压料垫部421,还能扩散到接合部422。因此,半导体装置A1能够抑制由于半导体元件2的发热而使半导体元件2的结合温度上升。即,半导体装置A1能够抑制半导体元件2的损坏。
根据第一实施方式,半导体元件1的门电极13的衬垫部131配置于元件主面1a中的在y方向上靠近引线4C的端缘侧。由此,半导体装置A1能够缩短俯视中的衬垫部131与控制元件3的分离距离。因此,由于能够缩短金属丝5F的长度,因此能够抑制金属丝5F的寄生电感、寄生电阻。尤其由于金属丝5F是驱动信号GH1的传送线,因此能够抑制半导体元件1的开关动作的应答性的下降、开关动作的误动作。同样,半导体元件2的门电极23的衬垫部231配置于元件主面2a中的在y方向上靠近引线4C的端缘侧。由此,半导体装置A1能够缩短俯视中的衬垫部231与控制元件3的分离距离。因此,由于能够缩短金属丝5H的长度,因此能够抑制金属丝5H的寄生电感、寄生电阻。尤其由于金属丝5H是驱动信号GL1的传送线,因此能够抑制半导体元件2的开关动作的应答性的下降、开关动作的误动作。
<第二实施方式>
接着,参照图8关于第二实施方式的半导体装置A2进行说明。图8是表示半导体装置A2的俯视图,以想象线(双点划线)表示封闭部件6。
如图8所示,半导体装置A2与半导体装置A1相比,引线框4的结构不同。具体地说,半导体装置A2的引线框4与半导体装置A1的引线框4不同,不包括引线4E、4F。
如图8所示,半导体装置A2的引线框4以没有引线4E的量将引线4D扩张至配置有引线4E的位置。同样,如图8所示,以没有引线4F的量将引线4B的接合部422扩张至配置有引线4E的位置。另外,由于没有引线4E、4F,因此多个连接部件5可以不包括金属丝5G、5I。
根据第二实施方式,半导体装置A2与半导体装置A1相同,具备引线4A、引线4B以及4C。引线4A与引线4B在x方向上观察互相重合,引线4C在y方向上观察与引线4A以及引线4B的双方重合。因此,半导体装置A2与半导体装置A1相同,能够缩短连接半导体元件1和半导体元件2的配线的距离(在本实施方式中,各金属丝5B、5C以及引线4A的一部分的各长度)。因此,半导体装置A2能够实现寄生电感、寄生电阻的降低,因此能够实现高效率化以及节能化。
根据第二实施方式,半导体装置A2与半导体装置A1相比,引线4D扩张。由此,半导体装置A2与半导体装置A1相比,能降低引线4D中的配线电阻。尤其由于引线4D是上述的动力类电流路径的一部分,因此半导体装置A2与半导体装置A1相比,能抑制电力变换中的电力损失。同样,半导体装置A2与半导体装置A1相比,引线4B的接合部422扩张。由此,半导体装置A2与半导体装置A1相比,能降低引线4B中的配线电阻。尤其由于引线4B是上述的动力类电流路径的一部分,因此半导体装置A2与半导体装置A1相比,能抑制电力变换中的电力损失。另外,引线4B搭载有半导体元件2,传递来自半导体元件2的热量。由此,通过引线4B(接合部422)扩张,能够提高来自半导体元件2的热量的扩散效率。
<第三实施方式>
接着,参照图9以及图10说明第三实施方式的半导体装置A3。图9是表示半导体装置A3的俯视图,以想象线(双点划线)表示封闭部件6。图10是沿图9的X-X线的剖视图。另外,即使在半导体装置A3中,也与第二实施方式相同,引线框4可以不包括引线4E、4F。
如图9以及图10所示,半导体装置A3与半导体装置A1相比,在多个连接部件5代替金属丝5A、5B、5C、5D而具备夹子7A、7B、7C、7D的方面不同。另外,图9所示的半导体装置A3与半导体装置A1相比,在半导体元件1中,多个衬垫部111(漏电极11)和多个衬垫部121(源电极12)交替。
夹子7A~7D分别折弯板状的金属部件而成。夹子7A~7D的结构材料例如是含有Cu的金属或含有Al的金属等。或者,也可以是CIC(Copper-Invar-Copper)等金属包层材料。另外,在图10所示的示例中,各夹子7A~7D的形状未限定为图9所示的示例。
根据第三实施方式,半导体装置A3与半导体装置A1相同,具备引线4A、引线4B以及4C。引线4A和引线4B在x方向上观察互相重合,引线4c在y方向上观察与引线4A以及引线4B的双方重合。因此,半导体装置A3与半导体装置A1相同,能够缩短连接半导体元件1和半导体元件2的配线的距离(在本实施方式中,各夹子7B、7C以及引线4A的一部分的各长度)。因此,半导体装置A3能够实现寄生电感、寄生电阻的降低,因此能够实现高效率化以及节能化。
根据第三实施方式,多个连接部件5代替金属丝5A包括夹子7A。夹子7A与金属丝5A相比,能够减小配线电阻。尤其由于夹子7A是上述的动力类电流路径的一部分,因此半导体装置A3与半导体装置A1相比,能够抑制电力变换中的电力损失。同样,多个连接部件5代替金属丝5B、5C、5D包括夹子7B、7C、7D。各夹子7B、7C、7D与各金属丝5B、5C、5D相比,能够减小配线电阻。尤其由于各夹子7B、7C、7D分别是上述的动力类电流路径的一部分,因此半导体装置A3与半导体装置A1相比,能够抑制电力变换中的电力损失。
在第三实施方式中,表示各夹子7A~7D是一部分折弯了的构造的情况,但并未限定于此。例如,如图11所示,各夹子7A~7D可以是改变了其一部分的厚度(z方向的尺寸)的构造。图11是该变形例的半导体装置的剖视图,与图10所示的剖面对应。例如,如图11所示,各夹子7A~7D的与半导体元件1或者半导体元件2接合的部分薄,并且与引线4A、4B、4D的任一个接合的部分厚。
在第三实施方式中,夹子7A具有梳齿状的部分,表示该梳齿状的部分与多个衬垫部111(漏电极11)接合的情况,但并未限定于此。例如,可以分别具备带状的多个夹子7A,在多个衬垫部111上分别接合一个夹子7A。即使在夹子7B~7D中也相同。
<第四实施方式>
接着,参照图12说明第四实施方式的半导体装置A4。图12是表示半导体装置A4的俯视图,以想象线(双点划线)表示封闭部件6。另外,即使在半导体装置A4中,也与第二实施方式相同,引线框4可以不包括引线4E、4F。另外,即使在半导体装置A4中,也与第三实施方式相同,可以代替各金属丝5A~5D,使用各夹子7A~7D。
如图12所示,半导体装置A4与半导体装置A1相比,半导体元件1、2的各电极(漏电极11、21以及源电极12、22)的结构不同。具体地说,各衬垫部111、121、211、221的俯视形状不同。
半导体装置A4的各衬垫部111带锥形。具体地说,各衬垫部111在x方向上从x1方向侧的端缘向x2方向侧的端缘,y方向的尺寸小。各衬垫部111在俯视中大致是三角形。另外,在各衬垫部121、衬垫部211、衬垫部221上也带锥形。具体地说,各衬垫部121在x方向上从x2方向侧的端缘向x1方向侧的端缘,y方向的尺寸小。各衬垫部211在x方向上从x1方向侧的端缘向x2方向侧的端缘,y方向的尺寸小。各衬垫部221在x方向上从x2方向侧的端缘向x1方向侧的端缘,y方向的尺寸小。各衬垫部121、211、221分别在俯视中大致是三角形。
根据第四实施方式,半导体装置A4与半导体装置A1相同,具备引线4A、引线4B以及4C。引线4A和引线4B在x方向上观察互相重合,引线4C在y方向上观察与引线4A以及引线4B的双方重合。因此,半导体装置A4与半导体装置A1相同,能够缩短连接半导体元件1和半导体元件2的配线的距离(在本实施方式中,各金属丝5B、5C以及引线4A的一部分的各长度)。因此,半导体装置A4能够实现寄生电感、寄生电阻的降低,因此能够实现高效率化以及节能化。
在第一实施方式至第四实施方式中,表示在各半导体装置A1~A4的各引线4A~4J上形成有凹部49的情况,但并未限定于此,也可以不形成凹部49。另外,在各半导体装置A1~A4中,表示凹部49沿俯视中的各引线4A~4J的外周缘形成的情况,但并未限定于此。例如,如图13所示,也可以沿俯视中的各引线4A~4J的端缘中与树脂侧面631~634的任一个接触的端缘形成凹部49。图13是表示该变形例的半导体装置的立体图,表示从底面侧观察的情况。在该情况下,在封闭部件6上沿俯视中的外周缘形成凹部69。凹部49和凹部69连接。图13所示的半导体装置在通过焊接安装于电子设备等的电路基板时容易形成焊接焊缝。因此,能够提高通过目视确认作为无引线封装的半导体装置的焊接状态的可能性。
在第一实施方式至第四实施方式中,表示各半导体装置A1~A4是SON型的封装形式的情况,但并未限定于此,也可以由其他封装形式构成。例如,也可以由BGA(Ball GridArray)型、LGA(Land Grid Array)型、QFP(Quad Flat Package)型、QFN(Quad Flat Non-lead)型等的封装形式构成。另外,这些封装形式是一例,并未限定于此。例如图14表示由QFN型的封装形式形成的半导体装置(仰视图)。
本发明的半导体装置并未限定于上述实施方式。本发明的半导体装置的各部的具体的结构能自如地进行多种设计改变。

Claims (24)

1.一种半导体装置,其特征在于,
具备:
第一半导体元件,其具有在厚度方向上分离的第一主面以及第一背面,在上述第一主面配置有第一漏电极、第一源电极以及第一门电极;
第二半导体元件,其具有在上述厚度方向上分离的第二主面以及第二背面,在上述第二主面配置有第二漏电极、第二源电极以及第二门电极;
与上述第一门电极以及上述第二门电极导通的控制元件;
包括互相分离的多个引线的引线框;
一端接合于上述第一源电极的第二连接部件;以及
一端接合于上述第二漏电极的第三连接部件,
上述多个引线包括与上述第一背面对置且搭载了上述第一半导体元件的第一引线、与上述第二背面对置且搭载了上述第二半导体元件的第二引线以及搭载了上述控制元件的第三引线,
在与上述厚度方向正交的第一方向上观察时,上述第一引线和上述第二引线互相重合,
在与上述厚度方向以及上述第一方向双方正交的第二方向上观察时,上述第三引线与上述第一引线以及上述第二引线双方重合,
上述第一引线包括接合了上述第一半导体元件的第一压料垫部以及接合了上述第二连接部件的另一端的第一接合部,
在上述厚度方向上观察时,上述第一接合部位于上述第一半导体元件与上述第二半导体元件之间,
上述第三连接部件的另一端接合于上述第一接合部。
2.根据权利要求1所述的半导体装置,其特征在于,
上述第一门电极在上述第一方向上配置于远离上述第二半导体元件的端缘部,
上述第二门电极在上述第一方向上配置于远离上述第一半导体元件的端缘部。
3.根据权利要求2所述的半导体装置,其特征在于,
上述第一漏电极以及上述第一源电极均是在上述第一方向上延伸的带状,并且在上述第二方向上排列。
4.根据权利要求3所述的半导体装置,其特征在于,
上述第二漏电极以及上述第二源电极均是在上述第一方向上延伸的带状,并且在上述第二方向上排列。
5.根据权利要求4所述的半导体装置,其特征在于,
还具备一端接合于上述第一漏电极的第一连接部件,
上述多个引线还包括接合了上述第一连接部件的另一端的第四引线,
在上述第一方向上观察时,上述第四引线与上述第一引线以及上述第二引线双方重合,并且,在上述第一方向上夹着上述第一引线而位于上述第二引线的相反侧。
6.根据权利要求5所述的半导体装置,其特征在于,
上述第一压料垫部和上述第一接合部一体地形成。
7.根据权利要求6所述的半导体装置,其特征在于,
还具备一端接合于上述第二源电极的第四连接部件,
上述第二引线包括接合了上述第二半导体元件的第二压料垫部以及接合了上述第四连接部件的另一端的第二接合部,
在上述厚度方向上观察时,上述第二压料垫部比上述第二接合部靠近上述第一压料垫部。
8.根据权利要求7所述的半导体装置,其特征在于,
上述第二压料垫部和上述第二接合部一体地形成。
9.根据权利要求8所述的半导体装置,其特征在于,
还具备一端接合于上述控制元件的第五连接部件,
上述第五连接部件的另一端接合于上述第一接合部。
10.根据权利要求9所述的半导体装置,其特征在于,
上述第五连接部件的上述另一端在上述第一方向上接合于上述第二连接部件的上述另一端与上述第三连接部件的上述另一端之间。
11.根据权利要求7~10任一项所述的半导体装置,其特征在于,
还具备一端接合于上述控制元件的第六连接部件,
上述第一门电极具有在上述第二方向上互相分离的两个第一衬垫部,
上述第六连接部件的另一端接合于上述两个第一衬垫部的一方。
12.根据权利要求11所述的半导体装置,其特征在于,
上述两个第一衬垫部在上述第一半导体元件中是同电位。
13.根据权利要求11所述的半导体装置,其特征在于,
还具备一端接合于上述两个第一衬垫部的另一方的第七连接部件,
上述多个引线还包括接合了上述第七连接部件的另一端的第五引线。
14.根据权利要求13所述的半导体装置,其特征在于,
在上述厚度方向上观察时,上述两个第一衬垫部的上述一方配置于上述第一主面中上述第二方向的靠近上述第三引线的端缘侧,
在上述厚度方向上观察时,上述两个第一衬垫部的上述另一方配置于上述第一主面中上述第二方向的远离上述第三引线的端缘侧。
15.根据权利要求14所述的半导体装置,其特征在于,
上述第五引线在上述第二方向上配置于上述第四引线的旁边。
16.根据权利要求13~15任一项所述的半导体装置,其特征在于,
还具备一端接合于上述控制元件的第八连接部件,
上述第二门电极具有在上述第二方向上互相分离的两个第二衬垫部,
上述第八连接部件的另一端接合于上述两个第二衬垫部的一方。
17.根据权利要求16所述的半导体装置,其特征在于,
上述两个第二衬垫部在上述第二半导体元件中是同电位。
18.根据权利要求16所述的半导体装置,其特征在于,
还具备一端接合于上述两个第二衬垫部的另一方的第九连接部件,
上述多个引线还包括接合了上述第九连接部件的另一端的第六引线。
19.根据权利要求18所述的半导体装置,其特征在于,
在上述厚度方向上观察时,上述两个第二衬垫部的上述一方配置于上述第二主面中上述第二方向的靠近上述第三引线的端缘侧,
在上述厚度方向上观察时,上述两个第二衬垫部的上述另一方配置于上述第二主面中上述第二方向的远离上述第三引线的端缘侧。
20.根据权利要求19所述的半导体装置,其特征在于,
上述第六引线在上述第二方向上配置于上述第二接合部的旁边。
21.根据权利要求20所述的半导体装置,其特征在于,
在上述第一方向上观察时,上述第五引线和上述第六引线重合。
22.根据权利要求17~21任一项所述的半导体装置,其特征在于,
还具备各自的一端接合于上述控制元件的多个第十连接部件,
上述多个引线还包括接合了上述多个第十连接部件的各自的另一端的多个第七引线,
在上述第一方向上观察时,上述多个第七引线全部与上述第三引线重合。
23.根据权利要求22所述的半导体装置,其特征在于,
在上述多个第七引线上,具有在上述第二方向上观察时与上述第四引线重合的部位和在上述第二方向上观察时与上述第二接合部重合的部位。
24.根据权利要求1~10任一项所述的半导体装置,其特征在于,
上述第一半导体元件以及上述第二半导体元件的各构成材料是氮化镓。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103000592A (zh) * 2011-08-29 2013-03-27 富晶电子股份有限公司 封装结构
CN104347579A (zh) * 2013-07-31 2015-02-11 瑞萨电子株式会社 半导体装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3737673B2 (ja) * 2000-05-23 2006-01-18 株式会社ルネサステクノロジ 半導体装置
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JP5291864B2 (ja) * 2006-02-21 2013-09-18 ルネサスエレクトロニクス株式会社 Dc/dcコンバータ用半導体装置の製造方法およびdc/dcコンバータ用半導体装置
JP2009231805A (ja) 2008-02-29 2009-10-08 Renesas Technology Corp 半導体装置
JP5783997B2 (ja) 2012-12-28 2015-09-24 三菱電機株式会社 電力用半導体装置
JP5925364B2 (ja) * 2015-05-11 2016-05-25 三菱電機株式会社 電力用半導体装置
JP6657963B2 (ja) * 2016-01-05 2020-03-04 富士電機株式会社 Mosfet
JP6832094B2 (ja) * 2016-08-05 2021-02-24 ローム株式会社 パワーモジュール及びモータ駆動回路
US10177080B2 (en) * 2016-10-16 2019-01-08 Alpha And Omega Semiconductor (Cayman) Ltd. Molded intelligent power module
JP7032910B2 (ja) * 2017-01-05 2022-03-09 ローム株式会社 整流ic及びこれを用いた絶縁型スイッチング電源
JP7312604B2 (ja) * 2019-05-13 2023-07-21 ローム株式会社 半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103000592A (zh) * 2011-08-29 2013-03-27 富晶电子股份有限公司 封装结构
CN104347579A (zh) * 2013-07-31 2015-02-11 瑞萨电子株式会社 半导体装置

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