CN204216038U - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN204216038U
CN204216038U CN201420551883.0U CN201420551883U CN204216038U CN 204216038 U CN204216038 U CN 204216038U CN 201420551883 U CN201420551883 U CN 201420551883U CN 204216038 U CN204216038 U CN 204216038U
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China
Prior art keywords
interconnection
transistor
unit
engagement member
conductor pattern
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Expired - Fee Related
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CN201420551883.0U
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English (en)
Inventor
三浦喜直
中村卓
团野忠敏
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Renesas Electronics Corp
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Renesas Electronics Corp
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Abstract

本实用新型涉及一种半导体器件。源极互连和漏极互连被交替地设置在多个晶体管单元之间。一条接合线在多个点处被连接到源极互连。另一接合线在多个点处被连接到源极互连。另外，一条接合线在多个点处被连接到漏极互连。另外，另一接合线在多个点处被连接到漏极互连。

Description

半导体器件
本申请基于日本专利申请No.2013-196874，其内容通过引用被合并在此。
技术领域
本实用新型涉及一种半导体器件，并且，例如，涉及一种可适用于具有晶体管和互连的半导体器件的技术。
背景技术
当半导体芯片被使用时，要求通过接合线等等将半导体芯片连接到诸如引线端子的外部端子。
与使用接合线的半导体器件有关的技术包括，例如，在日本未经审查的专利公开No.2000-133730中公开的技术。在日本未经审查的专利公开No.2000-133730中，双极晶体管和单极晶体管被形成在半导体芯片中。相同的导线在多个点处被连接到与双极晶体管的发射极电极连接的互连。另外，相同的导线在多个点处被连接到与单极晶体管的漏电极连接的互连。日本未经审查的专利公开No.2000-133730公开了，随着导线的连接点的数目增加，晶体管的响应的延迟时间被缩短。
另一方面，最近已经开发了使用化合物半导体层作为沟道的晶体管。这样的晶体管具有导通电阻低的特征。
同时，日本未经审查的专利公开No.2009-206140和日本未经审查的专利公开No.2011-210771公开了：在具有绝缘栅双极晶体管(IGBT)的半导体器件中，导线在多个点处被连接到IGBT的表面电极。
在具有晶体管的半导体器件中，要求降低导通电阻。这样的导通电阻包括由晶体管引起的分量和由互连引起的分量。发明人已经研究降低由互连引起的电阻分量。根据本说明书的描述和附图其它问题和新颖的特征将会变得更加清楚。
实用新型内容
在一个实施例中，半导体器件包括第一晶体管单元、第二晶体管单元、以及第三晶体管单元。这些晶体管单元被依次并排地布置在第一方向上，并且都包括栅电极在第一方向上延伸的多个晶体管。第一互连在第一晶体管单元和第二晶体管单元之间延伸，第二互连在第一晶体管单元介于中间的情况下在第一互连的相反侧延伸，第三互连在第二晶体管单元和第三晶体管单元之间延伸，并且第四互连在第三晶体管单元介于中间的情况下在第三互连的相反侧延伸。第一互连被连接到第一晶体管单元的多个晶体管的源电极和第二晶体管单元的多个晶体管的源电极。第二互连被连接到第一晶体管单元的多个晶体管的漏电极。第三互连被连接到第二晶体管单元的多个晶体管的漏电极和第三晶体管单元的多个晶体管的漏电极。第四互连在第二方向上延伸，并且被连接到第三晶体管单元的多个晶体管的源电极。半导体器件包括第一接合构件、第二接合构件、第三接合构件、以及第四接合构件。第一接合构件在多个点处被连接到第一互连，第二接合构件在多个点处被连接到第二互连，第三接合构件在多个点处被连接到第三互连，并且第四接合构件在多个点处被连接到第四互连。
根据实施例，在具有晶体管的半导体器件中，能够减小由互连引起的电阻分量。
附图说明
结合附图，从某些优选实施例的下面的描述中，本实用新型的以上和其它目的、优点以及特征将会更加显而易见，其中：
图1是图示根据第一实施例的半导体器件的配置的平面图。
图2是沿着图1的线A-A’截取的横截面图。
图3是图示接合线被连接到漏极互连所在的点的图。
图4是图示晶体管单元的配置的平面图。
图5是图示图4的横截面B-B’的第一示例的图。
图6是图示图4的横截面B-B’的第二示例的图。
图7是图示图4的横截面B-B’的第三示例的图。
图8是图示图4的横截面B-B’的第四示例的图。
图9是图示图4的横截面B-B’的第五示例的图。
图10是沿着图4的线C-C’的横截面图。
图11是图示根据第二实施例的半导体器件的配置的平面图。
图12是图示根据第三实施例的半导体器件的配置的平面图。
图13是图示图12的修改示例的图。
图14是图示根据第四实施例的半导体器件的配置的平面图。
图15是沿着图14中示出的半导体器件的线D-D’截取的横截面图。
图16是图示根据第五实施例的半导体器件的配置的图。
图17是图示根据第六实施例的电子设备的配置的图。
图18是图示图17的修改示例的图。
具体实施方式
在此现在参考说明性实施例描述本实用新型。本领域的技术人员将会认识到，为了解释性目的，使用本实用新型的教导能够完成许多替代性实施例并且本实用新型不限于实施例。
在下文中，将会参考附图描述本实用新型的实施例。在所有的附图中，通过相同的附图标记参考相同的元件并且其描述将不会被重复。
(第一实施例)
图1是图示根据第一实施例的半导体器件SD的配置的平面图。图2是沿着图1的线A-A’截取的横截面图。在附图中示出的半导体器件SD包括多个晶体管单元TRU(第一晶体管单元(TRU1)、第二晶体管单元(TRU2)、以及第三晶体管单元(TRU3))、多个漏极互连DRI(第二互连和第三互连)、以及多个源极互连SOI(第一互连和第四互连)。
多个晶体管单元TRU被并排地布置在第一方向(附图中的Y方向)中，并且包括多个晶体管TR(稍后描述)。晶体管TR例如是用于功率控制的晶体管，并且栅电极GE(稍后参考图4描述)在第一方向上延伸。全部多个晶体管单元TRU使用衬底SUB形成。
漏极互连DRI和源极互连SOI被交替地定位在晶体管单元TRU之间，并且在与第一方向相交的方向(第二方向：附图中的X方向)，例如，垂直于第一方向的方向上延伸。换言之，漏极互连DRI被交替地形成在晶体管单元TRU之间，并且源极互连SOI被形成在其中没有将漏极互连DRI布置在晶体管单元TRU之间的部分中。换言之，第一源极互连SOI1(第一互连)在第一晶体管单元TRU1和第二晶体管单元TRU2之间延伸，并且第二漏极互连DRI2(第三互连)在第二晶体管单元TRU2和第三晶体管单元TRU3之间延伸。第一漏极互连DRI1(第二互连)在第一晶体管单元TRU1介于中间的情况下在第一源极互连SOI1的相反侧延伸，并且第二源极互连SOI2(第四互连)在第三晶体管单元TRU3介于中间的情况下在第二漏极互连DRI2的相反侧延伸。
被包括在第一晶体管单元TRU1中的晶体管TR的源电极SOE和被包括在第二晶体管单元TRU2中的晶体管TR的源电极SOE被连接到第一源极互连SOI1。被包括在第一晶体管单元TRU1中的晶体管TR的漏电极DRE被连接到第一漏极互连DRI1。被包括在第二晶体管单元TRU2中的晶体管TR的漏电极DRE和被包括在第三晶体管单元TRU3中的晶体管TR的漏电极DRE被连接到第二漏极互连DRI2。被包括在第三晶体管单元TRU3中的晶体管TR的源电极SOE被连接到第二源极互连SOI2。
同时，在附图中示出的示例中，半导体器件SD仅包括三个晶体管单元TRU，但是可以包括更多的晶体管单元TRU。在这样的情况下，被包括在紧挨着第一晶体管单元TRU1定位的晶体管单元TRU(未示出)中的晶体管TR的漏电极进一步被连接到第一漏极互连DRI1。另外，被包括在紧挨着第三晶体管单元TRU3定位的晶体管单元TRU(未示出)中的晶体管TR的源电极进一步被连接到第二源极互连SOI2。
半导体器件SD进一步包括多条接合线WIR1和多条接合线WIR2。接合线WIR1的一端被连接到源极互连SOI，并且接合线WIR2的一端被连接到漏极互连DRI。
具体地，一条接合线WIR1(第一接合线WIR11)在多个点处被连接到源极互连SOI1(第一互连)。另一接合线WIR1(第四接合线WIR12)在多个点处被连接到源极互连SOI2(第四互连)。另外，一条接合线WIR2(第二接合线WIR21)在多个点处被连接到漏极互连DRI1(第二接合线WIR21)。另外，另一接合线WIR2(第三接合线WIR22)在多个点处被连接到漏极互连DRI2(第三互连)。
同时，接合线WIR1的另一端和接合线WIR2的另一端两者被连接到外部端子(例如，引线框架的引线端子)。
在附图中示出的示例中，衬底SUB是矩形的。当在平面图中看到时，接合线WIR1中的每一条从衬底SUB的边SID1(本实施例中的第一边)延伸到衬底SUB的外部，并且接合线WIR2中的每一条从在与衬底SUB的边SID1的相反侧的边SID2(本实施例中的第三边)延伸到衬底SUB的外部。因此，能够减少在接合线WIR1和接合线WIR2之间发生电介质击穿的风险。同时，边SID1和SID2两者是在衬底SUB的四个边中的与源极互连SOI和漏极互连DRI延伸的方向相交的边。
图3是在接合线WIR2被连接到漏极互连DRI的点的图。如上所述，接合线WIR2在多个点处被连接到漏极互连DRI。当连接点的数目被设定为n，并且漏极互连DRI的长度被设定为L时，在连接点之间的间隔变成等于L/n。另外，在最接近漏极互连DRI的端部的连接点与漏极互连DRI的端部之间的间隔是L/(2n)。在附图中示出的示例中，建立n＝3的关系，并且在连接点之间的间隔是L/3。在最接近漏极互连DRI的端部的连接点和漏极互连DRI的端部之间的间隔是L/6。以这样的方式，能够抑制在漏极互连DRI的特定部分上的电流的集中。
同时，在接合线WIR1被连接到源极互连SOI的点也与在图3中示出的示例相似。
图4是图示晶体管单元TRU的配置的平面图。使用衬底SUB形成半导体器件SD。在衬底SUB中形成元件隔离区域EI。元件隔离区域EI将其中形成有多个晶体管TR的区域(在下文中，被表示为元件形成区域)与其它区域隔离。元件隔离区域EI是其中通过将高浓度B引入到例如阻挡层BAR(稍后参考图5描述)和沟道层CNL(稍后参考图5描述)而使电阻增加的区域。元件隔离区域EI的下端位于缓冲层BUF的表面层处。
元件形成区域被设置在晶体管单元TUR中的每一个中。多个晶体管TR被形成在元件形成区域中。多个晶体管TR被排列在第二方向(X方向)中。多个晶体管TR具有栅电极GE。多个栅电极GE在第一方向(Y方向)中彼此平行地延伸。具体地，元件形成区域是矩形的。栅电极GE平行地延伸到元件形成区域的短边。栅电极GE由例如包含Au或者Al的金属形成。
栅电极GE的两个端部位于元件隔离区域EI上。在栅极互连GEI介于中间的情况下，栅电极GE的一端被连接到栅极板GEP。栅极互连GEI被形成在元件隔离区域EI上方，并且在第二方向(X方向)中延伸。即，栅电极GE具有梳齿状。
源电极SOE和漏电极DRE被交替地设置在栅电极GE之间。换言之，沿着第二方向(X方向)，源电极SOE、栅电极GE、漏电极DRE、以及栅电极GE依次被重复地布置在元件形成区域中。在源极互连SOI介于中间的情况下，多个源电极SOE被彼此平行地连接，并且在漏极互连DRI介于中间的情况下，多个漏电极DRE被彼此连接。
源极互连SOI与源电极SOE一体化地形成，并且从而可以是源电极SOE的一部分。类似地，漏极互连DRI与漏电极DRE一体化地形成，并且从而可以是漏电极DRE的一部分。即，在本实施例中，源电极SOE和漏电极DRE两者具有梳齿状。同时，源电极SOE和漏电极DRE例如是Al。
同时，被包括在彼此相邻的晶体管单元TRU中的源极互连SOI被交替地布置在源极互连SOI延伸的方向(附图中的X方向)中，被包括在彼此相邻的晶体管单元TRU中的漏极互连DRI也被交替地布置。
图5是图示图4的横截面B-B’的第一示例的图。衬底SUB具有其中缓冲层BUF、沟道层CNL、以及阻挡层BAR依次被外延地生长在衬底SUB2上的配置。衬底SUB2例如是p+型体材料的硅衬底。缓冲层BUF是在沟道层CNL和衬底SUB2之间的缓冲。缓冲层BUF是其中重复地层叠例如AlN/GaN的化合物半导体层的氮化物半导体层。沟道层CNL是被外延地生长在缓冲层BUF上的层。沟道层CNL例如是GaN，但是可以是诸如AlGaN的其它氮化物半导体层。阻挡层BAR是由具有不同于沟道层CNL的晶格常数的晶格常数的材料形成。阻挡层BAR例如是AlGaN。形成阻挡层BAR，从而在沟道层CNL中产生用作载流子的二维电子气。
漏电极DRE和源电极SOE被形成在阻挡层BAR上。此外，绝缘膜INS2和栅电极GE被形成在位于漏电极DRE和源电极SOE之间的阻挡层BAR的区域上。在附图中示出的示例中，绝缘膜INS2也用作栅极绝缘膜。在附图中示出的示例中，绝缘膜INS2例如是不定形状态下的SiO2或者Al2O3。在附图中示出的示例中，从栅电极GE到漏电极DRE之间的距离比从栅电极GE到源电极SOE之间的距离长，以便于在栅极和漏极之间提供耐受电压。
图6是图示图4的横截面B-B’的第二示例的图。在附图中示出的示例具有与在图3中示出的第一示例中相同的配置，不同之处在于，化合物半导体层GSL而非栅极绝缘膜GINS被形成在栅电极GE和阻挡层BAR之间。化合物半导体层GSL是具有与衬底SUB2相同的导电类型(例如，p型)的氮化物半导体层(例如，AlGaN或者GaN)。同时，在附图中示出的示例中，阻挡层BAR和沟道层CNL是具有与衬底SUB2的导电类型相反的导电类型(例如，n型)的化合物半导体层。
图7是图示图4的横截面B-B’的第三示例的图。在附图中示出的示例中，晶体管TR是金属绝缘体半导体异质结场效应晶体管(MIS-HJ-FET)。具体地，栅电极GE的一部分被掩埋在绝缘膜INS2中，并且在绝缘膜INS1介于中间的情况下被连接到阻挡层BAR。绝缘膜INS2被形成在绝缘膜INS2上和在绝缘膜INS2和栅电极GE之间。在附图中示出的示例中，绝缘膜INS1也用作栅极绝缘膜。在附图中示出的示例中，绝缘膜INS2例如是SiN膜。绝缘膜INS1例如是不定形状态下的SiO2或者Al2O3。在这样的结构中，被形成在沟道层CNL中的二维电子气在位于栅电极GE下方的部分中被中断。为此，在小于阈值的电压被施加到栅电极GE的状态下，电流不流过沟道层CNL。当电压被施加到栅电极GE时，电流流过沟道层CNL。
图8是图示图4的横截面B-B’的第四示例的图。在附图中示出的示例中，晶体管TR是金属绝缘体半导体场效应晶体管(MIS-FET)，并且是常关型晶体管。具体地，栅电极GE的一部分经过绝缘膜INS2和阻挡层BAR，并且到达沟道层CNL。绝缘膜INS1被形成在绝缘膜INS2、阻挡层BAR以及沟道层CNL与栅电极GE之间。绝缘膜INS1和INS2的配置与在图6中示出的第二示例中的相同。绝缘膜INS1也用作栅极绝缘膜。通过栅电极GE隔离被形成在沟道层CNL中的二维电子气。为此，在电压没有被施加到栅电极GE的状态下，电流不流过沟道层CNL。当等于或者大于阈值的电压被施加到栅电极GE时，电流流过沟道层CNL。
图9是图示图4的横截面B-B’的第五示例的图。在附图中示出的示例中，晶体管TR是结场效应晶体管(J-FET)，并且是常关型晶体管。具体地，第一导电类型层SEM被形成在阻挡层BAR和栅电极GE之间。第一导电类型层SEM例如是AlGaN。
图10是沿着图4的线C-C’截取的横截面图。绝缘膜INS2也被形成在元件隔离区域EI上。栅极互连GEI位于绝缘膜INS2上。绝缘中间层INSL1被形成在绝缘膜INS2上并且在栅极互连GE1上。绝缘中间层INSL1是由例如SiN膜形成。绝缘中间层INSL1没有被形成在元件形成区域上。源极互连SOI和漏极互连DRI被形成在绝缘中间层INSL1上。
接下来，将会描述制造半导体器件SD的方法的示例。首先，缓冲层BUF、沟道层CNL、以及阻挡层BAR被依次外延地生长在衬底SUB2上。同时，可以制备其中缓冲层BUF和沟道层CNL被形成在衬底SUB2上的衬底。接下来，元件隔离区域EI被形成在阻挡层BAR和沟道层CNL中。
接下来，使用例如CVD方法，绝缘膜INS2被形成在阻挡层BAR和元件隔离区域EI上。接下来，使用溅射方法，用作栅电极GE、栅极互连GEI、以及栅极板GEP的膜被形成在绝缘膜INS2上。接下来，此膜被选择性地去除。因此，形成栅电极GE、栅极互连GEI、以及栅极板GEP。接下来，使用CVD方法，绝缘中间层INSL1被形成在栅电极GE和绝缘膜INS2上。
接下来，掩膜图案被形成在绝缘中间层INS1上，并且使用掩膜图案作为掩膜蚀刻绝缘中间层INSL1。因此，绝缘中间层INSL1的位于元件形成区域的部分被去除。其后，掩膜图案被去除。
接下来，使用例如溅射方法，用作源电极SOE、源极互连SOI、漏电极DRE、以及漏极互连DRI的金属膜被形成在绝缘中间层INSL1上，以及在位于元件形成区域内的阻挡层BAR上。接下来，选择性地去除此金属膜。因此，形成源电极SOE、源极互连SOI、漏电极DRE、以及漏极互连DRI。
其后，接合线WIR1在多个点处被连接到源极互连SOI，并且接合线WIR2在多个点处被连接到漏极互连DRI。
接下来，将会描述本实用新型的作用。根据本实施例，第一源极互连SOI被连接到被包括在第一晶体管单元TRU1中的源电极SOE和被包括在第二晶体管单元TRU2中的源电极SOE。另外，第一漏极互连DRI被连接到被包括在第二晶体管单元TRU2中的漏电极DRE和被包括在第三晶体管单元TRU3中的漏电极DRE。为此，仅要求漏极互连DRI和源极互连SOI中的任意一个被设置在彼此相邻的晶体管单元TRU之间。因此，与漏极互连DRI和源极互连SOI两者被布置在彼此相邻的晶体管单元TRU之间的情况相比较，互连宽度能够被增加到在彼此相邻的漏极互连DRI和源极互连SOI之间不需要的空间的程度。因此，能够降低由被包括在半导体器件SD中的寄生电阻中的互连引起的电阻分量。
另外，接合线WIR1在多个点处被连接到源极互连SOI，并且接合线WIR2在多个点处被连接到漏极互连DRI。因此，在接合线WIR1和源极互连SOI之间的连接电阻，和在接合线WIR2和漏极互连DRI之间的连接电阻两者被减小。此外，因为每单位长度的接合线WIR1和WIR2的电阻远远低于半导体芯片内的源极互连或者漏极互连的电阻，所以整个互连电阻分量也被减小。
特别地，在本实施例中，晶体管TR的沟道被形成在沟道层CNL中。沟道层CNL是化合物半导体层，并且具有低于硅的电阻的电阻。在这样的情况下，即使当晶体管TR的寄生电阻被减小时，在互连电阻或连接电阻变得较大的状态下使用化合物半导体层的意义被减少。在本实施例中，因为由互连引起的电阻分量能够被减小，所以在晶体管TR的沟道层中使用化合物半导体层的效果增加。
(第二实施例)
图11是图示根据第二实施例的半导体器件SD的配置的平面图。除了下述要点之外，根据本实施例的半导体器件SD具有与根据第一实施例的半导体器件SD的配置相同的配置。
首先，半导体器件SD包括替代接合线WIR1的接合带LB1(第一接合带LB11和第四接合带LB12)，并且包括替代接合线WIR2的接合带LB2(第二接合带LB21和第三接合带LB22)。接合带LB1和LB2两者具有大于接合线WIR1和WIR2的宽度的宽度，并且具有更低的每单位长度电阻。接合带LB1和LB2的宽度例如是大于接合带LB1和LB2的厚度的十倍。
源极互连SOI的连接到接合带LB1的部分的宽度大于源极互连SOI的其它部分的宽度。类似地，漏极互连DRI的连接到接合带LB2的部分的宽度大于漏极互连DRI的其它部分的宽度。同时，在附图中示出的示例中，源极互连SOI和漏极互连DRI的宽度朝着第一晶体管单元TRU1(或者第三晶体管单元TRU3)变得更大，但是宽度在朝着第二晶体管单元TRU2的方向上没有变得更大。为此，第二晶体管单元TRU2的有效区域没有被减小。
在本实施例中，也获得与第一实施例相同的效果。另外，因为使用接合带LB1和LB2替代接合线WIR1和WIR2，所以能够减小漏极互连DRI和源极互连SOI与外部端子之间的电阻。另外，因为各个连接点的面积也增加，所以在漏极互连DRI和接合带LB2之间的连接电阻也减小，并且在源极互连SOI和接合带LB1之间的连接电阻也减小。因此，在晶体管TR的沟道层中使用化合物半导体层的效果进一步增加。
(第三实施例)
图12是图示根据第三实施例的半导体器件SD的配置的平面图。除了下述要点之外，根据本实施例的半导体器件SD具有与根据第一实施例的半导体器件SD的配置相同的配置。
首先，接合线WIR1和接合线WIR2两者在与源极互连SOI和漏极互连DRI相交的方向(例如，与其垂直的方向)中延伸。接合线WIR1中的每一条被连接到所有的源极互连SOI(例如，源极互连SOI1(第一互连)和源极互连SOI2(第四互连))。另外，接合线WIR2中的每一条被连接到所有的漏极互连DRI(例如，漏极互连DRI1(第二互连)和漏极互连DRI2(第三互连)。
当在平面图中看时，接合线WIR1的在没有被连接到源极互连SOI的一侧的端部从不同于边SID1和SID2的边SID3(本实施例中的第一边)，即在平行于源极互连SOI和漏极互连DIR的方向上的边延伸到衬底SUB的外部。另外，接合线WIR2的在没有被连接到漏极互连DRI的一侧的端部从边SID3的相反侧的边SID4(本实施例中的第二边)延伸到衬底SUB的外部。
根据本实施例，多条接合线WIR1被连接到一个源极互连SOI，并且多条接合线WIR2被连接到一个漏极互连DRI。为此，在接合线WIR1和源极互连SOI之间的连接电阻和在接合线WIR2和漏极互连DRI之间的连接电阻两者被减小。因此，获得与在第一实施例中相同的效果。
同时，在本实施例中，如在图13中所示，可以使用接合带LB1和LB2，替代接合线WIR1和WIR2。在这样的情况下，获得与在第二实施例中相同的效果。另外，不要求被源极互连SOI和漏极互连DRI的连接到接合带的部分被扩宽。因此，与第二实施例相比较，能够增加晶体管单元TRU的有效区域。
另外，当在平面图中看时，接合带LB1和接合带LB2在彼此相反的方向上延伸。因此，能够减小在接合带LB1和接合带LB2之间的电介质击穿的发生的风险。
(第四实施例)
图14是图示根据第四实施例的半导体器件SD的配置的平面图，并且图15是沿着图14中示出的半导体器件SD的线D-D’截取的横截面图。图14对应于第一实施例中的图1，并且图15对应于第一实施例中的图10。除了下述要点之外，根据本实施例的半导体器件SD具有与根据第一或者第二实施例的半导体器件SD相同的配置。附图示出与在第一实施例中相同的情况。
首先，半导体器件SD包括多个漏极焊盘电极DRP(第二上层导体图案和第三上层导体图案)、多个漏极接触DRC(第二连接构件和第三连接构件)、多个源极焊盘电极SOP(第一上层导体图案和第四上层导体图案)、以及多个源极接触SOC(第一连接构件和第四连接构件)。
源极焊盘电极SOP和漏极焊盘电极DRP两者被设置在漏极互连DRI和源极互连SOI上方，并且具有比漏极互连DRI和源极互连SOI的宽度大的宽度。源极焊盘电极SOP和漏极焊盘电极DRP在第二方向(附图中的X方向)中延伸。
如在图14中所示，源极焊盘电极SOP的至少一部分与源极互连SOI重叠，并且漏极焊盘电极DRP的至少一部分与漏极互连DRI重叠。多个源极接触SOC位于源极焊盘电极SOP和源极互连SOI彼此重叠的区域中。另外，多个漏极接触DRC位于漏极焊盘电极DRP和漏极互连DRI彼此重叠的区域中。源极接触SOC将源极互连SOI连接到源极焊盘电极SOP，并且漏极接触DRC将漏极互连DRI连接到漏极焊盘电极DRP。设置源极焊盘电极SOP以便于降低源极互连SOI的表观电阻，并且设置漏极焊盘电极DRP以便于降低漏极互连DRI的表观电阻。
如在图15中所示，绝缘中间层INSL2被形成在源极互连SOI、漏极互连DRI、以及绝缘中间层INSL1上。绝缘中间层INSL2例如是氧化硅膜。源极焊盘电极SOP和漏极焊盘电极DRP被形成在绝缘中间层INSL2上，并且源极接触SOC和漏极接触DRC被掩埋在绝缘中间层INSL2中。源极接触SOC可以与源极焊盘电极SOP一体化地形成。类似地，漏极接触DRC可以与漏极焊盘电极DRP一体化地形成。源极焊盘电极SOP和漏极焊盘电极DRP例如是由诸如Al的金属形成。
另外，如在图14中所示，当在平面图中看时，漏极焊盘电极DRP(第一漏极焊盘电极DRP1)的被连接到第一漏极互连DRI1的部分与第一晶体管单元TRU1重叠。另外，源极焊盘电极SOP(第一源极焊盘电极SOP1)的被连接到第一源极互连SOI1的部分与第一晶体管单元TRU1和第二晶体管单元TRU2中的至少一个重叠。另外，第二漏极焊盘电极DRP2的被连接到第二漏极互连DIR2的部分与第二晶体管单元TRU2和第三晶体管单元TRU3中的至少一个重叠。此外，第二源极焊盘电极SOP2的被连接到第二源极互连SOI2的部分与第三晶体管单元TRU3重叠。以这样的方式，即使当半导体器件SD的平面形状没有被增加时，也能够增加漏极焊盘电极DRP和源极焊盘电极SOP的平面形状，并且进一步减小源极电极SOE的表观电阻和漏极电极DRE的表观电阻。
在附图中示出的示例中，第一源极焊盘电极SOP的一部分与第一晶体管单元TRU1重叠，并且第一源极焊盘电极SOP的另一部分与第二晶体管单元TRU2重叠。第一源极焊盘电极SOP1的与第一晶体管单元TRU1重叠的部分的宽度和第一源极焊盘电极SOP1的与第二晶体管单元TRU2重叠的部分的宽度大体上彼此相等。另外，第二漏极焊盘电极DRP2的一部分与第二晶体管单元TRU2重叠，并且第二漏极焊盘电极DRP2的另一部分与至少一个第三晶体管单元TRU3重叠。第二漏极焊盘电极DRP2的与第二晶体管单元TRU2重叠的部分的宽度和第二漏极焊盘电极DRP2的与第三晶体管单元TRU2重叠的部分的宽度大体上彼此相等。
然而，第一源极焊盘电极SOP1的与第一晶体管单元TRU1重叠的部分的宽度和第一源极焊盘电极SOP1的与第二晶体管单元TRU2重叠的部分的宽度可以彼此不同。另外，第二漏极焊盘电极DRP2的与第二晶体管单元TRU2重叠的部分的宽度和第二漏极焊盘电极DRP2的与三晶体管单元TRU3重叠的部分的宽度也可以彼此不同。
另外，第一漏极焊盘电极DRP1可以仅与第二晶体管单元TRU2重叠，并且第二源极焊盘电极SOP2可以仅与第三晶体管单元TRU3重叠。
另外，如在图15中所示，栅极焊盘电极GEP被形成在与源极焊盘电极SOP和漏极焊盘电极DRP相同的层上。栅极焊盘电极GEP2通过被掩埋在绝缘中间层INSL2中的栅极接触GEC被连接到栅极板GEP。
接合带LB1(或者接合线WIR1)被连接到源极焊盘电极SOP，并且接合带LB2(或者接合线WIR2)被连接到漏极焊盘电极DRP。接合带LB1(或者接合线WIR1)到源极焊盘电极SOP的连接的结构与第一或第二实施例中的接合线WIR1到源极互连SOI的连接的结构相同。此外，接合带LB2(或者接合线WIR2)到漏极焊盘电极DRP的连接的结构与第一或第二实施例中的接合线WIR2到漏极互连DRI的连接的结构相同。
在本实施例中，也获得与第一或者第二实施例中相同的效果。另外，因为提供源极焊盘电极SOP和漏极焊盘电极DRP，所以能够降低源电极SOE的表观电阻和漏电极DRE的表观电阻。
(第五实施例)
图16是图示根据第五实施例的半导体器件SD的配置的图。除了下述要点之外，根据本实施例的半导体器件SD具有与根据第三实施例的半导体器件SD的配置相同的配置。
首先，半导体器件SD包括根据第四实施例的漏极焊盘电极DRP和源极焊盘电极SOP。接合带LB1(或者接合线WIR1)被连接到源极焊盘电极SOP，并且接合带LB2(或者接合线WIR2)被连接到漏极焊盘电极DRP。接合带LB1(或者接合线WIR1)到源极焊盘电极SOP的连接的结构与第三实施例中的接合线WIR1到源极互连SOI的连接的结构相同。另外，接合带LB2(或者接合线WIR2)到漏极焊盘电极DPR的连接的结构与第三实施例中的接合线WIR2到漏极互连DRI的结构相同。
在本实施例中，也获得与第四实施例相同的效果。
(第六实施例)
图17是图示根据第六实施例的电子设备ED的配置的图。电子设备ED包括半导体器件SD。如在第一至第六实施例中的任意一个中示出半导体器件SD的配置。
半导体器件SD被安装在保持构件HLD上。保持构件HLD例如是半导体封装的引线框架，并且包括栅极端子GET、源极端子SOT、以及漏极端子DRT。栅极端子GET通过接合线WIR3(或者接合带)被连接到栅极焊盘电极GEP2。源极端子SOT通过接合线WIR1(或者接合带LB1)被连接到源极焊盘电极SOP，并且漏极端子DRT通过接合线WIR2(或者接合带LB2)被连接到漏极焊盘电极DRP。在附图中示出的示例中，基于半导体器件SD，源极端子SOT、漏极端子DRT、以及栅极端子GET位于相同的方向上。同时，半导体器件SD被安装在管芯焊盘DP上。
然而，如在图18中所示，基于半导体器件SD，源极端子SOT和漏极端子DRT可以位于彼此的相反侧。在这样的情况下，优选的是，栅极端子GET位于与具有相对低的电势的源极端子的相同侧。以这样的方式，能够抑制在栅极端子GET和其它端子之间发生电介质击穿。
在本实施例中，也获得与在第一至第五实施例中的任意一个中相同的效果。
如在上面所陈述的，虽然基于其实施例已经具体地描述了由发明人设计的本实用新型，但是本实用新型不限于在上面提及的实施例，并且不言而喻的是，在没有脱离本实用新型的情况下可以进行各种变化和修改。
显然的是，本实用新型不限于上述实施例，并且在没有脱离本实用新型的范围和精神的情况下可以进行修改和变化。

Claims (10)

1.一种半导体器件，包括：
衬底；和
第一晶体管单元、第二晶体管单元、以及第三晶体管单元，所述第一晶体管单元、所述第二晶体管单元、以及所述第三晶体管单元被形成在所述衬底中并且在第一方向上被依次并排地布置，
其中，所述第一晶体管单元、所述第二晶体管单元、以及所述第三晶体管单元都包括多个晶体管，在所述多个晶体管中，栅电极在所述第一方向上延伸，
所述半导体器件进一步包括：
第一互连，所述第一互连在与所述第一方向相交的第二方向上在所述第一晶体管单元和所述第二晶体管单元之间延伸，并且被连接到所述第一晶体管单元的所述多个晶体管的源电极和所述第二晶体管单元的所述多个晶体管的源电极；
第二互连，所述第二互连在所述第一晶体管单元介于所述第二互连和所述第一互连之间的情况下位于所述第一互连的相反侧，在所述第二方向上延伸，并且被连接到所述第一晶体管单元的所述多个晶体管的漏电极；
第三互连，所述第三互连在所述第二方向上在所述第二晶体管单元和所述第三晶体管单元之间延伸，并且被连接到所述第二晶体管单元的所述多个晶体管的漏电极和所述第三晶体管单元的所述多个晶体管的漏电极；
第四互连，所述第四互连在所述第三晶体管单元介于所述第四互连和所述第三互连之间的情况下位于所述第三互连的相反侧，在所述第二方向上延伸，并且被连接到所述第三晶体管单元的所述多个晶体管的源电极；
第一接合构件，所述第一接合构件在多个点处被连接到所述第一互连；
第二接合构件，所述第二接合构件在多个点处被连接到所述第二互连；
第三接合构件，所述第三接合构件在多个点处被连接到所述第三互连；以及
第四接合构件，所述第四接合构件在多个点处被连接到所述第四互连。
2.根据权利要求1所述的半导体器件，其中，所述第一接合构件、所述第二接合构件、所述第三接合构件、以及所述第四接合构件是接合线。
3.根据权利要求1所述的半导体器件，其中，所述衬底是矩形的，并且
其中，当在平面图中看时，
所述第一接合构件和所述第四接合构件从所述衬底的第一边延伸到所述衬底的外部，并且
所述第二接合构件和所述第三接合构件从所述衬底的面对所述第一边的第二边延伸到所述衬底的外部。
4.根据权利要求1所述的半导体器件，其中，当连接点的数目被设定为n并且连接到所述接合构件的互连的长度被设定为L时，
所述第一接合构件、所述第二接合构件、所述第三接合构件、以及所述第四接合构件中的每一个被构造使得在所述连接点之间的间隔是L/n，并且
在最接近所述互连的端部的连接点与所述互连的所述端部之间的间隔是L/(2n)。
5.一种半导体器件，包括：
衬底；和
第一晶体管单元、第二晶体管单元、以及第三晶体管单元，所述第一晶体管单元、所述第二晶体管单元、以及所述第三晶体管单元被形成在所述衬底中并且在第一方向上被依次并排地布置，
其中，所述第一晶体管单元、所述第二晶体管单元、以及所述第三晶体管单元都包括多个晶体管，在所述多个晶体管中，栅电极在所述第一方向上延伸，
所述半导体器件进一步包括：
第一互连，所述第一互连在与所述第一方向相交的第二方向上在所述第一晶体管单元和所述第二晶体管单元之间延伸，并且被连接到所述第一晶体管单元的所述多个晶体管的源电极和所述第二晶体管单元的所述多个晶体管的源电极；
第二互连，所述第二互连在所述第一晶体管单元介于所述第二互连和所述第一互连之间的情况下位于所述第一互连的相反侧，在所述第二方向上延伸，并且被连接到所述第一晶体管单元的所述多个晶体管的漏电极；
第三互连，所述第三互连在所述第二方向上在所述第二晶体管单元和所述第三晶体管单元之间延伸，并且被连接到所述第二晶体管单元的所述多个晶体管的漏电极和所述第三晶体管单元的所述多个晶体管的漏电极；
第四互连，所述第四互连在所述第三晶体管单元介于所述第四互连和所述第三互连之间的情况下位于所述第三互连的相反侧，在所述第二方向上延伸，并且被连接到所述第三晶体管单元的所述多个晶体管的源电极；
第一接合构件，当在平面图中看时，所述第一接合构件在与所述第一互连和所述第四互连相交的方向上延伸，并且被连接到所述第一互连和所述第四互连中的每一个；和
第二接合构件，当在平面图中看时，所述第二接合构件在与所述第二互连和所述第三互连相交的方向上延伸，并且被连接到所述第二互连和所述第三互连中的每一个。
6.根据权利要求5所述的半导体器件，其中，所述第一接合构件和所述第二接合构件是接合带。
7.根据权利要求5所述的半导体器件，进一步包括多个第一接合构件和多个第二接合构件。
8.根据权利要求5所述的半导体器件，其中，所述衬底是矩形的，并且
其中，当在平面图中看时，
所述第一接合构件从所述衬底的第一边延伸到所述衬底的外部，并且
所述第二接合构件从所述衬底的面对所述第一边的第二边延伸到所述衬底的外部。
9.一种半导体器件，包括在第一方向上被依次并排地布置的第一晶体管单元、第二晶体管单元、以及第三晶体管单元，
其中，所述第一晶体管单元、所述第二晶体管单元、以及所述第三晶体管单元都包括多个晶体管，在所述多个晶体管中，栅电极在所述第一方向上延伸，
所述半导体器件进一步包括：
第一互连，所述第一互连在与所述第一方向相交的第二方向上在所述第一晶体管单元和所述第二晶体管单元之间延伸，并且被连接到所述第一晶体管单元的所述多个晶体管的源电极和所述第二晶体管单元的所述多个晶体管的源电极；
第二互连，所述第二互连在所述第一晶体管单元介于所述第二互连和所述第一互连之间的情况下位于所述第一互连的相反侧，在所述第二方向上延伸，并且被连接到所述第一晶体管单元的所述多个晶体管的漏电极；
第三互连，所述第三互连在所述第二方向上在所述第二晶体管单元和所述第三晶体管单元之间延伸，并且被连接到所述第二晶体管单元的所述多个晶体管的漏电极和所述第三晶体管单元的所述多个晶体管的漏电极；
第四互连，所述第四互连在所述第三晶体管单元介于所述第四互连和所述第三互连之间的情况下位于所述第三互连的相反侧，在所述第二方向上延伸，并且被连接到所述第三晶体管单元的所述多个晶体管的源电极；
第一上层导体图案，所述第一上层导体图案被设置在所述第一互连上方，具有比所述第一互连的宽度大的宽度并且在所述第二方向上延伸；
第一连接构件，所述第一连接构件将所述第一互连连接到所述第一上层导体图案；
第二上层导体图案，所述第二上层导体图案被设置在所述第二互连上方，具有比所述第二互连的宽度大的宽度并且在所述第二方向上延伸；
第二连接构件，所述第二连接构件将所述第二互连连接到所述第二上层导体图案；
第三上层导体图案，所述第三上层导体图案被设置在所述第三互连上方，具有比所述第三互连的宽度大的宽度并且在所述第二方向上延伸；
第三连接构件，所述第三连接构件将所述第三互连连接到所述第三上层导体图案；
第四上层导体图案，所述第四上层导体图案被设置在所述第四互连上方，具有比所述第四互连的宽度大的宽度并且在所述第二方向上延伸；
第一接合构件，所述第一接合构件在多个点处被连接到所述第一上层导体图案；
第二接合构件，所述第二接合构件在多个点处被连接到所述第二上层导体图案；
第三接合构件，所述第三接合构件在多个点处被连接到所述第三上层导体图案；以及
第四接合构件，所述第四接合构件在多个点处被连接到所述第四上层导体图案。
10.一种半导体器件，包括在第一方向上被依次并排地布置的第一晶体管单元、第二晶体管单元、以及第三晶体管单元，
其中，所述第一晶体管单元、所述第二晶体管单元、以及所述第三晶体管单元都包括多个晶体管，在所述多个晶体管中，栅电极在所述第一方向上延伸，
所述半导体器件进一步包括：
第一互连，所述第一互连在与所述第一方向相交的第二方向上在所述第一晶体管单元和所述第二晶体管单元之间延伸，并且被连接到所述第一晶体管单元的所述多个晶体管的源电极和所述第二晶体管单元的所述多个晶体管的源电极；
第二互连，所述第二互连在所述第一晶体管单元介于所述第二互连和所述第一互连之间的情况下位于所述第一互连的相反侧，在所述第二方向上延伸，并且被连接到所述第一晶体管单元的所述多个晶体管的漏电极；
第三互连，所述第三互连在所述第二方向上在所述第二晶体管单元和所述第三晶体管单元之间延伸，并且被连接到所述第二晶体管单元的所述多个晶体管的漏电极和所述第三晶体管单元的所述多个晶体管的漏电极；
第四互连，所述第四互连在所述第三晶体管单元介于所述第四互连和所述第三互连之间的情况下位于所述第三互连的相反侧，在所述第二方向上延伸，并且被连接到所述第三晶体管单元的所述多个晶体管的源电极；
第一上层导体图案，所述第一上层导体图案被设置在所述第一互连上方，具有比所述第一互连的宽度大的宽度并且在所述第二方向上延伸；
第一连接构件，所述第一连接构件将所述第一互连连接到所述第一上层导体图案；
第二上层导体图案，所述第二上层导体图案被设置在所述第二互连上方，具有比所述第二互连的宽度大的宽度并且在所述第二方向上延伸；
第二连接构件，所述第二连接构件将所述第二互连连接到所述第二上层导体图案；
第三上层导体图案，所述第三上层导体图案被设置在所述第三互连上方，具有比所述第三互连的宽度大的宽度并且在所述第二方向上延伸；
第三连接构件，所述第三连接构件将所述第三互连连接到所述第三上层导体图案；
第四上层导体图案，所述第四上层导体图案被设置在所述第四互连上方，具有比所述第四互连的宽度大的宽度并且在所述第二方向上延伸；
第一接合构件，当在平面图中看时，所述第一接合构件在与所述第一上层导体图案和所述第四上层导体图案相交的方向上延伸，并且被连接到所述第一上层导体图案和所述第四上层导体图案中的每一个；和
第二接合构件，当在平面图中看时，所述第二接合构件在与所述第二上层导体图案和所述第三上层导体图案相交的方向上延伸，并且被连接到所述第二上层导体图案和所述第三上层导体图案中的每一个。
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JP6211867B2 (ja) 2017-10-11
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CN104465610A (zh) 2015-03-25

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