CN103918354A - 配线基板及其制造方法 - Google Patents

配线基板及其制造方法 Download PDF

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Publication number
CN103918354A
CN103918354A CN201380002511.0A CN201380002511A CN103918354A CN 103918354 A CN103918354 A CN 103918354A CN 201380002511 A CN201380002511 A CN 201380002511A CN 103918354 A CN103918354 A CN 103918354A
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China
Prior art keywords
splicing ear
distribution conductor
wiring substrate
dam
conductor
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Granted
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CN201380002511.0A
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CN103918354B (zh
Inventor
林贵广
永井诚
伊藤达也
森圣二
若园诚
西田智弘
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Niterra Co Ltd
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NGK Spark Plug Co Ltd
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
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    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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Abstract

提供一种配线基板，其中形成于层叠体的最外层的精确和刚性的坝部牢固地保护配线导体，且配线基板与半导体芯片的连接可靠性优异。构成该配线基板（10）的层叠体（31）包括作为最外层的导体层（24）的多个连接端子部（41）和配线导体（62）。配线导体（62）配置在通过用于倒装芯片地安装半导体芯片（51）的多个连接端子部（41）之间的预定位置。层叠体的最外层的树脂绝缘层（23）具有坝部（63）和增强部（64）。坝部（63）覆盖配线导体（62）。增强部（64）形成在配线导体（62）和邻近配线导体（62）的连接端子部（41）之间，且小于坝部（63）的高度（H3）。增强部（64）与坝部（63）的侧面连接。

Description

配线基板及其制造方法
技术领域
本发明涉及一种配线基板及其制造方法，该配线基板具有用于倒装芯片（flip-chip）地安装半导体芯片的多个连接端子部。
背景技术
近年来，用作电脑的微处理器等的半导体集成电路元件（半导体芯片）在速度和其功能上得到了很大的发展，与之相伴地，其端子的数量增加且存在端子之间的节距也变窄的趋势。通常，在半导体芯片的底部配置大量的连接端子，且半导体芯片的各个连接端子连接到形成于配线基板的多个连接端子部，以利用倒装芯片的形式安装半导体芯片。
例如，针对沿着芯片底部的外周配置大量的连接端子的外缘型半导体芯片（peripheral type semiconductor chip），已经提出了用于倒装芯片的连接的配线基板（例如，参照专利文献1）。在这种配线基板中，与半导体芯片的外形对应的矩形形状的芯片安装区域被设定于基板主面上，且多个连接端子部以诸如沿着芯片安装区域的外周的方式布置。多个连接端子部被设置于带状配线导体的一部分。配线导体本身被设置于基板主面的作为最外层的树脂绝缘层的阻焊层覆盖，且几乎整个配线导体处于未露出的状态。另一方面，每个连接端子部的表面通过设置在阻焊层中的开口向外侧露出。然后，每个露出的连接端子部和半导体芯片侧的连接端子被配置成彼此面对，且它们被构造成通过焊料凸块等彼此电连接。
此外，在这种配线基板101中，作为增加端子的数量和缩窄端子之间的节距的一部分，例如在阻焊层102的开口103中，正在尝试将不同的配线导体以通过具有连接端子部104的多个配线导体105之间的方式配置在预定的位置（参见图15）。然而，在配线导体106被配置在具有连接端子部104的配线导体105之间的预定位置的情况下，连接端子部104和配线导体106在距离上变得太近且不再确保相互绝缘的距离。为此，存在在焊料连接时可能发生短路缺陷的可能性。作为针对短路缺陷的措施，必需通过利用一部分阻焊层102（为了方便，将其称为“坝部107”）来覆盖位于开口103中的配线导体106和邻近的连接端子部104，而实现位于开口103中的配线导体106与邻近的连接端子部104的绝缘。
这里，将说明图15所示的配线基板101的制造方法。首先，通过在树脂绝缘层108上形成铜镀层并对其蚀刻来形成配线导体105、106。接着，在树脂绝缘层108上施加随后成为阻焊层102的感光树脂绝缘材料以形成覆盖配线导体105、106的树脂绝缘材料层109（参见图16）。接着，光掩膜110被置在树脂绝缘材料层109上且在此状态下紫外线112通过光掩膜110被照射在树脂绝缘材料层109上。然后，紫外线112接触基本位于光掩膜110的光通道部111正下方的区域，且树脂绝缘材料层109中的区域被选择性地曝光。图16中，虚线示出了曝光部113。之后，曝光的树脂绝缘材料层109被显影（参见图17）且通过热或紫外线被固化，并且在露出于表面的配线导体105上进行诸如镀层等的最外层表面处理。结果，完成了具有精确的坝部107的配线基板101（参见图18）。
现有技术文献
专利文献
专利文献1：日本特开2011-14644号公报
发明内容
发明要解决的问题
然而，在上述相关领域的制造方法中，在曝光部113的宽度被设为窄以形成窄宽度的精确的坝部107且在传统通常条件下进行曝光的情况下，紫外线112可能不会充分地到达树脂绝缘材料层109的深层部分（deep portion）。那么，在这种情况下，如图16所示，在曝光部113的底部倾向于容易产生曝光缺陷区域115（未曝光或未充分曝光区域）。因此，如果在传统通常条件下进行显影，则底部的曝光缺陷区域115将被露出，且该部分将变成底切（undercut）114（参见图17等）。如果存在这种底切114，坝部107的强度变小，这将导致剥离等。除此之外，如果在底切114中露出配线导体106，那么容易发生的是：最外层表面处理可能导致配线导体105和106之间的短路缺陷。此外，如图19所示，如果形成于半导体芯片120侧的连接端子121的焊料凸块122滑入底切144，也容易导致这种短路缺陷。阻焊层102越厚，如上所述的阻焊剂曝光时硬化深度的不充分导致的这些问题越显著。
为了避免阻焊剂曝光时硬化深度不充分的情况，例如，可构想到诸如利用比传统通常条件大的曝光量进行曝光等的应对措施。那么，通过使用该措施，可能不会产生曝光缺陷区域115，使得不会在图案底部形成底切114（参照图20至23）。然而，在这种情况下，由于紫外线112从光掩膜110的光通道部111发生泄露，最终可能会发生“晕影”，且不仅在位于光通道部111正下方的部分处会容易地曝光而且在该部分的周围区域（参见图20中以113A所示的区域）处也会容易地曝光。因此，坝部107A可能形成为具有比最初意图达到的宽度大的宽度，与之相关地，位于介于中间的端子部104的两侧的坝部107A之间的间隔变窄（参见图21和22）。因此，如果在将半导体芯片120安装于配线基板101时发生移位，即使发生少量移位，半导体芯片120侧的连接端子121以及焊料凸块122也将会接触坝部107A（参见图23）。因此，在这种情况下容易发生不良连接（poor connection）。
此外，还可以构想到另一种应对措施，以被设定为比传统通常条件的显影时间短的显影时间进行显影。利用该措施，即使在留有曝光缺陷区域115的情况下，所述的缺陷部分也不会被显影，因此，不会在图案底部形成底切114（参见图24至26）。然而，在这种情况下，树脂绝缘材料层109将部分地附着到最初应当被显影的部分（例如，连接端子部104的上表面等）并且将被硬化。结果，产生残留的阻焊剂123，且当进行诸如镀层等的最外层表面处理时，这产生了容易形成未镀层部分的缺陷（参见图26）。因此，也容易发生不良连接。
因此，即使采用这两种防止底切114用的措施，也难以在配线导体106上稳定地形成精确和刚性的坝部107。
鉴于上述问题做出了本发明，且本发明的目的在于提供一种配线基板，该配线基板的配线导体由形成于层叠体的最外层的精确和刚性的坝部确实地保护，使得实现优异的与半导体芯片的连接可靠性。此外，本发明的另一个目的在于提供一种该配线基板的制造方法，使得能够稳固地制造具有优异的与半导体芯片的连接可靠性的上述配线基板。
用于解决问题的方案
根据用于解决上述问题的手段（手段1），提供一种配线基板，其包括层叠体，在所述层叠体中堆叠一个或多个树脂绝缘层以及一个或多个导体层，其中，所述层叠体的最外层的导体层包括：多个连接端子部，所述多个连接端子部布置于半导体芯片的安装区域，所述多个连接端子部的表面露出而用于倒装芯片地安装所述半导体芯片；和配线导体，所述配线导体配置在所述多个连接端子部之间的预定位置，以及其中所述层叠体的最外层的树脂绝缘层包括：坝部，所述坝部用于覆盖所述配线导体；和增强部，所述增强部形成在所述配线导体和邻近所述配线导体的所述连接端子部之间，所述增强部形成为低于所述坝部的高度，所述增强部与所述坝部的侧面连接。
因此，根据手段1中描述的发明，当精确的坝部形成为层叠体的最外层的树脂绝缘层的一部分时，增强部与坝部的侧面一体化，导致在坝部的底部增强，该坝部的底部是以传统方式容易形成底切的位置。因此，可以获得精确和刚性的坝部，且配置在通过多个连接端子部之间的预定位置的配线导体由坝部牢固地保护，结果，避免了坝部的剥离和配线导体从坝部的露出。此外，由于增强部形成为低于坝部的高度，避免了增强部可能接触半导体芯片侧的连接端子。根据上述，能够通过焊料等确定地连接半导体芯片侧的连接端子和连接端子部，因而配线基板在与半导体芯片的连接可靠性方面变得优异。
手段1的配线基板为具有层叠体的所谓的有机配线基板，在该层叠体中分别堆叠了一层或多层树脂绝缘层和一层或多层导体层。有机配线基板的优势在于与例如陶瓷配线基板等相比，容易获得高密度的配线。
例如，可以利用主要成分为热固性树脂的堆积材料形成树脂绝缘层。作为树脂绝缘层的形成材料的具体示例，存在列举的一些热固性树脂，诸如环氧树脂、酚醛树脂、聚氨酯树脂、硅树脂和聚酰亚胺树脂。另外，也可使用这些树脂、玻璃纤维（玻璃纺布和玻璃无纺布）和诸如聚酰亚胺纤维等的有机纤维的复合材料，或者将诸如环氧树脂等的热固性树脂浸渍于多孔连续的PTFE等的三维网络氟系树脂基材料的树脂-树脂复合材料。
尽管能够使用诸如铜、银、金、铂、镍、钛、铝和铬等的各种类型的导电金属形成导体层，但是优选地以铜为主要成分构成作为有机配线基板中的导体层。可以利用诸如减法、半添加法和全添加法等的公知方法作为形成导体层的方法。更具体地，例如可使用蚀刻铜箔法、无电镀铜或电解镀铜。此外，还能够在利用诸如溅射和CVD等的方法形成薄膜之后通过进行蚀刻形成导电层，或通过印刷导电性糊剂等形成导电层。
只要半导体芯片能够被倒装芯片地安装在配线基板上，任何半导体芯片都是可行的，具体地，半导体芯片可以是大量连接端子沿着芯片底部的外周配置的外周型，或者是大量连接端子配置于芯片底部的整个区域的区域型。此外，作为半导体芯片，其可以是用作电脑的微处理器的IC芯片，或者是诸如DRAM（动态随机存取存储器）和SRAM（静态随机存取存储器）等的IC芯片。
该配线基板具有作为层叠体中的最外层的导体层的一部分的多个连接端子部。多个连接端子部布置于半导体芯片的安装区域以倒装芯片地安装于半导体芯片。多个连接端子部例如形成为配线导体的一部分，且该部分从最外层的树脂绝缘层露出（这就是所谓的“露出的配线导体”）。连接端子部可以位于露出的配线导体的端部，或可以分别位于露出的配线导体的中间。此外，尽管连接端子部可以形成为宽度与露出的配线导体的宽度相等，但是连接端子部的宽度也可形成为比露出的配线导体的宽度大。当采用较宽的连接端子部时，连接端子部例如可以形成为平面视图中的正方形、长方形、椭圆形或圆形。连接端子部的平面视图形状可以根据配线基板的设计计划、半导体芯片的端子形状等适当地选择。此外，当以矩形形状形成连接端子部时，多个连接端子部可以布置成彼此平行。此外，相邻的多个连接端子部之间的节距可以设定为100μm或更小，且优选地为80μm或更小以获得高密度的配置。
层叠体中最外层的树脂绝缘层由例如阻焊材料等的具有感光性的树脂绝缘材料形成。在最外层的树脂绝缘层中的半导体芯片的安装区域中形成一个或多个开口。开口的形状不必需地限制，只要其能露出多个连接端子部的表面即可，然而，将开口形成为矩形带状（缝状）可能更好。
这种配线基板具有作为层叠体中的最外层的导体层的配置在通过多个连接端子部之间的预定位置的配线导体。由于该配线导体不像上述的露出的配线导体那样，主要不向外侧露出，因此为了方便其被称为“未露出的配线导体”。优选地使得未露出的配线导体与多个连接端子部平行地配置，且以恒定的间隔分离以获得高密度的安装。
构成最外层的树脂绝缘层的一部分的坝部全面覆盖未露出的配线导体。相对于最外层的树脂绝缘层的底部的水平高度，坝部的高度被设定为高于未露出的配线导体的高度，且低于或等于除了坝部和增强部之外的最外层的树脂绝缘层的高度。然而，另外要说的是，更优选地将坝部的高度设定为等于除了坝部和增强部之外的最外层的树脂绝缘层的高度。坝部的宽度（上部宽度）被设定为稍微大于未露出的配线导体的宽度（上部宽度），更具体地被设定为大于等于未露出的配线导体的宽度（上部宽度）的1.1倍或小于等于未露出的配线导体的宽度（上部宽度）的2.5倍。如果该值小于1.1倍，则坝部的宽度会太窄，且有可能不再充分地覆盖未露出的配线导体的侧面。另一方面，如果该值超过了2.5倍，有可能使得半导体芯片侧的连接端子和焊料凸块容易接触坝部。
构成最外层的树脂绝缘层的一部分的增强部形成在未露出的配线导体和邻近未露出的配线导体的连接端子部之间，且形成在位于最外层的树脂绝缘层的正下方的树脂绝缘层的表面上，以与坝部的侧面一体化。优选地，在未露出的配线导体和邻近未露出的配线导体的连接端子部之间填充增强部。利用这种构造，增强部沿着与未露出的配线导体和坝部的纵向垂直交叉的方向在一定程度上变长，且增强部和支撑增强部的上述树脂绝缘层的接触区域也变大。因此，坝部被牢固地增强，且使得坝部稳固。
增强部相对于最外层的绝缘层的底部的高度应当形成为比坝部的高度小。更具体地，优选地，增强部的高度小于或等于多个连接端子部的高度，且还优选地，至少多个连接端子部的表面从增强部露出。根据该构造，即使当在未露出的配线导体和连接端子部之间完全填充增强部时，连接端子部的表面也不在低于增强部的上表面的位置，这证实了减少了将半导体芯片侧的连接端子连接到连接端子部的问题。
此外，更优选地，使得增强部的高度小于多个连接端子部的高度，且更优选地，使得多个连接端子部的侧面的上部和多个连接端子部的整个表面从增强部露出。利用这种构造，即使当在未露出的配线导体和连接端子部之间完全填充增强部时，也将是连接端子部的三个面露出的状态，且与诸如焊料等的导电金属材料的接触区域也变大。因此，连接端子部和半导体芯片侧的连接端子更牢固地连接。
尽管坝部和增强部两者由具有感光性的树脂绝缘材料形成，但是优选地这些部分例如由共同的阻焊材料形成且被一体化形成。如此一体化形成的结构能够增大坝部和增强部的一体化部分的强度，且能够更牢固地增强坝部。此外，不像坝部和增强部分别使用不同的阻焊材料形成的结构，根据该构造，容易实现减小制造成本和简化制造工序。
可以在层叠体的表面上露出的多个连接端子部上进行诸如镀层和溅射等的最外层表面处理。例如，在构成多个连接端子部的导电金属为铜或铜合金的情况下，由除了铜或铜合金之外的金属形成的层（镍层、钯层、金层、锡层等）可形成为最外层表面处理。
根据用于解决上述问题的其他手段（手段2），提供一种根据手段1的配线基板的制造方法，其包括：导体层形成步骤，在所述半导体芯片的安装区域形成所述多个连接端子部和所述配线导体；和树脂绝缘层形成步骤，该步骤包括：通过在如下的树脂绝缘材料覆盖所述多个连接端子部和所述配线导体的状态下在所述多个连接端子部和所述配线导体上配置所述树脂绝缘材料并且对所述树脂绝缘材料进行局部曝光和显影来形成最外层的树脂绝缘层，并且一体地形成所述坝部和所述增强部，所述树脂绝缘材料具有感光性并且将变成最外层的树脂绝缘层。
因此，根据手段2描述的发明，在树脂绝缘层形成工序中，通过在配置于多个连接端子部和配线导体的具有感光性的树脂绝缘材料上进行局部曝光和显影形成最外层的树脂绝缘层。这时，与该工序一起，形成覆盖配线导体的坝部，且一体地形成与坝部的侧面一体化的增强部。因此，由于即使当形成了精确的坝部时，增强部也与坝部的侧面一体化，使得坝部的最初容易产生底切的底部被增强了。因此，能够更容易和牢固地获得精确和刚性的坝部。此外，根据本发明，由于不必需采用避免底切的措施，能够避免诸如大量曝光导致产生晕影和短时间显影导致产生残留树脂等有问题的情况，因此降低了发生不良连接的风险。因此，能够相对容易和牢固地制造与半导体芯片的连接可靠性优异的上述配线基板。
附图说明
图1是示出利用本发明实施的有机（organic）配线基板的局部截面图。
图2是示出了其上倒装芯片地安装了半导体芯片的上述配线基板的主要部分放大截面图。
图3是示出了上述配线基板中的坝部和增强部的主要部分放大截面图。
图4是用于示出上述配线基板的制造方法的局部截面图。
图5是用于示出上述配线基板的制造方法的局部截面图。
图6是用于示出上述配线基板的制造方法的局部截面图。
图7是用于示出上述配线基板的制造方法的局部截面图。
图8是用于示出上述配线基板的制造方法的主要部分放大截面图。
图9是用于示出上述配线基板的制造方法的主要部分放大截面图。
图10是用于示出上述配线基板的制造方法的主要部分放大截面图。
图11是用于示出上述配线基板的制造方法的主要部分放大截面图。
图12是用于示出上述配线基板的制造方法的主要部分放大截面图。
图13是示出另一个实施方式的配线基板的主要部分放大截面图。
图14是示出再一个实施方式的配线基板的主要部分放大截面图。
图15是用于示出传统有机配线基板的制造方法的主要部分放大截面图。
图16是用于示出传统有机配线基板的制造方法的主要部分放大截面图。
图17是用于示出传统有机配线基板的制造方法的主要部分放大截面图。
图18是用于示出传统有机配线基板的制造方法的主要部分放大截面图。
图19是用于示出传统有机配线基板的制造方法的主要部分放大截面图。
图20是用于示出传统有机配线基板的制造方法的主要部分放大截面图。
图21是用于示出传统有机配线基板的制造方法的主要部分放大截面图。
图22是用于示出传统有机配线基板的制造方法的主要部分放大截面图。
图23是用于示出传统有机配线基板的制造方法的主要部分放大截面图。
图24是用于示出传统有机配线基板的制造方法的主要部分放大截面图。
图25是用于示出传统有机配线基板的制造方法的主要部分放大截面图。
图26是用于示出传统有机配线基板的制造方法的主要部分放大截面图。
具体实施方式
以下，将基于图1至12详细描述本发明实施成作为配线基板的有机配线基板的一个实施方式。
如图1所示，本实施方式的有机配线基板10是具有外周结构的配线基板，且具有作为半导体芯片安装面的基板主面11以及位于基板主面11的相反侧的基板背面12。该有机配线基板10具有矩形板状的芯基板13、形成在芯基板13的（图1中，上表面）芯主面14的第一堆积层31以及形成在芯基板13的（图1中，下表面）芯背面15的第二堆积层32。
本实施方式的芯基板13由树脂绝缘材料（环氧玻璃材料）形成，例如通过使环氧树脂浸渍到作为增强材料的玻璃布中而获得该树脂绝缘材料。在芯基板13中，以贯穿芯主面14和芯背面15的方式形成多个通孔导体16。通孔导体16的内侧填满了例如环氧树脂等的闭塞体（blocking body）17。此外，在芯基板13的芯主面14和芯背面15上，由铜形成的导体层19以图案方式形成。这些导体层19电连接到通孔导体16。
形成在芯基板13的芯主面14的第一堆积层31是如下的层叠体：该层叠体具有其中堆叠了由热固性树脂（环氧树脂）形成的多个树脂绝缘层21、22和23以及由铜形成的多个导体层24的结构。树脂绝缘层21、22由具有热固性的树脂绝缘材料（例如环氧树脂）形成。在第一堆积层31中，最外层的导体层24包含沿着芯片安装区域54的外周配置的多个连接端子部41以倒装芯片地安装半导体芯片51。在本实施方式中，第一堆积层31中最外层的树脂绝缘层23为阻焊层23，该阻焊层23由具有感光性的树脂绝缘材料形成。在阻焊层23中，多个缝状开口43形成于与芯片安装区域54的四边对应的位置。则如图1至3所示，在阻焊层23的开口43中，以相等的间隔形成多个连接端子部41。在本实施方式中，这些连接端子部41形成为平面视图中的矩形形状，且形成于从阻焊层23的开口43露出的配线导体61（即，露出的配线导体61）的顶端部或中间处。这里，使得连接端子部41的宽度等于露出的配线导体61的宽度。
在本实施方式中，多个连接端子部41设置在树脂绝缘层22的上表面。此外，导通孔33和填充的通路导体34分别形成于树脂绝缘层21、22。每个通路导体34电连接到各个导体层19、24和连接端子部41。
例如，使用具有铜柱结构的连接端子52的半导体芯片作为安装于本实施方式的配线基板10的半导体芯片51。此外，具有镀金凸块结构或金柱结构而非铜柱结构的连接端子52的半导体芯片51可被倒装芯片地安装。
形成在芯基板13的芯背面15的第二堆积层32具有与上述第一堆积层31的结构几乎相同的结构。即，第二堆积层32具有其中堆叠了树脂绝缘层26、27和28以及导体层24的结构。在第二堆积层32中，用于连接到母板（未图示）的多个外部连接端子45形成为最外层的导体层24。此外，导通孔33和通路导体34也形成于树脂绝缘层26、27。每个通路导体34电连接到导体层19、24以及外部连接端子45。此外，第二堆积层32中的最外层的树脂绝缘层28由阻焊剂28构成。用于露出外部连接端子45的开口47设置于阻焊剂28的指定位置。此外，在外部连接端子45中，从开口47露出的下表面被未图示的镀层（例如，镍金镀层）覆盖。能够电连接到未图示的母板的多个焊料凸块49配置在外部连接端子45的下表面的预定位置。然后，有机配线基板10利用焊料凸块49安装到未图示的母板。
接着，将利用图2和图3详细说明设置于芯片安装区域54的多个结构，该芯片安装区域54位于基板主面11侧的第一堆积层31上。
在位于阻焊层23正下方的树脂绝缘层22上，未向外侧露出的其他的多个配线导体62（即，未露出的配线导体62）配置在露出的配线导体旁边的预定位置。通过使得每个未露出的配线导体62通过露出的配线导体61中间的方式，未露出的配线导体62与具有连接端子部41的露出的配线导体61平行地形成。露出的配线导体61的上部的宽度W3（即，连接端子部41的上部的宽度）等于未露出的配线导体62的上部的宽度W1，例如，该宽度W3被设定为大约10μm至30μm（本实施方式中为20μm）。露出的配线导体61和未露出的配线导体62之间的间隔W4例如也被设定为大约10μm至30μm（本实施方式中为20μm）。此外，露出的配线导体61和未露出的配线导体62的相对于树脂绝缘层22的表面（即，阻焊层23的底部）的水平高度（level）的高度H2例如被设定为大约10μm至20μm（本实施方式中，为15μm）。
阻焊层23在开口43中具有坝部（dam portion）63和增强部64。坝部63由具有感光性的树脂绝缘材料形成，且全面覆盖未露出的配线导体62。坝部63相对于树脂绝缘层22的表面的水平高度的高度H3被设定为等于开口43外侧的阻焊层23的高度，且例如被设定为大约20μm至40μm（本实施方式中为30μm）。此外，当未露出的配线导体62的高度H2用作被比较的目标时，坝部63的高度H3被设定为高度H2的1.1至2.5倍，且在本实施方式中被设定为大约2倍。另一方面，坝部63的上部的宽度W2被设定为是未露出的配线导体62的上部的宽度W1的大约1.1至2.5倍（本实施方式中，大约为30μm，即大约1.5倍）。
在树脂绝缘层22的表面上，增强部64形成在未露出的配线导体62和邻近未露出的配线导体62的连接端子部41之间，且完全填充了两者之间的部分。增强部64由类似于坝部63的具有感光性的树脂绝缘材料形成，且与坝部63的两侧面一体化为整体。增强部64相对于树脂绝缘层22的表面的水平高度的高度H1小于露出的配线导体61的高度H2（连接端子部41的高度H2），且在本实施方式中被设定为大约3μm至12μm。因此，多个连接端子部41的侧面的上部和多个连接端子部41的整个表面处于从增强部64露出的状态。此外，多个连接端子部41的侧面的下部处于与增强部64接触的状态。此外，如图3所示，当比较坝部63的上缘区域63a的角部的曲率与坝部63和增强部64之间的连接区域63b的角部的曲率时，前者大于后者。
接着，将基于图4至12说明本实施方式的有机配线基板10的制造方法。
首先，制备铜箔被堆叠在由环氧玻璃形成的基体材料的两个面上的覆铜堆叠板。然后，利用钻孔机进行钻孔，使得以贯穿覆铜堆叠板71的正面和背面的方式在预先指定的位置形成通孔72（参见图4）。然后，通过在覆铜堆叠板71的通孔72的内表面上进行无电镀铜和电解镀铜而在通孔72中形成通孔导体16。
然后，通过将绝缘树脂材料（环氧树脂）埋入通孔导体16的中空部并使绝缘树脂材料硬化来形成闭塞体17。此外，覆铜堆叠板71的铜箔和形成于铜箔的镀铜层例如通过减法形成图案。结果，如图5所示，获得了其中形成导体层19和通孔导体16的芯基板13。
然后，通过进行堆积工序，第一堆积层31形成于芯基板13的芯主面14，第二堆积层32也形成于芯基板13的芯背面15。
详细来说，在芯基板13的芯主面14和芯背面15上，配置由环氧树脂形成的片状树脂绝缘层21、26，且树脂绝缘层21、26被粘结在芯基板13的芯主面14和芯背面15上。然后，例如利用准分子激光器、UV激光器、CO2激光器等激光器进行激光束铣削（milling）在树脂绝缘层21、26的预定位置形成导通孔33（参见图6）。随后，进行利用诸如高锰酸钾溶液等的蚀刻溶液去除每个导通孔33中的残渣的除污工序。此外，作为除污工序，除了利用蚀刻溶液处理之外，可以进行例如通过O2等离子体的等离子体灰化处理。
通过根据传统公知的方法进行无电镀铜和电解镀铜而在每个导通孔33中形成通路导体34。此外，通过利用传统公知的方法（例如半添加法）蚀刻而在树脂绝缘层21、26上以图案方式形成导体层24（参见图7）。
利用与形成上述的树脂绝缘层21、26和导体层24的方法相同的方法还形成了堆叠在树脂绝缘层21、26上的其他树脂绝缘层22、27和导体层24。此外，这里像树脂绝缘层22上的导体层24那样，分别形成未露出的配线导体62和具有多个连接端子部41的露出的配线导体61（参见图8：导体层形成工序）。此外，多个外部连接端子45在树脂绝缘层27上形成为导体层24。
接着，之后变成阻焊层23的感光树脂绝缘材料被施加于树脂绝缘层22，且被硬化以形成全面覆盖露出的配线导体61和未露出的配线导体62的树脂绝缘材料层66（参见图9）。这里，例如选择阻焊材料作为感光树脂绝缘材料，该阻焊材料的主要组分为感光环氧树脂。在这种情况下，阻焊材料可为能够被施加于该层的液体，且可以为能够粘结于该层的膜状物体。当使用膜状阻焊材料时，优选在阻焊材料的厚度方向上将已经粘结的阻焊材料按压以确保表面平坦度之后进行曝光和显影。
接着，具有在玻璃基板的指定位置形成的光通道部82的光掩膜81被置于树脂绝缘材料层66。在这种状态下，在传统通常条件下利用紫外线83通过光掩膜81照射树脂绝缘材料层66，对树脂绝缘材料层66进行局部曝光（参见图10）。通过这种曝光，紫外线83接触位于光掩膜81的光通道部82正下方的区域，且树脂绝缘材料层66中的该区域被选择性地暴露于紫外线。图10中，虚线示出了将成为坝部63等的曝光部84。当在上述条件下进行曝光时，紫外线83有可能未完全到达树脂绝缘材料层66的深层部分，且在曝光部84的图案底部产生曝光缺陷区域85。
之后，设定一个条件，通过该条件在未曝光部中剩余了大约3μm至12μm的厚度的部分，且利用专用的显影溶液对树脂绝缘材料层66显影（参见图11）。该显影形成了作为最外层的树脂绝缘层的阻焊层23，且将构成该阻焊层23的一部分的坝部63和增强部64形成为整体（树脂绝缘层形成工序）。然后，此外，在通过热或紫外线使阻焊层23、坝部63和增强部64固化之后（参见图12），在露出的配线导体61上进行诸如镀镍金等的最外层表面处理。通过经受上述处理，完成了具有精确的坝部63和与坝部63一体化的增强部64的有机配线基板10。
因此，根据本实施方式，可以获得如下效果。
（1）本实施方式的有机配线基板10被构造成具有如上所述的坝部63和增强部64。因此，即使当精确的坝部63形成为阻焊层23的一部分时，增强部64也与坝部63的侧面一体化。为此，其中最初容易产生底切的坝部63的底部可以被增强。因此，可以获得精确和刚性的坝部63，且配置于穿过多个连接端子部41之间的预定位置的未露出的配线导体62被坝部63牢固地保护。结果，可以避免诸如坝部63的剥离以及未露出的配线导体62从坝部63的露出等有问题的情况。此外，由于增强部64形成为比坝部63的高度H3低，因此避免了增强部64可能会接触半导体芯片51侧的连接端子52。根据上述，能够通过焊料凸块53牢固地连接半导体芯片51侧的连接端子52和连接端子部41，由此能够获得与半导体芯片51的连接可靠性优异的有机配线基板10。
（2）在本实施方式的有机配线基板10中，在未露出的配线导体62和邻近该未露出的配线导体62的连接端子部41之间完全填充增强部64。根据该构造，增强部64沿着与未露出的配线导体62和坝部63的纵向垂直交叉的方向（即，图1至图3的水平方向）在一定程度上变长。因此，增强部64和支撑增强部64的树脂绝缘层22之间的接触区域也变大。因此，该构造具有如下优势：坝部63被牢固地增强且使得坝部63稳固。因此，能更有把握地避免诸如坝部63的剥离以及未露出的配线导体62从坝部63的露出等有问题的情况，因此能够进一步改进与半导体芯片51的连接可靠性。
（3）在本实施方式的有机配线基板10中，增强部64的高度H1小于多个连接端子部41的高度H2。因此，多个连接端子部41的侧面的上部和多个连接端子部41的表面从增强部64露出。利用该构造，即使在未露出的配线导体62和连接端子部41之间完全填充增强部64，那么也将是连接端子部41的三个面露出的状态。因此，多个连接端子部41和诸如焊料等的导电金属材料的接触区域变大。因此，连接端子部41和半导体芯片51侧的连接端子52更牢固地连接，因此能够更加改进与半导体芯片51的连接可靠性。
（4）在本实施方式的有机配线基板10中，坝部63和增强部64由共同的阻焊材料形成，且形成为整体。那么，利用以这种方式一体地形成的结构，能够增大坝部63和增强部64的连接部分的强度，因此更牢固地增强了坝部63。此外，不像坝部63和增强部64分别使用不同的阻焊材料形成的结构，根据该构造，容易实现减小制造成本和简化制造工序。
（5）在本实施方式中，通过如上所述的导体层形成工序和树脂绝缘层形成工序制造期望的有机配线基板10。即，在树脂绝缘层形成工序中，当形成阻焊层23时，覆盖未露出的配线导体62的坝部63和接触坝部63的侧面的增强部64被同时一体地形成。因此，由于即使当形成精确的坝部63时，增强部64也能连接坝部63的侧面，所以最初趋于发展底切的坝部63的底部被增强了。因此，能够相对容易和牢固地获得精确和刚性的坝部63。此外，根据本实施方式的制造方法，不必需采取避免底切用的措施。因此，能够避免诸如大量曝光导致产生晕影和短时间显影导致产生残留树脂等有问题的情况，结果降低了发生不良连接的风险。因此，能够相对容易和牢固地制造与半导体芯片51的连接可靠性优异的有机配线基板10。
此外，可以对本发明的实施方式进行如下变型。
在上述实施方式中，尽管增强部64的高度小于连接端子部41的高度，且连接端子部41的侧面的上部和连接端子部41的表面从增强部64露出，但是也优选地采用例如类似于图13示出的其他实施方式的有机配线基板10A的构造。即，该有机配线基板10A被构造成处于增强部64的高度等于连接端子部41的高度且仅连接端子部41的表面从增强部64露出的状态。
在上述实施方式中，尽管增强部64被形成为完全填充在树脂绝缘层22的表面上的未露出的配线导体62和连接端子部41之间，但是也可采用例如类似于图14示出的其他实施方式的有机配线基板10B的增强部64未完全填充的构造。即，在该有机配线基板10B中，增强部64的侧面不邻接连接端子部41的侧面。
在上述实施方式中，尽管坝部63和增强部64由共同的阻焊材料形成，但是两者也可分别使用不同的树脂绝缘材料层66形成。
在上述实施方式中，在将具有感光性的树脂绝缘材料设置于树脂绝缘层22的表面之后，形成阻焊层23，且通过进行局部曝光和显影一体地形成坝部23和增强部64。然而，可以适当地改变最外层的树脂绝缘层23的形成方法。例如，存在热固性的树脂绝缘层23被涂覆于树脂绝缘层22的待热固化的表面、且随后施加机械抛光（mechanical polishing）、直到露出连接端子部41的表面的方法。在这种情况下，代替机械抛光，可以采用诸如喷砂处理等的研磨加工（abrasive machining），且除此之外，可以采用干法蚀刻处理。
尽管上述实施方式的有机配线基板10为具有芯基板13的配线基板，但是不限于此，且本发明可以被应用于不具有芯的无芯配线基板。
尽管上述实施方式中的有机配线基板10的模型为BGA（球栅阵列），但是不仅限于该BGA，例如，本发明可以被应用于诸如PGA（针栅阵列）和LGA（触点阵列）等的配线基板。
附图标记说明
10、10A、10B 配线基板
21、22、23、26、27、28 树脂绝缘层
23    作为最外层的树脂绝缘层的阻焊层
24    导体层
31    作为层叠体的第一堆积层
32    作为层叠体的第二堆积层
41    连接端子部
51    半导体芯片
54    安装区域
61    （露出的）配线导体
62    （未露出）的配线导体
63    坝部
64    增强部
66    树脂绝缘材料
H1    增强部的高度
H2    连接端子部的高度
H3    坝部的高度

Claims (5)

1.一种配线基板，其包括层叠体，在所述层叠体中堆叠一个或多个树脂绝缘层以及一个或多个导体层，
其中，所述层叠体的最外层的导体层包括：
多个连接端子部，所述多个连接端子部布置于半导体芯片的安装区域，所述多个连接端子部的表面露出而用于倒装芯片地安装所述半导体芯片；和
配线导体，所述配线导体配置在所述多个连接端子部之间的预定位置，以及
其中，所述层叠体的最外层的树脂绝缘层包括：
坝部，所述坝部用于覆盖所述配线导体；和
增强部，所述增强部形成在所述配线导体和邻近所述配线导体的所述连接端子部之间，所述增强部形成为低于所述坝部的高度，所述增强部与所述坝部的侧面连接。
2.根据权利要求1所述的配线基板，其特征在于，
在所述配线导体和邻近所述配线导体的所述连接端子部之间填充所述增强部。
3.根据权利要求2所述的配线基板，其特征在于，
所述增强部的高度小于所述多个连接端子部的高度，以及
所述多个连接端子部的侧面的上部和所述多个连接端子部的表面从所述增强部露出。
4.根据权利要求1至3中任一项所述的配线基板，其特征在于，
所述坝部和所述增强部由共同的阻焊材料形成且形成为整体。
5.一种根据权利要求1至4中任一项所述的配线基板的制造方法，其包括：
导体层形成步骤，在所述半导体芯片的安装区域形成所述多个连接端子部和所述配线导体；和
树脂绝缘层形成步骤，该步骤包括：
通过在如下的树脂绝缘材料覆盖所述多个连接端子部和所述配线导体的状态下在所述多个连接端子部和所述配线导体上配置所述树脂绝缘材料并且对所述树脂绝缘材料进行局部曝光和显影来形成最外层的树脂绝缘层，并且一体地形成所述坝部和所述增强部，其中，所述树脂绝缘材料具有感光性并且将变成最外层的树脂绝缘层。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104392940A (zh) * 2014-10-31 2015-03-04 南通富士通微电子股份有限公司 形成倒装芯片半导体封装的方法
CN107591385A (zh) * 2016-07-08 2018-01-16 欣兴电子股份有限公司 封装基板及其制造方法
CN111952269A (zh) * 2019-05-15 2020-11-17 日本特殊陶业株式会社 配线基板及其制造方法

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015213124A (ja) * 2014-05-02 2015-11-26 イビデン株式会社 パッケージ基板
JP5873152B1 (ja) * 2014-09-29 2016-03-01 日本特殊陶業株式会社 配線基板
KR102574411B1 (ko) * 2016-12-16 2023-09-04 삼성전기주식회사 인쇄회로기판 및 그 제조방법
TWI635782B (zh) * 2017-03-21 2018-09-11 欣興電子股份有限公司 線路板堆疊結構及其製作方法
US11127704B2 (en) 2017-11-28 2021-09-21 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with bump structure and method of making semiconductor device
TWI687142B (zh) * 2018-12-28 2020-03-01 南亞電路板股份有限公司 電路板結構及其製造方法
KR20210115188A (ko) 2020-03-12 2021-09-27 엘지이노텍 주식회사 인쇄회로기판 및 이의 제조 방법
KR20210131149A (ko) * 2020-04-23 2021-11-02 엘지이노텍 주식회사 인쇄회로기판 및 이의 제조 방법
KR20220007255A (ko) 2020-07-10 2022-01-18 삼성전자주식회사 반도체 패키지
US11551939B2 (en) * 2020-09-02 2023-01-10 Qualcomm Incorporated Substrate comprising interconnects embedded in a solder resist layer
KR20230015213A (ko) * 2021-07-22 2023-01-31 엘지이노텍 주식회사 회로기판 및 이를 포함하는 패키지 기판
KR20230094663A (ko) * 2021-12-21 2023-06-28 삼성전기주식회사 인쇄회로기판 및 그 제조방법

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009152317A (ja) * 2007-12-19 2009-07-09 Panasonic Corp 半導体装置およびその製造方法
JP2011192692A (ja) * 2010-03-12 2011-09-29 Mitsubishi Paper Mills Ltd ソルダーレジストパターンの形成方法
JP2012074449A (ja) * 2010-09-28 2012-04-12 Toppan Printing Co Ltd 実装基板

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04195043A (ja) * 1990-11-28 1992-07-15 Hitachi Chem Co Ltd 感光性組成物及びこれを用いたソルダレジストの形成された印刷配線板の製造法
US5844468A (en) * 1996-05-13 1998-12-01 Rohm Co. Ltd. Chip network electronic component
JP4179407B2 (ja) * 2000-08-08 2008-11-12 日本特殊陶業株式会社 配線基板
JP2004153141A (ja) * 2002-10-31 2004-05-27 Ngk Spark Plug Co Ltd セラミック配線基板、それを用いた部品実装済み配線基板、及びそれらの製造方法
JP2004153139A (ja) * 2002-10-31 2004-05-27 Ngk Spark Plug Co Ltd セラミック配線基板、それを用いた部品実装済み配線基板、及びそれらの製造方法
JP4352834B2 (ja) 2003-09-24 2009-10-28 セイコーエプソン株式会社 実装構造体、電気光学装置、電子機器、および実装構造体の製造方法
JP4544913B2 (ja) * 2004-03-24 2010-09-15 富士フイルム株式会社 表面グラフト形成方法、導電性膜の形成方法、金属パターン形成方法、多層配線板の形成方法、表面グラフト材料、及び導電性材料
JP2011014644A (ja) 2009-06-30 2011-01-20 Kyocer Slc Technologies Corp 配線基板およびその製造方法
KR101891840B1 (ko) 2010-09-28 2018-08-24 미쓰비시 세이시 가부시키가이샤 솔더 레지스트 패턴의 형성 방법
KR20140027731A (ko) * 2012-08-27 2014-03-07 삼성전기주식회사 솔더 레지스트 형성 방법 및 패키지용 기판

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009152317A (ja) * 2007-12-19 2009-07-09 Panasonic Corp 半導体装置およびその製造方法
JP2011192692A (ja) * 2010-03-12 2011-09-29 Mitsubishi Paper Mills Ltd ソルダーレジストパターンの形成方法
JP2012074449A (ja) * 2010-09-28 2012-04-12 Toppan Printing Co Ltd 実装基板

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104392940A (zh) * 2014-10-31 2015-03-04 南通富士通微电子股份有限公司 形成倒装芯片半导体封装的方法
CN107591385A (zh) * 2016-07-08 2018-01-16 欣兴电子股份有限公司 封装基板及其制造方法
CN111952269A (zh) * 2019-05-15 2020-11-17 日本特殊陶业株式会社 配线基板及其制造方法

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US20150216059A1 (en) 2015-07-30

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