TW201436678A - 配線基板及其製造方法 - Google Patents

配線基板及其製造方法 Download PDF

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Publication number
TW201436678A
TW201436678A TW102139684A TW102139684A TW201436678A TW 201436678 A TW201436678 A TW 201436678A TW 102139684 A TW102139684 A TW 102139684A TW 102139684 A TW102139684 A TW 102139684A TW 201436678 A TW201436678 A TW 201436678A
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Taiwan
Prior art keywords
connection terminal
layer
resin insulating
wiring
conductor
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TW102139684A
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English (en)
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TWI520664B (zh
Inventor
Takahiro Hayashi
Makoto Nagai
Tatsuya Ito
Seiji Mori
Makoto Wakazono
Tomohiro Nishida
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Ngk Spark Plug Co
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Publication of TW201436678A publication Critical patent/TW201436678A/zh
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Publication of TWI520664B publication Critical patent/TWI520664B/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H05K3/3452—Solder masks
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    • H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
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Abstract

[課題]提供一種配線基板，藉由形成於積層體之最表層的微細且牢固之堤部而確實地保護配線導體，且與半導體晶片之連接可靠度優良。[解決手段]構成此配線基板10之積層體31包含複數個連接端子部41及配線導體62作為最表層之導體層24。配線導體62係通過用以覆晶安裝半導體晶片51之複數個連接端子部41之間而配置。積層體之最表層的樹脂絕緣層23具有堤部63及補強部64。堤部63被覆配線導體62。補強部64係於與配線導體62相鄰之連接端子部41之間形成為比堤部63之高度H3低。補強部64係連結於堤部63之側面。

Description

配線基板及其製造方法
本發明係關於具備用以覆晶安裝半導體晶片之複數個連接端子部的配線基板及其製造方法。
作為電腦之微處理器等而使用之半導體積體電路元件(半導體晶片)，近年來越來越高速化及高功能化，伴隨此，半導體積體電路元件具有端子數增加且端子間之間距變窄的傾向。一般而言，於半導體晶片之底面配置有多個連接端子，半導體晶片之各連接端子係以覆晶之形態連接於形成在半導體搭載用之配線基板的複數個連接端子部。
例如，先前提出一種用以覆晶連接沿晶片底面之外周配置多個連接端子的周邊型半導體晶片的配線基板(例如，參照專利文獻1)。此配線基板中，於基板主表面設定有相當於半導體晶片之外形的矩形形狀之晶片搭載區域，並以沿此晶片搭載區域之外周的方式排列複數個連接端子部。複數個連接端子部係設於帶狀之配線導體的一部分上。配線導體本身係由作為最表面層之樹脂絕緣層而設於基板主表面上的抗銲劑層所被覆，其絕大部分成為非露出之狀態。另一方面，各連接端子部之表面係經由設於抗銲劑層之開口部而露出於外部。此外 ，露出之各連接端子部與半導體晶片側的連接端子係對向配置，且以彼此經由銲料凸塊等電性連接的方式形成。
然而，此種配線基板101中，作為多端子化及狹間距化之一環，例如，曾嘗試於抗銲劑層102之開口部103以通過具有連接端子部104之複數個配線導體105間之方式配置其他配線導體106(參照第15圖)。但是，於具有連接端子部104之配線導體105間配置配線導體106的情況下，連接端子部104與配線導體106之距離過於接近，無法確保彼此之絕緣距離。因此，恐有於銲接連接時產生短路不良之虞。作為其對策，需要對位於開口部103之該配線導體106，也以抗銲劑層102之一部分(方便起見記為「堤部107」)進行被覆，以期與相鄰之連接端子部104絕緣。
在此，對第15圖所示之製造配線基板101的步驟進行說明。首先，於樹脂絕緣層108上形成鍍銅層，藉由對此鍍銅層進行蝕刻而形成配線導體105、106。其次，於絕緣樹脂層108上塗布後續作為抗銲劑層102之感光性樹脂絕緣材料，形成被覆配線導體105、106之樹脂絕緣材料層109(參照第16圖)。接著，於樹脂絕緣材料層109上配置光罩110，並於此狀態下經由光罩110照射紫外線112。於是，紫外線112基本上照射至光罩110之光通過部111正下方的區域，並選擇性地對樹脂絕緣材料層109之該區域進行感光。第16圖中，虛線顯示曝光部113。然後，對曝光後之樹脂絕緣材料層109進行顯像(參照第17圖) ，再以熱或紫外線烘烤，對露出於表面之配線導體105進行電鍍等之最表面處理。結果完成具有微細之堤部107的配線基板101(參照第18圖)。
[先前技術文獻] [專利文獻]
[專利文獻1]日本特開2011-14644號公報
然而，上述先前之製造方法中，將待形成狹窄寬度之微細堤部107的曝光部113的寬度設定為較窄，於以先前之一般條件曝光的情況下，會有紫外線112無法充分地抵達至樹脂絕緣材料層109之深部的情形。並且，於此情況下，容易於第16圖所示之曝光部113的底部產生曝光不良部位115(未曝光或曝光不足之部位)。因此，當以先前之一般條件顯像時，會露出底部之曝光不良部位115，進而在此形成基蝕114(參照第17圖等)。若有此種基蝕114，即會成為堤部107之強度降低而引起剝離等的原因。不僅如此，當於基蝕114處露出配線導體106時，恐有因進行最表面處理而於配線導體105、106之間產生短路不良之虞。此外，如第19圖所示，形成於半導體晶片120側之連接端子121上的銲料凸塊122進入基蝕114，也有恐因此原因而產生短路不良之虞。順便一提，像上述那樣之抗銲劑曝光時的硬化深度不足之問題，會隨抗銲劑層102增厚變得越為顯著。
為了避免抗銲劑曝光時之硬化深度不足的情況的發生，例如，可考慮以比先前之一般條件高的曝光量進行曝光的對策。根據此對策，由於不產生曝光不良部位115，因而不會於圖案底部形成基蝕114(參照第20至第23圖)。但是，此情況下，會產生自光罩110之光通過部111漏出紫外線112的「光暈」，不僅僅是光通部111之正下方的區域，連其周圍的區域亦容易被感光(參照第20圖中以113A所示之區域)。因此，會形成比原本要求之寬度更寬的寬度之堤部107A，伴隨此，造成隔著連接端子部104而位於兩側的堤部107A間之間隔變窄(參照第21、第22圖)。因此，於將半導體晶片120搭載於配線基板101上時，若兩者略有位置偏移，即會造成半導體晶片120側之連接端子121或銲料凸塊122接觸到堤部107A(參照第23圖)。因此，於此情況下容易產生連接不良。
此外，作為其他之對策，還可考慮比先前之一般條件縮短顯像時間進行顯像。根據此對策，即使殘留有曝光不良部位115，該部位亦不會被顯像，所以不會於圖案底部形成基蝕114(參照第24至第26圖)。但是，此情況下，會有樹脂絕緣材料層109在局部黏著於原本應被顯像之部分(例如，連接端子部104的上面等)的狀態下即被硬化的情形。結果產生抗銲劑殘留123，進而產生於進行電鍍等之最表面處理的情況下容易形成無電鍍部分之不良(參照第26圖)。因此，於此情況下也容易產生連接不良。
藉此，即使採取用以防止基蝕114之上述這二 個對策，要於配線導體106上穩定地形成微細且牢固之堤部107仍有困難。
本發明係鑒於上述課題而完成者，其目的在於提供一種配線基板，藉由形成於積層體之最表層的微細且牢固之堤部而確實地保護配線導體，且與半導體晶片之連接可靠度優良。此外，另一目的在於提供一種配線基板之製造方法，可確實地製造與半導體晶片之連接可靠度優良的該配線基板。
作為用以解決上述課題之手段(手段一)，具有一種配線基板，其包含：複數個連接端子部，其具有分別積層有一層以上之樹脂絕緣層及導體層的積層體，且為了覆晶安裝半導體晶片，該積層體之最表層的該導體層係配置於該半導體晶片之搭載區域且露出於表面；及配線導體，其配置於該複數個連接端子部之間；該配線基板之特徵為：該積層體之最表層的該樹脂絕緣層具有被覆該配線導體之堤部、及於該配線導體及與該配線導體相鄰之連接端子部之間形成為比該堤部的高度低且連結於該堤部之側面的補強部。
藉此，根據手段一記載之發明，即使於形成微細堤部作為積層體之最表層的樹脂絕緣層之一部分時，由於在其側面連結有補強部，因此原本容易產生基蝕之堤部的底部得到補強。藉此，可獲得微細且牢固之堤部，可藉由該堤部確實地保護通過複數個連接端子部之間而配置的配線導體，結果可避免堤部之剝離或配線導 體自堤部的露出。此外，由於補強部形成為比堤部之高度低，可避免補強部接觸到半導體晶片側之連接端子。根據以上所述，可經由銲料等確實地連接半導體晶片側之連接端子及連接端子部，進而可獲得與半導體晶片之連接可靠度優良的配線基板。
手段一之配線基板係具有分別積層有一層以上之樹脂絕緣層及導體層的積層體之所謂有機配線基板。有機配線基板之優點在於，例如與陶瓷配線基板等比較，容易達成配線之高密度化。
樹脂絕緣層也可使用例如以熱硬化性樹脂為主體之堆積材料而形成。作為樹脂絕緣層之形成材料的具體例，可列舉環氧樹脂、苯酚樹脂、聚氨酯樹脂、矽樹脂、聚醯亞胺樹脂等之熱硬化性樹脂。除此之外，還可使用這些樹脂與玻璃纖維(玻璃織布或玻璃不織布)或聚醯胺纖維等之有機纖維的複合材料、或者於連續多孔質PTFE等之三維網狀氟系樹脂基材中含浸環氧樹脂等的熱硬化性樹脂而成之樹脂-樹脂複合材料等。
導體層可使用銅、銀、金、白金、鎳、鈦、鋁、鉻等之各種導電金屬形成，但作為有機配線基板之導體層，以將銅作為主體所構成者為較佳。作為形成導體層之方法，可採用消減法、半添加法、全添加法等之周知方法。具體而言，例如，可使用銅箔之蝕刻、無電解鍍銅或電解鍍銅等之方法。又，可於利用濺鍍或CVD等之方法形成薄膜之後進行蝕刻，藉以形成導體層，或者也可藉由導電性糊等之印刷來形成導體層。
半導體晶片只要是能覆晶安裝於配線基板上者即可，具體可為沿晶片底面之外周配置多個連接端子的周邊型、於晶片底面之全域配置多個連接端子的區域型的任一方。此外，作為半導體晶片可列舉作為電腦之微處理器使用的IC晶片、DRAM(Dynamic Random Access Memory)、SRAM(Static Random Access Memory)等之IC晶片。
該配線基板係具有複數個連接端子部作為積層體之最表層的導體層之一部分。為了覆晶安裝半導體晶片，複數個連接端子部係配置於半導體晶片之搭載區域。複數個連接端子部例如係作為自最表層之樹脂絕緣層露出的配線導體(方便起見稱為「露出配線導體」)之一部分而形成。連接端子部可位於露出配線導體之端部，也可位於中段。此外，連接端子部可與露出配線導體形成為等寬，也可形成為比其更寬。於採用更寬寬度之連接端子部的情況下，也能以俯視為例如正方形、長方形、橢圓形、圓形的方式形成。連接端子部之俯視形狀可根據配線基板的設計或半導體晶片之端子形狀等適宜地變更。又，於作成長方形之連接端子部的情況下，也能以彼此平行之方式排列複數個連接端子部。此外，相鄰之複數個連接端子部之間的間距，例如設定為100μm以下，為了達成高密度化，以設定為80μm以下為較佳。
積層體之最表層的樹脂絕緣層係由具有感光性之樹脂絕緣材料所構成，例如，由抗銲劑材料等所形成。於最表層之樹脂絕緣層的半導體晶片之搭載區域形 成有一或二個以上之開口部。只要能使複數個連接端子部之表面露出，開口部之形狀並無特別限制，但以例如矩形帶狀(細縫狀)為較佳。
此配線基板具有通過複數個連接端子部間而配置之配線導體作為積層體的最表層之導體層。此配線導體與上述露出配線導體不同，基本上不露出於外部，所以為方便起見稱為「非露出配線導體」。非露出配線導體係以與複數個連接端子部平行的位置關係且相隔等間隔而配置，這點在達成高密度化方面較佳。
構成最表層之樹脂絕緣層的一部分之堤部，整體被覆於非露出配線導體。於以最表層之樹脂絕緣層的底面的位準為基準時，堤部之高度係設定為比非露出配線導體之高度高、且除堤部及補強部以外之最表層的樹脂絕緣層的高度以下，更甚者也可為與除堤部及補強部以外之最表層的樹脂絕緣層的高度等高。堤部之寬度(上部寬度)係設定為比非露出配線導體的寬度(上部寬度)略寬，具體而言，例如設定為非露出配線導體之寬度(上部寬度)的1.1倍以上2.5倍以下。若此值不滿1.1倍，則堤部之寬度變得太窄，恐有非露出配線導體之側面未被充分被覆之虞。若此值超過2.5倍，恐有半導體晶片側之連接端子或銲料凸塊容易接觸到堤部之虞。
構成最表層之樹脂絕緣層的一部分之補強部，係於位在最表層之樹脂絕緣層的正下方之樹脂絕緣層的表面上形成於非露出配線導體及與此非露出配線導體相鄰的連接端子部之間，且連結於堤部之側面。補強部 係以埋設於非露出配線導體及與此非露出配線導體相鄰的連接端子部之間較佳。若為此構成，補強部沿與非露出配線導體及堤部之長度方向正交的方向被增加一定長度，使得補強部與支撐該補強部之該樹脂絕緣層的接觸面積也增大。藉此，堤部確實被補強，進而可使堤部變得穩定。
以最表層之絕緣層的底面為基準時之補強部的高度，應形成為比堤部之高度還低。更為具體而言，補強部之高度可為複數個連接端子部之高度以下，且複數個連接端子部之至少表面自補強部露出。若為此構成，即使補強部完全埋設於非露出配線導體與連接端子部之間，連接端子部之表面仍不會成為比補強部之上面還低的位置，使得在與半導體晶片側之連接端子之連接時不容易產生障礙。
又，以補強部之高度係比複數個連接端子部的高度低為較佳，且以複數個連接端子部之整個表面及側面的上側部分自補強部露出為較佳。若為此構成，即使補強部完全埋設於非露出配線導體與連接端子部之間，仍成為連接端子部之三個面露出之狀態，使得與銲料等之導電金屬材料的接觸面積也增大。藉此，連接端子部與半導體晶片側之連接端子被更確實地連接。
堤部及補強部均由具有感光性之樹脂絕緣材料所構成，例如，以由共同之抗銲劑材料所構成且一體地形成為較佳。若為像這樣一體形成之構造，堤部與補強部之連結部分的強度增大，可更確實地補強堤部。此 外，根據此構造，與使用分別不同之抗銲劑材料形成堤部及補強部的構造不同，容易謀求製造成本降低及製造製程簡略化。
也可對露出於積層體之表面的複數個連接端子部實施電鍍或濺鍍等之最表面處理。例如，於構成複數個連接端子部之導電金屬為銅或銅合金之情況下，作為最表面處理，也可形成由銅或銅合金以外之金屬構成的層(鎳層、鈀層、金層、錫層等)。
作為用以解決上述課題之另一手段(手段二)，具有一種配線基板之製造方法，係手段一記載之配線基板之製造方法，該製造方法之特徵為包含：導體層形成製程，其於該半導體晶片之搭載區域形成該複數個連接端子部及該配線導體；及樹脂絕緣層形成製程，其於被覆該複數個連接端子部及該配線導體之狀態下，於這些連接端子部及配線導體上配置作為最表層之該樹脂絕緣層的具有感光性之樹脂絕緣材料，且藉由對該樹脂絕緣材料進行局部曝光及顯像，形成最表層之該樹脂絕緣層，並一體地形成該堤部及該補強部。
藉此，根據手段二記載之發明，於樹脂絕緣層形成製程中，對配置於複數個連接端子部及配線導體上的具有感光性之樹脂絕緣材料進行局部曝光及顯像，藉以形成最表層之樹脂絕緣層。此時，一併形成被覆配線導體之堤部，並一體地形成連結於該堤部之側面的補強部。因此，即使於形成微細之堤部時，由於堤部之側面連結有補強部，所以原本容易產生基蝕之堤部的底部 得到補強。因此，可較容易且確實地獲得微細且牢固之堤部。此外，根據本發明，不需要採取用以避免基蝕之對策，所以可避免因高曝光量引起之光暈的產生、短時間顯象引起之樹脂殘留的產生之情況，結果可降低產生連接不良之風險。藉此，可較容易且確實地製造與半導體晶片之連接可靠度優良的該配線基板。
10、10A、10B‧‧‧配線基板
21、22、23、26、27、28‧‧‧樹脂絕緣層
23‧‧‧作為最表層之樹脂絕緣層的抗銲劑層
24‧‧‧導體層
31‧‧‧作為積層體之第一增建層
32‧‧‧作為積層體之第二增建層
41‧‧‧連接端子部
51‧‧‧半導體晶片
54‧‧‧搭載區域
61‧‧‧(露出)配線導體
62‧‧‧(非露出)配線導體
63‧‧‧堤部
64‧‧‧補強部
66‧‧‧樹脂絕緣材料
H1‧‧‧補強部之高度
H2‧‧‧連接端子部之高度
H3‧‧‧堤部之高度
第1圖為顯示將本發明具體化之實施形態的有機配線基板之局部剖視圖。
第2圖為顯示覆晶安裝半導體晶片之該配線基板之要部放大剖視圖。
第3圖為顯示該配線基板上之堤部及補強部之要部放大剖視圖。
第4圖為用以說明該配線基板之製造方法之局部剖視圖。
第5圖為用以說明該配線基板之製造方法之局部剖視圖。
第6圖為用以說明該配線基板之製造方法之局部剖視圖。
第7圖為用以說明該配線基板之製造方法之局部剖視圖。
第8圖為用以說明該配線基板之製造方法之要部放大剖視圖。
第9圖為用以說明該配線基板之製造方法之要部放 大剖視圖。
第10圖為用以說明該配線基板之製造方法之要部放大剖視圖。
第11圖為用以說明該配線基板之製造方法之要部放大剖視圖。
第12圖為用以說明該配線基板之製造方法之要部放大剖視圖。
第13圖為顯示另一實施形態之配線基板之要部放大剖視圖。
第14圖為顯示另一實施形態之配線基板之要部放大剖視圖。
第15圖為用以說明先前之有機配線基板的製造方法之要部放大剖視圖。
第16圖為用以說明先前之有機配線基板的製造方法之要部放大剖視圖。
第17圖為用以說明先前之有機配線基板的製造方法之要部放大剖視圖。
第18圖為用以說明先前之有機配線基板的製造方法之要部放大剖視圖。
第19圖為用以說明先前之有機配線基板的製造方法之要部放大剖視圖。
第20圖為用以說明先前之有機配線基板的製造方法之要部放大剖視圖。
第21圖為用以說明先前之有機配線基板的製造方法之要部放大剖視圖。
第22圖為用以說明先前之有機配線基板的製造方法之要部放大剖視圖。
第23圖為用以說明先前之有機配線基板的製造方法之要部放大剖視圖。
第24圖為用以說明先前之有機配線基板的製造方法之要部放大剖視圖。
第25圖為用以說明先前之有機配線基板的製造方法之要部放大剖視圖。
第26圖為用以說明先前之有機配線基板的製造方法之要部放大剖視圖。
[實施發明之形態]
以下，根據第1至第12圖對將本發明具體構成為作為配線基板之有機配線基板的一實施形態詳細地進行說明。
本實施形態之有機配線基板10係具有周邊構造之配線基板，如第1圖所示，其具有作為半導體晶片搭載面之基板主表面11、及位於該主表面之相反側的基板背面12。有機配線基板10具備：矩形板狀之芯基板13、形成於芯基板13之芯主表面14(第1圖中的上面)上之第一增建層31；及形成於芯基板13之芯背面15(第1圖中的下面)上之第二增建層32。
本實施形態之芯基板13係藉由使環氧樹脂含浸於例如作為補強材之玻璃布而成的樹脂絕緣材料(玻璃環氧材料)所構成。於芯基板13上以貫通芯主表面14及 芯背面15的方式形成有複數個通孔導體16。通孔導體16之內部係以例如環氧樹脂等之封閉體17所填埋。此外，於芯基板13之芯主表面14及芯背面15上圖案形成有由銅構成的導體層19。這些導體層19係電性連接於通孔導體16。
形成於芯基板13之芯主表面14上之第一增建層31，係具有積層有由熱硬化性樹脂(環氧樹脂)所構成之複數個樹脂絕緣層21、22、23、及由銅構成之複數個導體層24之構造的積層體。樹脂絕緣層21、22係由具有熱硬化性之樹脂絕緣材料(例如，環氧樹脂)所構成。於第一增建層31中，最表層之導體層24包含為了覆晶安裝半導體晶片51而沿晶片搭載區域54之外周配置的複數個連接端子部41。本實施形態中，第一增建層31之最表層之樹脂絕緣層23係構成由具有感光性之樹脂絕緣材料所構成的抗銲劑層23。於抗銲劑層23上且對應於晶片搭載區域54之四邊的位置形成有複數個細縫狀的開口部43。然後，如第1至第3圖所示，於抗銲劑層23之開口部43內等間隔地形成有複數個連接端子部41。本實施形態中，這些連接端子部41俯視呈長方形，且形成於自抗銲劑層23之開口部43露出的配線導體61(即露出配線導體61)之前端部或中段。在此，連接端子部41之寬度係與露出配線導體61的寬度相等。
本實施形態中，複數個連接端子部41係設於樹脂絕緣層22之上面。此外，於樹脂絕緣層21、22分別形成有導孔33及填充導孔導體34。各導孔導體34係電性 連接於各導體層19、24及連接端子部41。
作為安裝於本實施形態之配線基板10的半導體晶片51，例如使用具有銅柱(Cu-pillar)構造之連接端子52者。又，銅柱構造以外，還可覆晶安裝具有鍍金凸塊構造、金柱構造之連接端子52之半導體晶片51。
形成於芯基板13之芯背面15上的第二增建層32係具有與上述第一增建層31大致相同之構造。也就是說，第二增建層32具有積層有樹脂絕緣層26、27、28及導體層24之構造。於第二增建層32中，形成有用以連接於母基板(省略圖示)之複數個外部連接端子45，作為最表層之導體層24。此外，於樹脂絕緣層26、27也形成有導孔33及導孔導體34。各導孔導體34係電性連接於導體層19、24及外部連接端子45。又，第二增建層32之最表層的樹脂絕緣層28係構成抗銲劑28。於抗銲劑28之規定部位設有用以使外部連接端子45露出之開口部47。此外，於外部連接端子45中，露出於開口部47內之下面係由未圖示之電鍍層(例如，鎳金鍍層)所被覆。於外部連接端子45之下面配置有能電性連接於未圖示的母基板之複數個銲料凸塊49。另外，有機配線基板10係藉由各銲料凸塊49被安裝於未圖示之母基板上。
其次，使用第2及第3圖對設於基板主表面11側之第一增建層31上的晶片搭載區域54之諸構造進行詳述。
於位在抗銲劑層23下方很近部位的樹脂絕緣層22上，除配置有露出配線導體外，還配置有未露出於 外部之其他複數個配線導體62(即非露出配線導體62)。非露出配線導體62係以通過具有連接端子部41之露出配線導體61間的方式與這些導體平行地形成。露出配線導體61上部之寬度W3(即連接端子部41上部之寬度)係與非露出配線導體62上部之寬度W1相等，例如設定為10μm~30μm(本實施形態中為20μm)。露出配線導體61與非露出配線導體62之間隔W4，例如也設定為10μm~30μm(本實施形態中為20μm)。此外，以樹脂絕緣層22之表面(即抗銲劑層23的底面)的位準為基準時之露出配線導體61及非露出配線導體62的高度H2，例如設定為10μm~20μm(本實施形態中為15μm)。
抗銲劑層23係於開口部43內具有堤部63及補強部64。堤部63係由具有感光性之樹脂絕緣材料所構成，且整體被覆於非露出配線導體62。以樹脂絕緣層22之表面的位準為基準時之堤部63的高度H3係與開口部43外之抗銲劑層23的高度相等，例如設定為20μm~40μm(本實施形態中為30μm)。又，於將非露出配線導體62之高度H2作為比較對象的情況下，堤部63之高度H3係設定為該高度H2之1.1倍~2.5倍左右，本實施形態中設定為約2倍。另一方面，堤部63之上部的寬度W2係設定為非露出配線導體62之上部的寬度W1的1.1倍~2.5倍(本實施形態中約為1.5倍即約30μm)。
補強部64係於樹脂絕緣層22之表面上形成於非露出配線導體62及與此非露出配線導體62相鄰之連接端子部41之間，且完全填埋於這些導體之間。補強部64 係與堤部63相同，由具有感光性之樹脂絕緣材料所構成，且一體連結於堤部63之兩側面。以樹脂絕緣層22之表面的位準為基準時之補強部64的高度H1係比露出配線導體61之高度H2(連接端子部41之高度H2)低，於本實施形態中設定為3μm~12μm左右。藉此，複數個連接端子部41之表面整體及側面的上側部分成為自補強部64露出的狀態。又，複數個連接端子部41之側面的下側部分成為與補強部64相接之狀態。此外，如第3圖所示，當對堤部63之上緣部位63a的角部之曲率及堤部63與補強部64之連結部位63b的角部之曲率進行比較時，前者比後者大。
接著，參照第4至第12圖對本實施形態之有機配線基板10的製造方法進行說明。
首先準備貼銅積層板，該貼銅積層板在由玻璃環氧所構成之基材的兩面貼附有銅箔。然後使用鑽孔機進行開孔加工，於既定位置預先形成貫通貼銅積層板71之表背面的貫通孔72(參照第4圖)。然後，對貼銅積層板71之貫通孔72的內面進行無電解鍍銅及電解鍍銅，藉此於貫通孔72內形成通孔導體16。
然後，將絕緣樹脂材料(環氧樹脂)填埋於通孔導體16之空洞部並將其硬化，而形成封閉體17。又，藉由例如消減法對貼銅積層板71之銅箔及形成於此銅箔上的鍍銅層進行圖案加工。結果如第5圖所示，獲得形成有導體層19及通孔導體16之芯基板13。
然後進行增建製程，藉此，於芯基板13之芯主表面14上形成第一增建層31，並於芯基板13之芯背面 15上形成第二增建層32。
詳細而言，於芯基板13之芯主表面14及芯背面15上配置由環氧樹脂構成的薄片狀之樹脂絕緣層21、26，並對樹脂絕緣層21、26進行黏貼。然後，藉由使用例如激光雷射、UV雷射或CO2雷射等實施雷射加工，於樹脂絕緣層21、26之既定位置形成導孔33(參照第6圖)。接著，進行使用過錳酸鉀溶液等之蝕刻液除去各導孔33內的污跡之去污跡製程。又，作為去污跡製程，於使用蝕刻液之處理以外，例如還可藉由O2電漿進行電漿拋光處理。
於去污跡製程之後，藉由根據先前周知之方法進行無電解鍍銅及電解鍍銅，於各導孔33內形成導孔導體34。又，藉由根據先前周知之方法(例如，半添加法)進行蝕刻，於樹脂絕緣層21、26上圖案形成導體層24(參照第7圖)。
有關其他之樹脂絕緣層22、27及導體層24，也藉由與上述樹脂絕緣層21、26及導體層24相同之方法形成，並積層於樹脂絕緣層21、26上。又，在此，作為樹脂絕緣層22上之導體層24，分別形成具有複數個連接端子部41之露出配線導體61、非露出配線導體62(參照第8圖：導體層形成製程)。此外，作為樹脂絕緣層27上之導體層24，分別形成複數個外部連接端子部45。
其次，於樹脂絕緣層22上塗布其後的過程中成為抗銲劑層23之感光性樹脂絕緣材料並予以硬化，形成整個被覆於露出配線導體61及非露出配線導體62的樹 脂絕緣材料層66(參照第9圖)。在此，作為感光性樹脂絕緣材料，例如選擇以感光性環氧樹脂為主體之抗銲劑材料。此情況下，抗銲劑材料可為能塗布之液狀物，也可為能黏貼之薄膜狀物。於使用薄膜狀之抗銲劑材料的情況下，為能確保表面之平坦性，以於厚度方向對黏著後之抗銲劑材料進行加壓之後再進行曝光及顯像為較佳。
接著，於樹脂絕緣材料層66上配置於玻璃基板之既定部位形成有光通過部82的光罩81。於此狀態下，經由光罩81且以先前之一般條件照射紫外線83，藉以對樹脂絕緣材料層66進行局部曝光(參照第10圖)。藉由此曝光，紫外線83照射至光罩81之光通過部82正下方的區域，並選擇性地對樹脂絕緣材料層66中之該區域進行感光。第10圖中，以虛線顯示其後之過程中成為堤部63等之曝光部84。於以上述條件進行曝光之情況下，紫外線83無法充分抵達樹脂絕緣材料層66之深部，可能會於曝光部84之圖案底部產生曝光不良部位85。
然後，對未曝光部分設定剩餘3μm~12μm之厚度量的條件，使用專用之顯像液對樹脂絕緣材料層66進行顯像(參照第11圖)。藉由此顯像形成抗銲劑層23即最表層之樹脂絕緣層，並一體地形成構成此抗銲劑層23之一部分的堤部63及補強部64(樹脂絕緣層形成製程)。然後，再以熱及紫外線對抗銲劑層23、堤部63及補強部64進行烘烤後(參照第12圖)，於露出配線導體61進行鎳金電鍍等之最表面處理。經過以上之製程，完成具有微細之堤部63及連結於此堤部63之補強部64的有機配線基 板10。
藉此，根據本實施形態，可獲得以下之效果。
(1)本實施形態之有機配線基板10，如上述，由具有堤部63及補強部64者所構成。因此，即使於形成微細堤部63作為抗銲劑層23之一部分時，在其側面仍連結有補強部64。因此原本容易產生基蝕的堤部63的底部得到補強。藉此，可獲得微細且牢固之堤部63，可藉由該堤部63確實地保護通過複數個連接端子部41之間而配置的非露出配線導體62。結果可避免堤部63之剝離或非露出配線導體62自堤部63露出的情況。此外，由於補強部64形成為比堤部63之高度H3低，可避免補強部64接觸到半導體晶片51側的連接端子52。根據以上所述，可經由銲料凸塊53確實地連接半導體晶片51側之連接端子52及連接端子部41，可獲得與半導體晶片51之連接可靠度優良的有機配線基板10。
(2)本實施形態之有機配線基板10中，補強部64完全填埋於非露出配線導體62及與此非露出配線導體62相鄰的連接端子部41之間。根據此構成，補強部64沿與非露出配線導體62及堤部63之長度方向正交的方向(即第1至第3圖的左右方向)被增加一定長度。因此，使得補強部64與支撐該補強部64之樹脂絕緣層22的接觸面積也增大。因此，具有堤部63確實被補強，堤部63變得穩定之優點。因此，可更確實地避免堤部63之剝離或非露出配線導體62自堤部63露出的情況，進而可進一步提高 與半導體晶片51之連接可靠度。
(3)本實施形態之有機配線基板10中，補強部64之高度H1係比複數個連接端子部41的高度H2低。結果，複數個連接端子部41之表面及側面的上側部分自補強部64露出。若為此構成，即使補強部64完全埋設於非露出配線導體62與連接端子部41之間，仍成為連接端子部41之3個面露出之狀態。因此，複數個連接端子部41與銲料等之導電金屬材料的接觸面積增大。藉此，可更確實地連接連接端子部41與半導體晶片51側之連接端子52，進而可進一步提高與半導體晶片51之連接可靠度。
(4)本實施形態之有機配線基板10中，堤部63及補強部64係由共同之抗銲劑材料所構成且一體地形成。若為像這樣一體形成之構造，堤部63與補強部64之連結部分的強度增大，可更確實地補強堤部63。此外，根據此構造，與使用分別不同之抗銲劑材料形成堤部63及補強部64的構造不同，容易謀求製造成本降低及製造製程簡略化。
(5)本實施形態中，經過如上述之導體層形成製程及樹脂絕緣層形成製程，製造所需之有機配線基板10。也就是說，於樹脂絕緣層形成製程中，於形成抗銲劑層23時，一併一體地形成被覆非露出配線導體62之堤部63、及連結於該堤部63之側面的補強部64。因此，即使於形成微細之堤部63時，由於其側面連結有補強部64，原本容易產生基蝕之堤部63的底部得到補強。藉此，可較容易且確實地獲得微細且牢固之堤部63。此外，根 據本實施形態之製造方法，不需要採取用以避免基蝕之對策。因此，可避免因高曝光量引起之光暈的產生、短時間顯象引起之樹脂殘留的產生之情況，結果可降低產生連接不良之風險。藉此，可較容易且確實地製造與半導體晶片51之連接可靠度優良的有機配線基板10。
又，本發明之實施形態還可按以下方式變更。
‧上述實施形態中，補強部64之高度比連接端子部41的高度低，且連接端子部41之表面及側面的上側部分自補強部64露出，但是，例如，也可為像第13圖所示之另一實施形態的有機配線基板10A那樣的構成。也就是說，於此有機配線基板10A中，成為補強部64之高度與連接端子部41的高度相等，且僅連接端子部41之表面自補強部64露出的狀態。
‧上述實施形態中，補強部64係於樹脂絕緣層22之表面上完全埋設於非露出配線導體62與連接端子部41之間，但是，例如，也可像第14圖所示之另一實施形態的有機配線基板10B那樣，採用不完全埋設之構成。也就是說，於此有機配線基板10B中，補強部64之側面未接觸於連接端子部41的側面。
‧上述實施形態中，堤部63及補強部64係由共同之抗銲劑材料所形成，但也可使用彼此不同之樹脂絕緣材料層66形成。
‧上述實施形態中，於樹脂絕緣層22之表面設置具有感光性的樹脂絕緣材料之後，藉由進行局部曝 光及顯像，形成抗銲劑層23並一體形成堤部63及補強部64。然而，最表層之樹脂絕緣層23之形成方法可適宜地變更。例如，也可採用於樹脂絕緣層22之表面塗布熱硬化性的樹脂絕緣層23並硬化後，直到使各連接端子部41之表面露出為止進行機械研磨的方法。此情況下，於可取代機械研磨而採用噴砂處理等之磨石加工之外，還可採用乾式蝕刻處理。
‧上述實施形態之有機配線基板10係具有芯基板13之配線基板，但不限於此，還可將本發明應用於不具有芯之無芯配線基板。
‧上述實施形態之有機配線基板10的形態係BGA(球柵陣列)，但不只限於BGA，還可將本發明應用於例如PGA(針柵陣列)或LGA(矩柵陣列)等之配線基板。
10‧‧‧配線基板
22‧‧‧樹脂絕緣層
23‧‧‧作為最表層之樹脂絕緣層的抗銲劑層
41‧‧‧連接端子部
43‧‧‧開口部
51‧‧‧半導體晶片
52‧‧‧連接端子
53‧‧‧銲料凸塊
61‧‧‧(露出)配線導體
62‧‧‧(非露出)配線導體
63‧‧‧堤部
64‧‧‧補強部

Claims (5)

  1. 一種配線基板，其包含：複數個連接端子部，其具有分別積層有一層以上之樹脂絕緣層及導體層的積層體，且為了覆晶安裝半導體晶片，該積層體之最表層的該導體層係配置於該半導體晶片之搭載區域且露出於表面；及配線導體，其配置於該複數個連接端子部之間；該配線基板之特徵為：該積層體之最表層的該樹脂絕緣層具有被覆該配線導體之堤部、及於該配線導體及與該配線導體相鄰之連接端子部之間形成為比該堤部的高度低且連結於該堤部之側面的補強部。
  2. 如申請專利範圍第1項之配線基板，其中該補強部係埋設於該配線導體及與該配線導體相鄰的連接端子部之間。
  3. 如申請專利範圍第2項之配線基板，其中該補強部之高度係比該複數個連接端子部的高度低，且該複數個連接端子部之表面及側面的上側部分自該補強部露出。
  4. 如申請專利範圍第1至3項中任一項之配線基板，其中該堤部及該補強部係由共同之抗銲劑材料所構成且一體地形成。
  5. 一種配線基板之製造方法，係如申請專利範圍第1至4項中任一項之配線基板之製造方法，該製造方法之特徵為包含：導體層形成製程，其於該半導體晶片之搭載區域形成該複數個連接端子部及該配線導體；及 樹脂絕緣層形成製程，其於被覆該複數個連接端子部及該配線導體之狀態下，於這些連接端子部及配線導體上配置作為最表層之該樹脂絕緣層的具有感光性之樹脂絕緣材料，且藉由對該樹脂絕緣材料進行局部曝光及顯像，形成最表層之該樹脂絕緣層，並一體地形成該堤部及該補強部。
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US9420703B2 (en) 2016-08-16
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JP5592459B2 (ja) 2014-09-17
US20150216059A1 (en) 2015-07-30

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