WO2014073128A1 - 配線基板及びその製造方法 - Google Patents

配線基板及びその製造方法 Download PDF

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Publication number
WO2014073128A1
WO2014073128A1 PCT/JP2013/003342 JP2013003342W WO2014073128A1 WO 2014073128 A1 WO2014073128 A1 WO 2014073128A1 JP 2013003342 W JP2013003342 W JP 2013003342W WO 2014073128 A1 WO2014073128 A1 WO 2014073128A1
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WIPO (PCT)
Prior art keywords
connection terminal
layer
dam
conductor
wiring
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PCT/JP2013/003342
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English (en)
French (fr)
Inventor
貴広 林
永井　誠
伊藤　達也
聖二 森
若園　誠
智弘 西田
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日本特殊陶業株式会社
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Application filed by 日本特殊陶業株式会社 filed Critical 日本特殊陶業株式会社
Priority to EP13824470.2A priority Critical patent/EP2784807B1/en
Priority to CN201380002511.0A priority patent/CN103918354B/zh
Priority to US14/237,065 priority patent/US9420703B2/en
Priority to KR1020147002931A priority patent/KR101596173B1/ko
Publication of WO2014073128A1 publication Critical patent/WO2014073128A1/ja

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    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/384—Bump effects
    • H01L2924/3841—Solder bridging
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845—Stepped hole, via, edge, bump or conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09881—Coating only between conductors, i.e. flush with the conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings

Definitions

  • the present invention relates to a wiring board having a plurality of connection terminal portions for flip-chip mounting a semiconductor chip and a method for manufacturing the same.
  • connection terminals are arranged on the bottom surface of a semiconductor chip, and each connection terminal of the semiconductor chip is connected in a flip chip form to a plurality of connection terminal portions formed on a wiring board for mounting a semiconductor.
  • a wiring board for flip-chip connection of a peripheral type semiconductor chip in which a large number of connection terminals are arranged along the outer periphery of the bottom surface of the chip has been proposed (for example, see Patent Document 1).
  • a rectangular chip mounting area corresponding to the outer shape of the semiconductor chip is set on the main surface of the board, and a plurality of connection terminal portions are arranged along the outer periphery of the chip mounting area.
  • the plurality of connection terminal portions are provided on a part of the strip-shaped wiring conductor.
  • the wiring conductor itself is covered with a solder resist layer provided on the main surface of the substrate as the outermost resin insulation layer, and most of the wiring conductor is not exposed.
  • connection terminal portion is exposed to the outside through an opening provided in the solder resist layer.
  • the exposed connection terminal portions and the connection terminals on the semiconductor chip side are arranged to face each other and are electrically connected to each other via solder bumps or the like.
  • the openings 103 of the solder resist layer 102 are passed between the plurality of wiring conductors 105 having the connection terminal portions 104.
  • the wiring conductor 106 is disposed between the wiring conductors 105 having the connection terminal portion 104, the distance between the connection terminal portion 104 and the wiring conductor 106 becomes too close, and a mutual insulation distance cannot be secured. For this reason, there is a possibility that a short circuit failure may occur during solder connection.
  • the wiring conductor 106 positioned in the opening 103 is also covered with a part of the solder resist layer 102 (referred to as “dam part 107” for convenience) to insulate the adjacent connection terminal part 104 from each other. It is necessary to plan.
  • dam part 107 a part of the solder resist layer 102
  • a procedure for manufacturing the wiring substrate 101 shown in FIG. 15 will be described.
  • a copper plating layer is formed on the resin insulating layer 108 and etched to form the wiring conductors 105 and 106.
  • a photosensitive resin insulating material that will later become the solder resist layer 102 is applied on the resin insulating layer 108 to form a resin insulating material layer 109 that covers the wiring conductors 105 and 106 (see FIG. 16).
  • a photomask 110 is placed over the resin insulating material layer 109, and in this state, ultraviolet rays 112 are irradiated through the photomask 110.
  • the ultraviolet light 112 hits an area directly below the light passage portion 111 of the photomask 110, and the area in the resin insulating material layer 109 is selectively exposed.
  • the exposure unit 113 is indicated by a broken line.
  • the exposed resin insulating material layer 109 is developed (see FIG. 17), further cured with heat or ultraviolet light, and the wiring conductor 105 exposed on the surface is subjected to an outermost surface treatment such as plating.
  • the wiring substrate 101 having the fine dam portion 107 is completed (see FIG. 18).
  • the ultraviolet rays 112 are resin-insulated.
  • the depth of the material layer 109 may not be sufficiently reached.
  • a poorly exposed portion 115 (a portion not exposed or insufficiently exposed) is likely to occur at the bottom of the exposed portion 113 as shown in FIG. Therefore, if development is performed under conventional normal conditions, a poorly exposed portion 115 at the bottom is exposed and becomes an undercut 114 (see FIG. 17 and the like). When such an undercut 114 is present, the strength of the dam portion 107 is reduced, which causes peeling or the like.
  • the solder bump 122 formed on the connection terminal 121 on the semiconductor chip 120 side enters the undercut 114, which may cause a short circuit defect.
  • the problem of insufficient curing depth at the time of solder resist exposure as described above becomes more prominent as the solder resist layer 102 becomes thicker.
  • a dam portion 107A having a width wider than the originally aimed width is formed, and accordingly, the interval between the dam portions 107A located on both sides of the connection terminal portion 104 is narrowed (FIG. 21, (See FIG. 22). For this reason, when the semiconductor chip 120 is mounted on the wiring substrate 101, if the two are slightly displaced, the connection terminals 121 and the solder bumps 122 on the semiconductor chip 120 side hit the dam portion 107A (see FIG. 23). Therefore, in this case, connection failure tends to occur. *
  • the present invention has been made in view of the above problems, and its purpose is to reliably protect the wiring conductor by the fine and strong dam portion formed on the outermost layer of the laminate, and to improve the connection reliability with the semiconductor chip.
  • the object is to provide an excellent wiring board.
  • Another object is to provide a method of manufacturing a wiring board that can reliably manufacture the wiring board having excellent connection reliability with a semiconductor chip.
  • the reinforcing portion is connected to the side surface, so that undercut is inherently not performed. Reinforces the bottom of dams that are likely to occur. Therefore, a fine and strong dam part can be obtained, and as a result of the wiring conductor arranged passing through between the plurality of connection terminal parts being surely protected by the dam part, the dam part can be peeled off or from the dam part. The exposure of the wiring conductor is avoided. Moreover, since the reinforcement part is formed lower than the height of the dam part, it is avoided that the reinforcement part hits the connection terminal on the semiconductor chip side. From the above, the connection terminal on the semiconductor chip side and the connection terminal portion can be reliably connected via solder or the like, and a wiring board excellent in connection reliability with the semiconductor chip can be obtained. *
  • the wiring substrate of means 1 is a so-called organic wiring substrate having a laminate in which one or more resin insulation layers and conductor layers are laminated.
  • the advantage of the organic wiring board is that it is easy to achieve higher wiring density than, for example, a ceramic wiring board.
  • the resin insulating layer may be formed using, for example, a build-up material mainly composed of a thermosetting resin.
  • a build-up material mainly composed of a thermosetting resin.
  • the material for forming the resin insulating layer include thermosetting resins such as epoxy resins, phenol resins, urethane resins, silicone resins, and polyimide resins.
  • thermosetting resins such as epoxy resins, phenol resins, urethane resins, silicone resins, and polyimide resins.
  • composite materials of these resins and organic fibers such as glass fibers (glass woven fabrics and glass nonwoven fabrics) and polyamide fibers, or three-dimensional network fluorine-based resin base materials such as continuous porous PTFE, epoxy resins, etc.
  • a resin-resin composite material impregnated with a thermosetting resin may be used.
  • the conductor layer can be formed using various conductive metals such as copper, silver, gold, platinum, nickel, titanium, aluminum, chromium, etc., but the conductor layer in the organic wiring board is mainly composed of copper. It is preferable.
  • a method for forming the conductor layer a known method such as a subtractive method, a semi-additive method, or a full additive method is employed. Specifically, for example, techniques such as etching of copper foil, electroless copper plating, or electrolytic copper plating are applied.
  • a conductor layer can be formed by etching after forming a thin film by a technique such as sputtering or CVD, or a conductor layer can be formed by printing a conductive paste or the like.
  • the semiconductor chip only needs to be flip-chip mountable on a wiring board. Specifically, a peripheral type in which a large number of connection terminals are arranged along the outer periphery of the chip bottom surface. Any of the arranged area types may be used. Examples of the semiconductor chip include an IC chip used as a computer microprocessor, an IC chip such as a DRAM (Dynamic Random Access Memory) and an SRAM (Static Random Access Memory). *
  • This wiring board has a plurality of connection terminal portions as a part of the outermost conductor layer in the laminate.
  • the plurality of connection terminal portions are arranged in a semiconductor chip mounting region for flip chip mounting of the semiconductor chip.
  • the plurality of connection terminal portions are formed, for example, as part of a wiring conductor exposed from the outermost resin insulation layer (referred to as an “exposed wiring conductor” for convenience).
  • the connection terminal portion may be located at the end of the exposed wiring conductor, or may be located in the middle thereof. Further, the connection terminal portion may be formed to have the same width as the exposed wiring conductor, but may be formed to be wide.
  • connection terminal portion When a wide connection terminal portion is employed, it may be formed to have, for example, a square shape, a rectangular shape, an elliptical shape, or a circular shape in plan view.
  • the planar view shape of the connection terminal portion can be appropriately changed according to the design design of the wiring board, the terminal shape of the semiconductor chip, and the like.
  • position a some connection terminal part when it is set as the rectangular connection terminal part, you may arrange
  • the pitch between a plurality of adjacent connection terminal portions is set to 100 ⁇ m or less, for example, and preferably set to 80 ⁇ m or less in order to achieve high density. *
  • the outermost resin insulating layer in the laminate is made of a resin insulating material having photosensitivity, and is formed of, for example, a solder resist material.
  • One or more openings are formed in the semiconductor chip mounting region in the outermost resin insulation layer.
  • the shape of the opening is not particularly limited as long as the surfaces of the plurality of connection terminal portions can be exposed. For example, a rectangular strip shape (slit shape) is preferable. *
  • This wiring board has a wiring conductor disposed between a plurality of connection terminal portions as the outermost conductive layer in the laminate. Since this wiring conductor is basically not exposed to the outside unlike the above-described exposed wiring conductor, it is referred to as a “non-exposed wiring conductor” for convenience.
  • the non-exposed wiring conductors are preferably arranged in a positional relationship parallel to the plurality of connection terminal portions and at equal intervals, in order to achieve high density.
  • the dam part constituting a part of the outermost resin insulation layer entirely covers the unexposed wiring conductor.
  • the height of the dam portion is higher than the height of the unexposed wiring conductor and the height of the outermost resin insulation layer excluding the dam portion and the reinforcement portion.
  • the height is equal to the height of the outermost resin insulating layer excluding the dam portion and the reinforcing portion.
  • the width (upper width) of the dam portion is set to be slightly wider than the width (upper width) of the non-exposed wiring conductor. Specifically, for example, 1.1 times or more of the width (upper width) of the non-exposed wiring conductor It is set to 2.5 times or less.
  • this value is less than 1.1 times, the width of the dam portion becomes too narrow and the side surfaces of the unexposed wiring conductor may not be sufficiently covered. If this value is more than 2.5 times, there is a risk that the connection terminals and solder bumps on the semiconductor chip side will easily hit the dam portion.
  • the reinforcing part that constitutes a part of the outermost resin insulation layer is formed between the non-exposed wiring conductor and the adjacent connection terminal part on the surface of the resin insulation layer located immediately below the outermost resin insulation layer. Connected to the side of the dam. It is preferable that the reinforcing portion fills a space between the unexposed wiring conductor and the connection terminal portion adjacent thereto. With this configuration, the reinforcing portion becomes somewhat long along the direction orthogonal to the longitudinal direction of the unexposed wiring conductor and the dam portion, and the contact area between the reinforcing portion and the resin insulating layer that supports the reinforcing portion also increases. Therefore, the dam portion is reliably reinforced and the dam portion is stabilized. *
  • the height of the reinforcing portion when the bottom surface of the outermost insulating layer is used as a reference should be formed lower than the height of the dam portion. More specifically, the height of the reinforcing portion is preferably equal to or less than the height of the plurality of connecting terminal portions, and at least the surfaces of the plurality of connecting terminal portions are preferably exposed from the reinforcing portion. According to this configuration, even if the reinforcing portion completely fills the space between the unexposed wiring conductor and the connecting terminal portion, the surface of the connecting terminal portion is not positioned lower than the upper surface of the reinforcing portion, and the semiconductor chip side This makes it difficult to interfere with the connection terminal. *
  • the height of the reinforcing portion is lower than the height of the plurality of connection terminal portions, and it is more preferable that the entire surfaces of the plurality of connection terminal portions and the upper portions of the side surfaces are exposed from the reinforcement portion.
  • the dam part and the reinforcing part are both made of a resin insulating material having photosensitivity, but are preferably made of, for example, a common solder resist material and integrally formed. With such an integrally formed structure, the strength of the connecting portion between the dam portion and the reinforcing portion is increased, and the dam portion can be reinforced more reliably. Further, according to this structure, unlike the structure in which the dam part and the reinforcing part are formed using different solder resist materials, it is easy to reduce the manufacturing cost and simplify the manufacturing process. *
  • the plurality of connection terminal portions exposed on the surface of the laminate may be subjected to an outermost surface treatment such as plating or sputtering.
  • an outermost surface treatment such as plating or sputtering.
  • the conductive metal constituting the plurality of connection terminal portions is copper or a copper alloy
  • a layer made of a metal other than copper or copper alloy nickel layer, palladium layer, gold layer, A tin layer, etc.
  • Another means (means 2) for solving the above problem is the method of manufacturing a wiring board according to means 1, wherein the plurality of connection terminal portions and the wiring conductor are formed in a mounting region of the semiconductor chip.
  • the resin insulating layer forming step partial exposure and development are performed on the photosensitive resin insulating material disposed on the plurality of connection terminal portions and the wiring conductor.
  • the outermost resin insulation layer is formed.
  • a dam portion covering the wiring conductor is formed, and a reinforcing portion connected to the side surface of the dam portion is integrally formed. Therefore, even when the fine dam part is formed, the reinforcing part is connected to the side surface thereof, so that the bottom part of the dam part where the undercut is likely to occur is reinforced. Therefore, a fine and strong dam part can be obtained relatively easily and reliably.
  • the wiring board having excellent connection reliability with the semiconductor chip can be manufactured relatively easily and reliably.
  • the fragmentary sectional view which shows the organic wiring board of embodiment which actualized this invention The principal part expanded sectional view which shows the said wiring board by which the semiconductor chip was flip-chip mounted. The principal part expanded sectional view which shows the dam part and reinforcement part in the said wiring board.
  • the fragmentary sectional view for demonstrating the manufacturing method of the said wiring board The fragmentary sectional view for demonstrating the manufacturing method of the said wiring board.
  • the fragmentary sectional view for demonstrating the manufacturing method of the said wiring board The fragmentary sectional view for demonstrating the manufacturing method of the said wiring board.
  • the fragmentary sectional view for demonstrating the manufacturing method of the said wiring board The principal part expanded sectional view for demonstrating the manufacturing method of the said wiring board.
  • the principal part expanded sectional view for demonstrating the manufacturing method of the said wiring board The principal part expanded sectional view for demonstrating the manufacturing method of the said wiring board.
  • the principal part expanded sectional view for demonstrating the manufacturing method of the said wiring board The principal part expanded sectional view for demonstrating the manufacturing method of the said wiring board.
  • the principal part expanded sectional view for demonstrating the manufacturing method of the said wiring board The principal part expanded sectional view which shows the wiring board of another embodiment.
  • the principal part expanded sectional view which shows the wiring board of another embodiment The principal part expanded sectional view for demonstrating the manufacturing method of the conventional organic wiring board.
  • the principal part expanded sectional view for demonstrating the manufacturing method of the conventional organic wiring board The principal part expanded sectional view for demonstrating the manufacturing method of the conventional organic wiring board.
  • the principal part expanded sectional view for demonstrating the manufacturing method of the conventional organic wiring board The principal part expanded sectional view for demonstrating the manufacturing method of the conventional organic wiring board.
  • the principal part expanded sectional view for demonstrating the manufacturing method of the conventional organic wiring board The principal part expanded sectional view for demonstrating the manufacturing method of the conventional organic wiring board.
  • the principal part expanded sectional view for demonstrating the manufacturing method of the conventional organic wiring board The principal part expanded sectional view for demonstrating the manufacturing method of the conventional organic wiring board.
  • the principal part expanded sectional view for demonstrating the manufacturing method of the conventional organic wiring board The principal part expanded sectional view for demonstrating the manufacturing method of the conventional organic wiring board.
  • the principal part expanded sectional view for demonstrating the manufacturing method of the conventional organic wiring board The principal part expanded sectional view for demonstrating the manufacturing method of the conventional organic wiring board.
  • the principal part expanded sectional view for demonstrating the manufacturing method of the conventional organic wiring board The principal part expanded sectional view for demonstrating the manufacturing method of the conventional organic wiring board.
  • the organic wiring substrate 10 of the present embodiment is a wiring substrate having a peripheral structure, and as shown in FIG. 1, a substrate main surface 11 to be a semiconductor chip mounting surface, and a substrate back surface 12 positioned on the opposite side thereof. have.
  • the organic wiring substrate 10 includes a rectangular plate-shaped core substrate 13, a first buildup layer 31 formed on the core main surface 14 (upper surface in FIG. 1) of the core substrate 13, and a core back surface 15 of the core substrate 13. And a second buildup layer 32 formed on the lower surface (the lower surface in FIG. 1). *
  • the core substrate 13 of this embodiment is made of a resin insulating material (glass epoxy material) formed by impregnating a glass cloth as a reinforcing material with an epoxy resin, for example.
  • a plurality of through-hole conductors 16 are formed in the core substrate 13 so as to penetrate the core main surface 14 and the core back surface 15.
  • the inside of the through-hole conductor 16 is filled with a closing body 17 such as an epoxy resin.
  • a conductor layer 19 made of copper is patterned on the core main surface 14 and the core back surface 15 of the core substrate 13. These conductor layers 19 are electrically connected to the through-hole conductor 16. *
  • the first buildup layer 31 formed on the core main surface 14 of the core substrate 13 includes a plurality of resin insulating layers 21, 22, 23 made of thermosetting resin (epoxy resin) and a plurality of conductor layers made of copper. 24 is a laminate having a structure in which 24 is laminated.
  • the resin insulating layers 21 and 22 are made of a resin insulating material (for example, epoxy resin) having thermosetting properties.
  • the outermost conductor layer 24 includes a plurality of connection terminal portions 41 arranged along the outer periphery of the chip mounting region 54 in order to flip-chip mount the semiconductor chip 51.
  • the outermost resin insulating layer 23 in the first buildup layer 31 is a solder resist layer 23 made of a photosensitive resin insulating material.
  • a plurality of slit-like openings 43 are formed at positions corresponding to the four sides of the chip mounting region 54.
  • a plurality of connection terminal portions 41 are formed at equal intervals in the opening 43 of the solder resist layer 23.
  • these connection terminal portions 41 have a rectangular shape in a plan view, and are formed at the front end portion or in the middle of the wiring conductor 61 exposed from the opening 43 of the solder resist layer 23 (that is, the exposed wiring conductor 61). Yes.
  • the width of the connection terminal portion 41 is equal to the width of the exposed wiring conductor 61. *
  • connection terminal portions 41 are provided on the upper surface of the resin insulating layer 22.
  • via holes 33 and filled via conductors 34 are formed in the resin insulating layers 21 and 22, respectively. Each via conductor 34 is electrically connected to each conductor layer 19, 24 and connection terminal portion 41.
  • connection terminal 52 having a Cu pillar structure As the semiconductor chip 51 mounted on the wiring board 10 of the present embodiment, for example, one having a connection terminal 52 having a Cu pillar structure is used. In addition to the Cu pillar structure, a semiconductor chip 51 having connection terminals 52 having an Au plating bump structure or an Au stud structure may be flip-chip mounted. *
  • the second buildup layer 32 formed on the core back surface 15 of the core substrate 13 has substantially the same structure as the first buildup layer 31 described above. That is, the second buildup layer 32 has a structure in which the resin insulating layers 26, 27, and 28 and the conductor layer 24 are laminated. In the second buildup layer 32, a plurality of external connection terminals 45 for connection to a mother board (not shown) are formed as the outermost conductor layer 24. Also, via holes 33 and via conductors 34 are formed in the resin insulating layers 26 and 27. Each via conductor 34 is electrically connected to the conductor layers 19 and 24 and the external connection terminal 45. Further, the outermost resin insulation layer 28 in the second buildup layer 32 is a solder resist 28.
  • An opening 47 for exposing the external connection terminal 45 is provided at a predetermined location of the solder resist 28.
  • the lower surface exposed in the opening 47 is covered with a plating layer (not shown) (for example, a nickel gold plating layer).
  • a plurality of solder bumps 49 that can be electrically connected to a mother board (not shown) are disposed on the lower surface of the external connection terminal 45.
  • the organic wiring board 10 is mounted on a mother board (not shown) by the solder bumps 49.
  • another plurality of wiring conductors 62 (that is, non-exposed wiring conductors 62) not exposed to the outside are disposed. Yes.
  • the non-exposed wiring conductors 62 are formed in parallel with the exposed wiring conductors 61 having the connection terminal portions 41 so as to pass between them.
  • the width W3 in the upper part of the exposed wiring conductor 61 (that is, the width in the upper part of the connection terminal portion 41) is equal to the width W1 in the upper part of the non-exposed wiring conductor 62, and is set to, for example, about 10 ⁇ m to 30 ⁇ m (20 ⁇ m in this embodiment). ing.
  • the distance W4 between the exposed wiring conductor 61 and the non-exposed wiring conductor 62 is also set to, for example, about 10 ⁇ m to 30 ⁇ m (20 ⁇ m in this embodiment). Further, the height H2 of the exposed wiring conductor 61 and the unexposed wiring conductor 62 when the level of the surface of the resin insulating layer 22 (that is, the bottom surface of the solder resist layer 23) is used as a reference is, for example, about 10 ⁇ m to 20 ⁇ m (this embodiment) Is set to 15 ⁇ m). *
  • the solder resist layer 23 has a dam part 63 and a reinforcing part 64 in the opening 43.
  • the dam part 63 is made of a resin insulating material having photosensitivity, and covers the non-exposed wiring conductor 62 as a whole.
  • the height H3 of the dam part 63 with respect to the level of the surface of the resin insulating layer 22 is equal to the height of the solder resist layer 23 outside the opening part 43, for example, about 20 ⁇ m to 40 ⁇ m (30 ⁇ m in this embodiment). Is set.
  • the height H3 of the dam portion 63 is set to about 1.1 to 2.5 times the height H2, and in this embodiment about It is set to 2 times.
  • the width W2 in the upper part of the dam part 63 is set to about 1.1 to 2.5 times the width W1 in the upper part of the unexposed wiring conductor 62 (about 30 ⁇ m, which is about 1.5 times in this embodiment). Has been. *
  • the reinforcing portion 64 is formed between the non-exposed wiring conductor 62 and the connection terminal portion 41 adjacent thereto on the surface of the resin insulating layer 22 and completely fills the space therebetween.
  • the reinforcing portion 64 is made of a resin insulating material having photosensitivity like the dam portion 63, and is integrally connected to both side surfaces of the dam portion 63.
  • the height H1 of the reinforcing portion 64 when the level of the surface of the resin insulating layer 22 is used as a reference is lower than the height H2 of the exposed wiring conductor 61 (height H2 of the connection terminal portion 41). In this embodiment, the height H1 is 3 ⁇ m. It is set to about 12 ⁇ m.
  • a copper clad laminate in which a copper foil is pasted on both sides of a substrate made of glass epoxy is prepared. And drilling is performed using a drill machine, and the through-hole 72 (refer FIG. 4) which penetrates the front and back of the copper clad laminated board 71 is previously formed in the predetermined position.
  • the through-hole conductor 16 is formed in the through hole 72 by performing electroless copper plating and electrolytic copper plating on the inner surface of the through hole 72 of the copper clad laminate 71.
  • the cavity of the through-hole conductor 16 is filled with an insulating resin material (epoxy resin) and cured to form the closing body 17. Furthermore, the copper foil of the copper clad laminate 71 and the copper plating layer formed on the copper foil are patterned by, for example, a subtractive method. As a result, as shown in FIG. 5, the core substrate 13 on which the conductor layer 19 and the through-hole conductor 16 are formed is obtained. *
  • the first build-up layer 31 is formed on the core main surface 14 of the core substrate 13, and the second build-up layer 32 is also formed on the core back surface 15 of the core substrate 13.
  • sheet-like resin insulation layers 21 and 26 made of epoxy resin are disposed on the core main surface 14 and the core back surface 15 of the core substrate 13, and the resin insulation layers 21 and 26 are attached.
  • via holes 33 are formed at predetermined positions of the resin insulating layers 21 and 26 by performing laser processing using, for example, excimer laser, UV laser, CO 2 laser or the like (see FIG. 6).
  • a desmear process is performed to remove smear in each via hole 33 using an etching solution such as a potassium permanganate solution.
  • an etching solution such as a potassium permanganate solution.
  • the desmear process in addition to treatment with an etchant, for example it may perform processing of plasma ashing using O 2 plasma.
  • via conductors 34 are formed in the via holes 33 by performing electroless copper plating and electrolytic copper plating according to a conventionally known method. Further, the conductor layer 24 is patterned on the resin insulating layers 21 and 26 by performing etching by a conventionally known method (for example, semi-additive method) (see FIG. 7).
  • the other resin insulation layers 22 and 27 and the conductor layer 24 are also formed by the same method as the resin insulation layers 21 and 26 and the conductor layer 24 described above, and are laminated on the resin insulation layers 21 and 26.
  • an exposed wiring conductor 61 and a non-exposed wiring conductor 62 each having a plurality of connection terminal portions 41 are formed (see FIG. 8: conductor layer forming step).
  • a plurality of external connection terminals 45 are formed as the conductor layer 24 on the resin insulating layer 27.
  • a photosensitive resin insulating material that will later become the solder resist layer 23 is applied and cured on the resin insulating layer 22, and a resin insulating material layer 66 covering the exposed wiring conductor 61 and the unexposed wiring conductor 62 as a whole is formed.
  • a solder resist material mainly composed of a photosensitive epoxy resin is selected as the photosensitive resin insulating material.
  • the solder resist material may be a liquid that can be applied or a film that can be attached.
  • a photomask 81 in which a light passage portion 82 is formed at a predetermined position of the glass substrate is disposed on the resin insulating material layer 66.
  • the resin insulating material layer 66 is partially exposed by irradiating the ultraviolet ray 83 through the photomask 81 under conventional normal conditions (see FIG. 10).
  • the ultraviolet ray 83 hits a region immediately below the light passage portion 82 of the photomask 81, and the region in the resin insulating material layer 66 is selectively exposed.
  • an exposure portion 84 that will later become the dam portion 63 and the like is indicated by a broken line.
  • the resin insulating material layer 66 is developed using a dedicated developer (see FIG. 11).
  • the solder resist layer 23 which is the outermost resin insulation layer is formed, and the dam part 63 and the reinforcing part 64 forming a part of the solder resist layer 23 are integrally formed (resin insulation layer forming step) ).
  • the exposed wiring conductor 61 is subjected to an outermost surface treatment such as nickel-gold plating.
  • the organic wiring board 10 of this embodiment has the dam part 63 and the reinforcement part 64 as mentioned above. Therefore, even when the fine dam portion 63 is formed as a part of the solder resist layer 23, the reinforcing portion 64 is connected to the side surface. For this reason, the bottom part of the dam part 63 which tends to generate an undercut is reinforced. Therefore, the fine and strong dam part 63 can be obtained, and the non-exposed wiring conductor 62 disposed through the plurality of connection terminal parts 41 is reliably protected by the dam part 63. As a result, situations such as peeling of the dam part 63 and exposure of the unexposed wiring conductor 62 from the dam part 63 are avoided.
  • the reinforcing portion 64 is formed lower than the height H3 of the dam portion 63, it is avoided that the reinforcing portion 64 hits the connection terminal 52 on the semiconductor chip 51 side. From the above, the connection terminal 52 on the semiconductor chip 51 side and the connection terminal portion 41 can be reliably connected via the solder bump 53, and the organic wiring substrate 10 having excellent connection reliability with the semiconductor chip 51 is obtained. Can do. *
  • the reinforcing portion 64 completely fills the space between the unexposed wiring conductor 62 and the connection terminal portion 41 adjacent thereto.
  • the reinforcing portion 64 is elongated to some extent along a direction orthogonal to the longitudinal direction of the unexposed wiring conductor 62 and the dam portion 63 (that is, the left-right direction in FIGS. 1 to 3). Therefore, the contact area between the reinforcing portion 64 and the resin insulating layer 22 that supports the reinforcing portion 64 also increases. Therefore, there is an advantage that the dam part 63 is reliably reinforced and the dam part 63 is stabilized. Therefore, it is possible to more reliably avoid situations such as peeling of the dam portion 63 and exposure of the non-exposed wiring conductor 62 from the dam portion 63, and further improve the connection reliability with the semiconductor chip 51.
  • the height H1 of the reinforcing portion 64 is lower than the height H2 of the plurality of connection terminal portions 41.
  • the surfaces of the plurality of connection terminal portions 41 and the upper side portions of the side surfaces are exposed from the reinforcing portion 64.
  • the dam part 63 and the reinforcement part 64 are integrally formed of a common solder resist material. And if it is the structure integrally formed in this way, the intensity
  • the desired organic wiring substrate 10 is manufactured through the conductor layer forming step and the resin insulating layer forming step as described above. That is, in the resin insulating layer forming step, when the solder resist layer 23 is formed, the dam portion 63 that covers the unexposed wiring conductor 62 and the reinforcing portion 64 that is connected to the side surface are integrally formed. The Therefore, even when the fine dam portion 63 is formed, since the reinforcing portion 64 is connected to the side surface thereof, the bottom portion of the dam portion 63 that is likely to generate an undercut is reinforced. Therefore, the fine and strong dam part 63 can be obtained relatively easily and reliably. Moreover, according to the manufacturing method of this embodiment, it is not necessary to take measures for avoiding undercutting.
  • the organic wiring substrate 10 having excellent connection reliability with the semiconductor chip 51 can be relatively easily and reliably manufactured.
  • the height of the reinforcing portion 64 is lower than the height of the connection terminal portion 41, and the surface of the connection terminal portion 41 and the upper portion of the side surface are exposed from the reinforcing portion 64. It is good also as a structure like the organic wiring board 10A of the embodiment. That is, in the organic wiring substrate 10A, the height of the reinforcing portion 64 is equal to the height of the connection terminal portion 41, and only the surface of the connection terminal portion 41 is exposed from the reinforcing portion 64.
  • the reinforcing portion 64 is formed so as to completely fill the space between the non-exposed wiring conductor 62 and the connection terminal portion 41 on the surface of the resin insulating layer 22, but for example, another embodiment shown in FIG. A configuration that is not completely filled, such as the organic wiring board 10B of the form, may be employed. That is, in the organic wiring substrate 10 ⁇ / b> B, the side surface of the reinforcing portion 64 is not in contact with the side surface of the connection terminal portion 41. *
  • dam portion 63 and the reinforcing portion 64 are formed of a common solder resist material, but may be formed using different resin insulating material layers 66. *
  • the solder resist layer 23 is formed by performing partial exposure and development, and the dam portion 63 and the reinforcement The part 64 was integrally formed.
  • the method for forming the outermost resin insulation layer 23 can be changed as appropriate. For example, a method of applying a thermosetting resin insulation layer 23 to the surface of the resin insulation layer 22 and thermally curing it, and then mechanically polishing until the surface of each connection terminal portion 41 is exposed may be adopted. Good. In this case, instead of mechanical polishing, abrasive processing such as sandblasting may be employed, or dry etching processing may be employed. *
  • the organic wiring board 10 of the said embodiment was a wiring board which has the core board
  • substrate 13 it is not limited to this, You may make this invention apply to the coreless wiring board which does not have a core. . *
  • the form of the organic wiring board 10 in the said embodiment is BGA (ball grid array), it is not limited only to BGA, For example, it is on wiring boards, such as PGA (pin grid array) and LGA (land grid array).
  • BGA ball grid array
  • PGA pin grid array
  • LGA laand grid array

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Abstract

積層体の最表層に形成した微細かつ強固なダム部により配線導体が確実に保護され、半導体チップとの接続信頼性に優れた配線基板を提供すること。この配線基板１０を構成する積層体３１は、最表層の導体層２４として複数の接続端子部４１と配線導体６２とを含む。配線導体６２は、半導体チップ５１をフリップチップ実装するための複数の接続端子部４１間を通過して配設される。積層体の最表層の樹脂絶縁層２３は、ダム部６３と補強部６４とを有する。ダム部６３は、配線導体６２を被覆する。補強部６４は、配線導体６２に隣接する接続端子部４１との間にてダム部６３の高さＨ３よりも低く形成される。補強部６４は、ダム部６３の側面に連結される。

Description

配線基板及びその製造方法
本発明は、半導体チップをフリップチップ実装するための複数の接続端子部を備えた配線基板及びその製造方法に関するものである。
コンピュータのマイクロプロセッサ等として使用される半導体集積回路素子（半導体チップ）は、近年ますます高速化、高機能化しており、これに付随して端子数が増え、端子間のピッチも狭くなる傾向にある。一般的に半導体チップの底面には多数の接続端子が配置されており、半導体チップの各接続端子は半導体搭載用の配線基板に形成された複数の接続端子部にフリップチップの形態で接続される。　
例えば、チップ底面の外周に沿って多数の接続端子を配置したペリフェラル型の半導体チップをフリップチップ接続するための配線基板が従来提案されている（例えば、特許文献１参照）。この配線基板では、半導体チップの外形に相当する矩形状のチップ搭載領域が基板主面にて設定され、そのチップ搭載領域の外周に沿うようにして複数の接続端子部が配列されている。複数の接続端子部は帯状の配線導体の一部に設けられている。配線導体自体は、最表層の樹脂絶縁層として基板主面上に設けられたソルダーレジスト層により被覆され、その殆どの部分が非露出の状態とされている。一方、各接続端子部の表面は、ソルダーレジスト層に設けられた開口部を介して外部に露出している。そして、露出した各接続端子部と半導体チップ側の接続端子とは対向配置され、互いにはんだバンプ等を介して電気的に接続されるようになっている。　
ところで、この種の配線基板１０１では、多端子化や狭ピッチ化の一環として、例えばソルダーレジスト層１０２の開口部１０３にて、接続端子部１０４を有する複数の配線導体１０５間を通過するように、別の配線導体１０６を配設することが試みられている（図１５参照）。ただし、接続端子部１０４を有する配線導体１０５間に配線導体１０６を配設する場合には、接続端子部１０４と配線導体１０６との距離が接近しすぎて、相互の絶縁距離が確保されなくなる。このため、はんだ接続時にショート不良が発生するおそれがある。その対策としては、開口部１０３に位置する当該配線導体１０６についてもソルダーレジスト層１０２の一部（便宜上「ダム部１０７」とする。）で被覆して、隣接する接続端子部１０４との絶縁を図る必要がある。　
ここで、図１５に示す配線基板１０１を製造する手順について説明する。まず、樹脂絶縁層１０８上に銅めっき層を形成し、これをエッチングすることにより、配線導体１０５，１０６を形成する。次に、樹脂絶縁層１０８上に後にソルダーレジスト層１０２となる感光性樹脂絶縁材料を塗布し、配線導体１０５，１０６を被覆する樹脂絶縁材料層１０９を形成する（図１６参照）。次に、樹脂絶縁材料層１０９上にフォトマスク１１０を配置し、この状態でフォトマスク１１０を介して紫外線１１２を照射する。すると、基本的にフォトマスク１１０の光通過部１１１の直下となる領域に紫外線１１２が当たり、樹脂絶縁材料層１０９における当該領域が選択的に感光する。図１６では、露光部１１３を破線で示している。この後、露光された樹脂絶縁材料層１０９を現像し（図１７参照）、さらに熱や紫外線にてキュアし、表面に露出する配線導体１０５にめっき等の最表面処理をする。その結果、微細なダム部１０７を有する配線基板１０１が完成する（図１８参照）。
特開２０１１－１４６４４号公報
しかしながら、上記従来の製造方法において、幅の狭い微細なダム部１０７を形成するべく露光部１１３の幅を狭く設定して、従来の通常の条件にて露光を行った場合、紫外線１１２が樹脂絶縁材料層１０９の深部まで十分に届かないことがある。そしてこの場合には、図１６に示すような露光部１１３の底部に露光不良部位１１５（未露光あるいは露光が不十分な部位）が発生しやすくなる。よって、従来の通常の条件にて現像を行うと、底部の露光不良部位１１５が露出し、そこがアンダーカット１１４となってしまう（図１７等を参照）。このようなアンダーカット１１４があると、ダム部１０７の強度が低下して剥離等が起こる原因となる。そればかりでなく、アンダーカット１１４にて配線導体１０６が露出していると、最表面処理を行うことで配線導体１０５，１０６間にショート不良が発生するおそれがある。また、図１９に示すように、半導体チップ１２０側の接続端子１２１上に形成されたはんだバンプ１２２がアンダーカット１１４に入り込み、これが原因となってショート不良が発生するおそれもある。ちなみに、上記のようなソルダーレジスト露光時の硬化深度不足といった問題は、ソルダーレジスト層１０２が厚くなるほど顕著になる。　
ソルダーレジスト露光時の硬化深度不足という事態を回避するためには、例えば、従来の通常の条件よりも高い露光量で露光を行うという対策が考えられる。そしてこの対策によれば、露光不良部位１１５が発生しなくなるため、パターン底部にアンダーカット１１４ができなくなる（図２０～図２３参照）。ただし、この場合にはフォトマスク１１０の光通過部１１１から紫外線１１２が漏れる「ハレーション」が発生し、光通過部１１１の直下ばかりでなくその周囲の領域まで感光しやすくなる（図２０にて１１３Ａで示す領域を参照）。よって、本来狙っている幅よりも広い幅のダム部１０７Ａが形成され、これに伴って接続端子部１０４を挟んでその両側に位置するダム部１０７Ａ間の間隔が狭くなってしまう（図２１，図２２参照）。そのため、半導体チップ１２０を配線基板１０１上に搭載する際に両者が少しでも位置ずれしていると、半導体チップ１２０側の接続端子１２１やはんだバンプ１２２がダム部１０７Ａに当たってしまう（図２３参照）。ゆえに、この場合には接続不良が起こりやすくなる。　
また別の対策として、従来の通常の条件よりも現像時間を短くして現像を行うことも考えられる。そしてこの対策によれば、露光不良部位１１５が残っていたとしてもその部位が現像されないことから、パターン底部にアンダーカット１１４ができなくなる（図２４～図２６参照）。ただし、この場合には本来現像されるべき部分（例えば接続端子部１０４の上面など）にて樹脂絶縁材料層１０９が部分的に付着したまま硬化してしまう。その結果、ソルダーレジスト残り１２３が生じ、めっき等の最表面処理を行った場合に無めっき部ができやすくなるという不具合が発生する（図２６参照）。ゆえに、この場合においても接続不良が起こりやすくなる。　
従って、アンダーカット１１４を防止するためのこれら２つの対策を講じたとしても、配線導体１０６上に微細かつ強固なダム部１０７を安定的に形成することは困難であった。　
本発明は上記の課題に鑑みてなされたものであり、その目的は、積層体の最表層に形成した微細かつ強固なダム部により配線導体が確実に保護され、半導体チップとの接続信頼性に優れた配線基板を提供することにある。また、別の目的は、半導体チップとの接続信頼性に優れた上記の配線基板を確実に製造することができる配線基板の製造方法を提供することにある。
そして上記課題を解決するための手段（手段１）としては、樹脂絶縁層及び導体層がそれぞれ１層以上積層された積層体を有し、前記積層体の最表層の前記導体層が、半導体チップをフリップチップ実装するために前記半導体チップの搭載領域にて配列されて表面に露出する複数の接続端子部と、前記複数の接続端子部間に配設された配線導体とを含む配線基板において、前記積層体の最表層の前記樹脂絶縁層は、前記配線導体を被覆するダム部と、前記配線導体とそれに隣接する接続端子部との間にて前記ダム部の高さよりも低く形成され、前記ダム部の側面に連結された補強部とを有することを特徴とする配線基板、がある。　
従って、手段１に記載の発明によると、積層体の最表層の樹脂絶縁層の一部として微細なダム部を形成したときでも、その側面に補強部が連結されているため、本来アンダーカットが発生しやすいダム部の底部が補強される。よって、微細かつ強固なダム部を得ることができ、複数の接続端子部間を通過して配設された配線導体がそのダム部により確実に保護される結果、ダム部の剥離やダム部からの配線導体の露出が回避される。また、補強部はダム部の高さよりも低く形成されているため、補強部が半導体チップ側の接続端子に当たることが回避される。以上のことから、半導体チップ側の接続端子と接続端子部とをはんだ等を介して確実に接続可能となり、半導体チップとの接続信頼性に優れた配線基板を得ることができる。　
手段１の配線基板は、樹脂絶縁層及び導体層がそれぞれ１層以上積層された積層体を有する、いわゆるオーガニック配線基板である。オーガニック配線基板の利点は、例えばセラミック配線基板などに比較して配線の高密度化が達成しやすいことである。　
樹脂絶縁層は、例えば熱硬化性樹脂を主体とするビルドアップ材を用いて形成されてもよい。樹脂絶縁層の形成材料の具体例としては、エポキシ樹脂、フェノール樹脂、ウレタン樹脂、シリコーン樹脂、ポリイミド樹脂などの熱硬化性樹脂が挙げられる。そのほか、これらの樹脂とガラス繊維（ガラス織布やガラス不織布）やポリアミド繊維等の有機繊維との複合材料、あるいは、連続多孔質ＰＴＦＥ等の三次元網目状フッ素系樹脂基材にエポキシ樹脂などの熱硬化性樹脂を含浸させた樹脂－樹脂複合材料等を使用してもよい。　
導体層は、銅、銀、金、白金、ニッケル、チタン、アルミニウム、クロム等といった各種の導電金属を用いて形成可能であるが、オーガニック配線基板における導体層としては、銅を主体として構成されたものであることが好ましい。導体層を形成する手法としては、サブトラクティブ法、セミアディティブ法、フルアディティブ法などといった公知の手法が採用される。具体的に言うと、例えば、銅箔のエッチング、無電解銅めっきあるいは電解銅めっきなどの手法が適用される。なお、スパッタやＣＶＤ等の手法により薄膜を形成した後にエッチングを行うことで導体層を形成したり、導電性ペースト等の印刷により導体層を形成したりすることも可能である。　
半導体チップは、配線基板上にフリップチップ実装可能なものであればよく、具体的にはチップ底面の外周に沿って多数の接続端子を配置したペリフェラル型、チップ底面の全域に多数の接続端子を配置したエリア型のいずれであってもよい。また、半導体チップとしては、コンピュータのマイクロプロセッサとして使用されるＩＣチップ、ＤＲＡＭ（Dynamic Random Access Memory）やＳＲＡＭ（Static Random Access Memory ）などのＩＣチップを挙げることができる。　
この配線基板は、積層体における最表層の導体層の一部として、複数の接続端子部を有している。複数の接続端子部は、半導体チップをフリップチップ実装するために半導体チップの搭載領域にて配列されている。複数の接続端子部は、例えば最表層の樹脂絶縁層から露出している配線導体（便宜上「露出配線導体」と呼ぶ。）の一部として形成される。接続端子部は露出配線導体の端部に位置していてもよく、その途中に位置していてもよい。また、接続端子部は露出配線導体と等幅に形成されていてもよいが、幅広に形成されていてもよい。幅広の接続端子部を採用した場合、平面視で例えば正方形状、長方形状、楕円形状、円形状となるように形成してもよい。接続端子部の平面視形状は、配線基板の設計デザインや半導体チップの端子形状等に応じて適宜変更することができる。なお、長方形状の接続端子部とした場合には、複数の接続端子部を互いに平行となるように配列してもよい。また、隣接する複数の接続端子部間のピッチは例えば１００μｍ以下に設定され、好ましくは高密度化を達成するために８０μｍ以下に設定される。　
　積層体における最表層の樹脂絶縁層は、感光性を有する樹脂絶縁材料からなり、例えばソルダーレジスト材などにより形成される。最表層の樹脂絶縁層における半導体チップの搭載領域には、１つまたは２つ以上の開口部が形成される。複数の接続端子部の表面を露出させることが可能であれば、開口部の形状は特に限定されないが、例えば矩形帯状（スリット状）とすることが好適である。　
この配線基板は、積層体における最表層の導体層として、複数の接続端子部間を通過して配設された配線導体を有している。この配線導体は、上記の露出配線導体とは異なり基本的に外部に露出しないものであるため、便宜上「非露出配線導体」と呼ぶことにする。非露出配線導体は、複数の接続端子部と平行な位置関係でかつ等間隔を隔てて配置されることが、高密度化を達成するうえで好ましい。　
最表層の樹脂絶縁層の一部を構成するダム部は、非露出配線導体を全体的に被覆している。最表層の樹脂絶縁層の底面のレベルを基準としたとき、ダム部の高さは、非露出配線導体の高さよりも高くかつダム部と補強部とを除いた最表層の樹脂絶縁層の高さ以下に設定されるが、強いて言えばダム部と補強部とを除いた最表層の樹脂絶縁層の高さと同等であることがよい。ダム部の幅（上部幅）は、非露出配線導体の幅（上部幅）よりもやや広い程度に設定され、具体的には例えば非露出配線導体の幅（上部幅）の１．１倍以上２．５倍以下に設定される。この値が１．１倍未満であると、ダム部の幅が狭くなりすぎて、非露出配線導体の側面が十分に被覆されなくなるおそれがある。この値が２．５倍超であると、半導体チップ側の接続端子やはんだバンプがダム部に当たりやすくなるおそれがある。　
最表層の樹脂絶縁層の一部を構成する補強部は、最表層の樹脂絶縁層の直下に位置する樹脂絶縁層の表面上において非露出配線導体とそれに隣接する接続端子部との間に形成され、ダム部の側面に連結される。補強部は、非露出配線導体とそれに隣接する接続端子部との間を埋めていることが好ましい。この構成であると、非露出配線導体及びダム部の長手方向と直交する方向に沿って補強部がある程度長くなり、補強部とそれを支持する上記樹脂絶縁層との接触面積も大きくなる。よって、ダム部が確実に補強され、ダム部が安定する。　
最表層の絶縁層の底面を基準としたときの補強部の高さは、ダム部の高さよりも低く形成されるべきである。より具体的に言うと、補強部の高さは複数の接続端子部の高さ以下であることがよく、複数の接続端子部の少なくとも表面は補強部から露出していることがよい。この構成によると、補強部が非露出配線導体と接続端子部との間を完全に埋めていたとしても、接続端子部の表面が補強部の上面よりも低い位置とはならず、半導体チップ側の接続端子との接続に支障を来しにくくなる。　
さらには、補強部の高さは複数の接続端子部の高さよりも低いことがより好ましく、複数の接続端子部の表面全体及び側面の上側部分は補強部から露出していることがより好ましい。この構成であると、補強部が非露出配線導体と接続端子部との間を完全に埋めていたとしても、接続端子部における３つの面が露出した状態となり、はんだ等の導電金属材料との接触面積も大きくなる。よって、接続端子部と半導体チップ側の接続端子とがより確実に接続される。　
ダム部及び補強部は、ともに感光性を有する樹脂絶縁材料からなるが、例えば共通のソルダーレジスト材料からなり一体形成されていることが好ましい。このように一体形成された構造であると、ダム部と補強部との連結部分の強度が上がり、ダム部をより確実に補強することができる。また、この構造によれば、ダム部と補強部とをそれぞれ異なるソルダーレジスト材料を用いて形成する構造とは異なり、製造コストの低減及び製造工程の簡略化を図りやすくなる。　
積層体の表面に露出する複数の接続端子部には、めっきやスパッタリング等といった最表面処理が施されていてもよい。例えば、複数の接続端子部を構成している導電金属が銅または銅合金であるような場合、最表面処理として、銅または銅合金以外の金属からなる層（ニッケル層、パラジウム層、金層、スズ層など）が形成されてもよい。　
上記課題を解決するための別の手段（手段２）としては、手段１に記載の配線基板の製造方法であって、前記半導体チップの搭載領域に前記複数の接続端子部及び前記配線導体を形成する導体層形成工程と、前記複数の接続端子部及び前記配線導体を覆うような状態で最表層の前記樹脂絶縁層となる感光性を有する樹脂絶縁材料をそれらの上に配置し、前記樹脂絶縁材料に対する部分的な露光及び現像を行うことにより、最表層の前記樹脂絶縁層を形成するとともに、前記ダム部及び前記補強部を一体的に形成する樹脂絶縁層形成工程とを含むことを特徴とする配線基板の製造方法、がある。　
従って、手段２に記載の発明によると、樹脂絶縁層形成工程において、複数の接続端子部及び配線導体の上に配置された感光性を有する樹脂絶縁材料に対し、部分的な露光及び現像を行うことにより、最表層の樹脂絶縁層が形成される。このとき、併せて配線導体を被覆するダム部が形成されるとともに、そのダム部の側面に連結する補強部が一体的に形成される。ゆえに、微細なダム部を形成したときでも、その側面に補強部が連結されているため、本来アンダーカットが発生しやすいダム部の底部が補強される。よって、微細かつ強固なダム部を比較的容易にかつ確実に得ることができる。また、本発明によれば、アンダーカットを回避するための対策を講じる必要がなくなるので、高露光量に起因するハレーションの発生や、短時間現像に起因する樹脂残りの発生といった事態が回避され、結果的に接続不良が起こるリスクが低減される。よって、半導体チップとの接続信頼性に優れた上記の配線基板を比較的容易にかつ確実に製造することができる。
本発明を具体化した実施形態のオーガニック配線基板を示す部分断面図。 半導体チップがフリップチップ実装された上記配線基板を示す要部拡大断面図。 上記配線基板におけるダム部及び補強部を示す要部拡大断面図。 上記配線基板の製造方法を説明するための部分断面図。 上記配線基板の製造方法を説明するための部分断面図。 上記配線基板の製造方法を説明するための部分断面図。 上記配線基板の製造方法を説明するための部分断面図。 上記配線基板の製造方法を説明するための要部拡大断面図。 上記配線基板の製造方法を説明するための要部拡大断面図。 上記配線基板の製造方法を説明するための要部拡大断面図。 上記配線基板の製造方法を説明するための要部拡大断面図。 上記配線基板の製造方法を説明するための要部拡大断面図。 別の実施形態の配線基板を示す要部拡大断面図。 別の実施形態の配線基板を示す要部拡大断面図。 従来のオーガニック配線基板の製造方法を説明するための要部拡大断面図。 従来のオーガニック配線基板の製造方法を説明するための要部拡大断面図。 従来のオーガニック配線基板の製造方法を説明するための要部拡大断面図。 従来のオーガニック配線基板の製造方法を説明するための要部拡大断面図。 従来のオーガニック配線基板の製造方法を説明するための要部拡大断面図。 従来のオーガニック配線基板の製造方法を説明するための要部拡大断面図。 従来のオーガニック配線基板の製造方法を説明するための要部拡大断面図。 従来のオーガニック配線基板の製造方法を説明するための要部拡大断面図。 従来のオーガニック配線基板の製造方法を説明するための要部拡大断面図。 従来のオーガニック配線基板の製造方法を説明するための要部拡大断面図。 従来のオーガニック配線基板の製造方法を説明するための要部拡大断面図。 従来のオーガニック配線基板の製造方法を説明するための要部拡大断面図。
以下、本発明を配線基板としてのオーガニック配線基板に具体化した一実施形態を図１～図１２に基づき詳細に説明する。　
本実施形態のオーガニック配線基板１０は、ペリフェラル構造を有する配線基板であって、図１に示されるように、半導体チップ搭載面となる基板主面１１と、その反対側に位置する基板裏面１２とを有している。このオーガニック配線基板１０は、矩形板状のコア基板１３と、コア基板１３のコア主面１４（図１は上面）上に形成される第１ビルドアップ層３１と、コア基板１３のコア裏面１５（図１では下面）上に形成される第２ビルドアップ層３２とを備えている。　
本実施形態のコア基板１３は、例えば補強材としてのガラスクロスにエポキシ樹脂を含浸させてなる樹脂絶縁材（ガラスエポキシ材）により構成されている。コア基板１３には、複数のスルーホール導体１６がコア主面１４及びコア裏面１５を貫通するように形成されている。スルーホール導体１６の内部は、例えばエポキシ樹脂などの閉塞体１７で埋められている。また、コア基板１３のコア主面１４及びコア裏面１５の上には、銅からなる導体層１９がパターン形成されている。これらの導体層１９はスルーホール導体１６に電気的に接続されている。　
コア基板１３のコア主面１４上に形成された第１ビルドアップ層３１は、熱硬化性樹脂（エポキシ樹脂）からなる複数の樹脂絶縁層２１，２２，２３と、銅からなる複数の導体層２４とを積層した構造を有する積層体である。樹脂絶縁層２１，２２は、熱硬化性を有する樹脂絶縁材料（例えばエポキシ樹脂）からなる。第１ビルドアップ層３１において、最表層の導体層２４は、半導体チップ５１をフリップチップ実装するためにチップ搭載領域５４の外周に沿って配置された複数の接続端子部４１を含んでいる。本実施形態では、第１ビルドアップ層３１における最表層の樹脂絶縁層２３が、感光性を有する樹脂絶縁材料からなるソルダーレジスト層２３となっている。ソルダーレジスト層２３において、チップ搭載領域５４の四辺に対応する位置には、スリット状の開口部４３が複数形成されている。そして、図１～図３に示されるように、ソルダーレジスト層２３の開口部４３内には複数の接続端子部４１が等間隔に形成されている。本実施形態においてこれらの接続端子部４１は、平面視で長方形状をなし、ソルダーレジスト層２３の開口部４３から露出する配線導体６１（即ち露出配線導体６１）の先端部または途中に形成されている。ここでは、接続端子部４１の幅は露出配線導体６１の幅と等しくなっている。　
本実施形態では、複数の接続端子部４１は樹脂絶縁層２２の上面に設けられている。また、樹脂絶縁層２１，２２には、それぞれビア穴３３及びフィルドビア導体３４が形成されている。各ビア導体３４は、各導体層１９，２４、接続端子部４１に電気的に接続される。　
本実施形態の配線基板１０に実装される半導体チップ５１としては、例えばＣｕピラー構造の接続端子５２を有するものが用いられる。なお、Ｃｕピラー構造以外に、Ａｕめっきバンプ構造やＡｕスタッド構造の接続端子５２を有する半導体チップ５１をフリップチップ実装してもよい。　
コア基板１３のコア裏面１５上に形成された第２ビルドアップ層３２は、上述した第１ビルドアップ層３１とほぼ同じ構造を有している。即ち、第２ビルドアップ層３２は、樹脂絶縁層２６，２７，２８と、導体層２４とを積層した構造を有している。第２ビルドアップ層３２において、最表層の導体層２４として、マザーボート（図示略）に接続するための複数の外部接続端子４５が形成されている。また、樹脂絶縁層２６，２７にもビア穴３３及びビア導体３４が形成されている。各ビア導体３４は、導体層１９，２４、外
部接続端子４５に電気的に接続されている。さらに、第２ビルドアップ層３２における最表層の樹脂絶縁層２８はソルダーレジスト２８となっている。ソルダーレジスト２８の所定箇所には、外部接続端子４５を露出させるための開口部４７が設けられている。また、外部接続端子４５において、開口部４７内にて露出する下面は、図示しないめっき層（例えばニッケル金めっき層）で覆われている。その外部接続端子４５の下面には、図示しないマザーボードに対して電気的に接続可能な複数のはんだバンプ４９が配設されている。そして、各はんだバンプ４９により、オーガニック配線基板１０は図示しないマザーボード上に実装される。　
次に、基板主面１１側の第１ビルドアップ層３１におけるチップ搭載領域５４に設けられた諸構造について図２，図３を用いて詳述する。　
ソルダーレジスト層２３のすぐ下に位置する樹脂絶縁層２２上には、露出配線導体のほか、外部に露出していない別の複数の配線導体６２（即ち非露出配線導体６２）が配設されている。非露出配線導体６２は、接続端子部４１を有する露出配線導体６１間を通過するようにそれらと平行に形成されている。露出配線導体６１の上部における幅Ｗ３（即ち接続端子部４１の上部における幅）は、非露出配線導体６２の上部における幅Ｗ１と等しく、例えば１０μｍ～３０μｍ程度（本実施形態では２０μｍ）に設定されている。露出配線導体６１と非露出配線導体６２との間隔Ｗ４も、例えば１０μｍ～３０μｍ程度（本実施形態では２０μｍ）に設定されている。また、樹脂絶縁層２２の表面（即ちソルダーレジスト層２３の底面）のレベルを基準としたときの露出配線導体６１及び非露出配線導体６２の高さＨ２は、例えば１０μｍ～２０μｍ程度（本実施形態では１５μｍ）に設定されている。　
ソルダーレジスト層２３は開口部４３内にダム部６３及び補強部６４を有している。ダム部６３は、感光性を有する樹脂絶縁材料からなるものであって、非露出配線導体６２を全体的に被覆している。樹脂絶縁層２２の表面のレベルを基準としたときのダム部６３の高さＨ３は、開口部４３外のソルダーレジスト層２３の高さと等しく、例えば２０μｍ～４０μｍ程度（本実施形態では３０μｍ）に設定されている。なお、非露出配線導体６２の高さＨ２を比較対象とした場合、ダム部６３の高さＨ３は当該高さＨ２の１．１倍～２．５倍程度に設定され、本実施形態では約２倍に設定されている。一方、ダム部６３の上部における幅Ｗ２は、非露出配線導体６２の上部における幅Ｗ１の１．１倍～２．５倍程度（本実施形態では約１．５倍である約３０μｍ）に設定されている。　
補強部６４は、樹脂絶縁層２２の表面上において非露出配線導体６２とそれに隣接する接続端子部４１との間に形成され、それらの間を完全に埋めている。補強部６４は、ダム部６３と同様に感光性を有する樹脂絶縁材料からなるものであって、ダム部６３の両方の側面に対して一体的に連結されている。樹脂絶縁層２２の表面のレベルを基準としたときの補強部６４の高さＨ１は、露出配線導体６１の高さＨ２（接続端子部４１の高さＨ２）よりも低く、本実施形態では３μｍ～１２μｍ程度に設定されている。従って、複数の接続端子部４１の表面全体及び側面の上側部分は、補強部６４から露出した状態となっている。なお、複数の接続端子部４１の側面の下側部分は、補強部６４と接した状態となっている。また、図３に示すように、ダム部６３の上縁部位６３ａの角部の曲率と、ダム部６３と補強部６４との連結部位６３ｂの角部の曲率とを比較すると、前者のほうが後者よりも大きくなっている。　
次に、本実施形態のオーガニック配線基板１０の製造方法を図４～図１２に基づいて説明する。　
まず、ガラスエポキシからなる基材の両面に銅箔が貼付された銅張積層板を準備する。そして、ドリル機を用いて孔あけ加工を行い、銅張積層板７１の表裏面を貫通する貫通孔７２（図４参照）を所定位置にあらかじめ形成しておく。そして、銅張積層板７１の貫通孔７２の内面に対する無電解銅めっき及び電解銅めっきを行うことで、貫通孔７２内にスルーホール導体１６を形成する。　
その後、スルーホール導体１６の空洞部を絶縁樹脂材料（エポキシ樹脂）で穴埋めしかつ硬化させて、閉塞体１７を形成する。さらに、銅張積層板７１の銅箔とその銅箔上に形成された銅めっき層とを、例えばサブトラクティブ法によってパターニングする。この結果、図５に示されるように、導体層１９及びスルーホール導体１６が形成されたコア基板１３を得る。　
そして、ビルドアップ工程を行うことで、コア基板１３のコア主面１４の上に第１ビルドアップ層３１を形成するとともに、コア基板１３のコア裏面１５の上にも第２ビルドアップ層３２を形成する。　
詳しくは、コア基板１３のコア主面１４及びコア裏面１５の上に、エポキシ樹脂からなるシート状の樹脂絶縁層２１，２６を配置し、樹脂絶縁層２１，２６を貼り付ける。そして、例えばエキシマレーザーやＵＶレーザーやＣＯ２レーザーなどを用いてレーザー加工を施すことによって樹脂絶縁層２１，２６の所定の位置にビア穴３３を形成する（図６参照）。次いで、過マンガン酸カリウム溶液などのエッチング液を用いて各ビア穴３３内のスミアを除去するデスミア工程を行う。なお、デスミア工程としては、エッチング液を用いた処理以外に、例えばＯ２プラズマによるプラズマアッシングの処理を行ってもよい。　
デスミア工程の後、従来公知の手法に従って無電解銅めっき及び電解銅めっきを行うことで、各ビア穴３３内にビア導体３４を形成する。さらに、従来公知の手法（例えばセミアディティブ法）によってエッチングを行うことで、樹脂絶縁層２１，２６上に導体層２４をパターン形成する（図７参照）。
他の樹脂絶縁層２２，２７及び導体層２４についても、上述した樹脂絶縁層２１，２６及び導体層２４と同様の手法によって形成し、樹脂絶縁層２１，２６上に積層していく。なおここで、樹脂絶縁層２２上の導体層２４として、複数の接続端子部４１を有する露出配線導体６１、非露出配線導体６２がそれぞれ形成される（図８参照：導体層形成工程）。また、樹脂絶縁層２７上の導体層２４として、複数の外部接続端子４５が形成される。　
次に、樹脂絶縁層２２上に後にソルダーレジスト層２３となる感光性樹脂絶縁材料を塗布して硬化させ、露出配線導体６１及び非露出配線導体６２を全体的に被覆する樹脂絶縁材料層６６を形成する（図９参照）。ここでは、感光性樹脂絶縁材料として、例えば感光性エポキシ樹脂を主体とするソルダーレジスト材料が選択される。この場合、ソルダーレジスト材料は塗布可能な液状物であってもよく、貼着可能なフィルム状物であってもよい。フィルム状のソルダーレジスト材を使用する場合、表面の平坦性を確保すべく、貼着後のソルダーレジスト材をその厚さ方向にプレスした後で露光及び現像を行うことが好ましい。　
次に、樹脂絶縁材料層６６上に、ガラス基板の所定箇所に光通過部８２が形成されたフォトマスク８１を配置する。この状態でフォトマスク８１を介して紫外線８３を従来の通常の条件にて照射することにより、樹脂絶縁材料層６６に対する部分的な露光を行う（図１０参照）。この露光により、フォトマスク８１の光通過部８２の直下となる領域に紫外線８３が当たり、樹脂絶縁材料層６６における当該領域が選択的に感光する。図１０では、後にダム部６３等となる露光部８４を破線で示している。上記条件にて露光を行った場合、紫外線８３が樹脂絶縁材料層６６の深部まで十分に届かず、露光部８４のパターン底部に露光不良部位８５が発生している可能がある。　
この後、未露光部分について３μｍ～１２μｍ程度の厚さ分を残すような条件を設定し、専用の現像液を用いて樹脂絶縁材料層６６を現像する（図１１参照）。この現像により、最表層の樹脂絶縁層であるソルダーレジスト層２３を形成するとともに、そのソルダーレジスト層２３の一部をなすダム部６３及び補強部６４を一体的に形成する（樹脂絶縁層形成工程）。そして、さらに熱や紫外線にてソルダーレジスト層２３、ダム部６３及び補強部６４をキュアした後（図１２参照）、露出配線導体６１にニッケル－金めっき等の最表面処理を行う。以上のような工程を経ることで、微細なダム部６３及びそれに連結される補強部６４を有するオーガニック配線基板１０が完成する。　
従って、本実施の形態によれば以下の効果を得ることができる。　
（１）本実施形態のオーガニック配線基板１０は、上記のようにダム部６３と補強部６４とを有したものとなっている。従って、ソルダーレジスト層２３の一部として微細なダム部６３を形成したときでも、その側面に補強部６４が連結されている。このため、本来アンダーカットが発生しやすいダム部６３の底部が補強される。よって、微細かつ強固なダム部６３を得ることができ、複数の接続端子部４１間を通過して配設された非露出配線導体６２がそのダム部６３により確実に保護される。その結果、ダム部６３の剥離やダム部６３からの非露出配線導体６２の露出といった事態が回避される。また、補強部６４はダム部６３の高さＨ３よりも低く形成されているため、補強部６４が半導体チップ５１側の接続端子５２に当たることが回避される。以上のことから、半導体チップ５１側の接続端子５２と接続端子部４１とをはんだバンプ５３を介して確実に接続可能となり、半導体チップ５１との接続信頼性に優れたオーガニック配線基板１０を得ることができる。　
（２）本実施形態のオーガニック配線基板１０では、補強部６４が非露出配線導体６２とそれに隣接する接続端子部４１との間を完全に埋めている。この構成によれば、非露出配線導体６２及びダム部６３の長手方向と直交する方向（即ち図１～図３の左右方向）に沿って、補強部６４がある程度長くなる。ゆえに、補強部６４とそれを支持する樹脂絶縁層２２との接触面積も大きくなる。よって、ダム部６３が確実に補強され、ダム部６３が安定するという利点がある。従って、ダム部６３の剥離やダム部６３からの非露出配線導体６２の露出といった事態をより確実に回避することができ、ひいては半導体チップ５１との接続信頼性をいっそう向上させることができる。　
（３）本実施形態のオーガニック配線基板１０では、補強部６４の高さＨ１が複数の接続端子部４１の高さＨ２より低くなっている。その結果、複数の接続端子部４１の表面及び側面の上側部分が補強部６４から露出している。この構成であると、補強部６４が非露出配線導体６２と接続端子部４１との間を完全に埋めていたとしても、接続端子部４１における３つの面が露出した状態となる。そのため、複数の接続端子部４１とはんだ等の導電金属材料との接触面積が大きくなる。よって、接続端子部４１と半導体チップ５１側の接続端子５２とがより確実に接続され、ひいては半導体チップ５１との接続信頼性をいっそう向上させることができる。　
（４）本実施形態のオーガニック配線基板１０では、ダム部６３及び補強部６４が共通のソルダーレジスト材料からなり一体形成されている。そして、このように一体形成された構造であると、ダム部６３と補強部６４との連結部分の強度が上がり、ダム部６３をより確実に補強することができる。また、この構造によれば、ダム部６３と補強部６４とをそれぞれ異なるソルダーレジスト材料を用いて形成する構造とは異なり、製造コストの低減及び製造工程の簡略化を図りやすくなる。　
（５）本実施形態では、上記のような導体層形成工程及び樹脂絶縁層形成工程を経て、所望のオーガニック配線基板１０を製造している。

即ち、樹脂絶縁層形成工程において、ソルダーレジスト層２３が形成されるときに、併せて非露出配線導体６２を被覆するダム部６３と、その側面に連結する補強部６４とが一体的に形成される。

ゆえに、微細なダム部６３を形成したときでも、その側面に補強部６４が連結されているため、本来アンダーカットが発生しやすいダム部６３の底部が補強される。

よって、微細かつ強固なダム部６３を比較的容易にかつ確実に得ることができる。

また、本実施形態の製造方法によれば、アンダーカットを回避するための対策を講じる必要がなくなる。

それゆえ、高露光量に起因するハレーションの発生や、短時間現像に起因する樹脂残りの発生といった事態が回避され、結果的に接続不良が起こるリスクが低減される。

よって、半導体チップ５１との接続信頼性に優れたオーガニック配線基板１０を比較的容易にかつ確実に製造することができる。　
なお、本発明の実施の形態は以下のように変更してもよい。　
・上記実施形態では、補強部６４の高さが接続端子部４１の高さより低く、接続端子部４１の表面及び側面の上側部分が補強部６４から露出していたが、例えば図１３に示す別の実施形態のオーガニック配線基板１０Ａのような構成としてもよい。即ち、このオーガニック配線基板１０Ａでは、補強部６４の高さが接続端子部４１の高さと等しく、接続端子部４１の表面のみ補強部６４から露出した状態となっている。　
・上記実施形態では、補強部６４が、樹脂絶縁層２２の表面上において非露出配線導体６２と接続端子部４１との間を完全に埋めるように形成したが、例えば図１４に示す別の実施形態のオーガニック配線基板１０Ｂのように完全には埋めない構成を採用してもよい。即ち、このオーガニック配線基板１０Ｂでは、補強部６４の側面が接続端子部４１の側面に対して接していない。　
・上記実施形態においてダム部６３及び補強部６４は、共通のソルダーレジスト材により形成されていたが、互いに別々の樹脂絶縁材料層６６を用いて形成されていてもよい。　
・上記実施形態では、樹脂絶縁層２２の表面に感光性を有する樹脂絶縁材を設けた後、部分的な露光及び現像を行うことで、ソルダーレジスト層２３を形成するとともに、ダム部６３及び補強部６４を一体形成していた。しかしながら、最表層の樹脂絶縁層２３の形成方法は適宜変更することができる。例えば、樹脂絶縁層２２の表面に熱硬化性の樹脂絶縁層２３を塗布して熱硬化させた後、各接続端子部４１の表面が露出するまで機械的に研磨するという手法を採用してもよい。この場合、機械的な研磨に代えて、サンドブラスト処理などの砥粒加工を採用してもよいほか、ドライエッチング処理を採用してもよい。　
・上記実施の形態のオーガニック配線基板１０は、コア基板１３を有する配線基板であったが、これに限定されるものではなく、コアを有さないコアレス配線基板に本発明を適用させてもよい。　
・上記実施の形態におけるオーガニック配線基板１０の形態は、ＢＧＡ（ボールグリッドアレイ）であるが、ＢＧＡのみに限定されず、例えばＰＧＡ（ピングリッドアレイ）やＬＧＡ（ランドグリッドアレイ）等の配線基板に本発明を適用させてもよい。
１０，１０Ａ，１０Ｂ…配線基板

　２１，２２，２３，２６，２７，２８…樹脂絶縁層

　２３…最表層の樹脂絶縁層としてのソルダーレジスト層

　２４…導体層

　３１…積層体としての第１ビルドアップ層

　３２…積層体としての第２ビルドアップ層

　４１…接続端子部

　５１…半導体チップ

　５４…搭載領域

　６１…（露出）配線導体

　６２…（非露出）配線導体

　６３…ダム部

　６４…補強部

　６６…樹脂絶縁材料

　Ｈ１…補強部の高さ

　Ｈ２…接続端子部の高さ

　Ｈ３…ダム部の高さ

Claims (5)

  1. 樹脂絶縁層及び導体層がそれぞれ１層以上積層された積層体を有し、前記積層体の最表層の前記導体層が、半導体チップをフリップチップ実装するために前記半導体チップの搭載領域にて配列されて表面に露出する複数の接続端子部と、前記複数の接続端子部間に配設された配線導体とを含む配線基板において、

    　前記積層体の最表層の前記樹脂絶縁層は、前記配線導体を被覆するダム部と、前記配線導体とそれに隣接する接続端子部との間にて前記ダム部の高さよりも低く形成され、前記ダム部の側面に連結された補強部とを有する

    ことを特徴とする配線基板。
  2. 前記補強部は、前記配線導体とそれに隣接する接続端子部との間を埋めていることを特徴とする請求項１に記載の配線基板。
  3. 前記補強部の高さは前記複数の接続端子部の高さより低く、前記複数の接続端子部の表面及び側面の上側部分は前記補強部から露出していることを特徴とする請求項２に記載の配線基板。
  4. 前記ダム部及び前記補強部は、共通のソルダーレジスト材料からなり一体形成されていることを特徴とする請求項１乃至３のいずれか１項に記載の配線基板。
  5. 請求項１乃至４のいずれか１項に記載の配線基板の製造方法であって、

    　前記半導体チップの搭載領域に前記複数の接続端子部及び前記配線導体を形成する導体層形成工程と、

    　前記複数の接続端子部及び前記配線導体を覆うような状態で最表層の前記樹脂絶縁層となる感光性を有する樹脂絶縁材料をそれらの上に配置し、前記樹脂絶縁材料に対する部分的な露光及び現像を行うことにより、最表層の前記樹脂絶縁層を形成するとともに、前記ダム部及び前記補強部を一体的に形成する樹脂絶縁層形成工程と

    を含むことを特徴とする配線基板の製造方法。
PCT/JP2013/003342 2012-11-07 2013-05-27 配線基板及びその製造方法 WO2014073128A1 (ja)

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US14/237,065 US9420703B2 (en) 2012-11-07 2013-05-27 Wiring board and manufacturing method of the same
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US9420703B2 (en) 2016-08-16
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