JP2015026775A - 配線基板 - Google Patents
配線基板 Download PDFInfo
- Publication number
- JP2015026775A JP2015026775A JP2013156676A JP2013156676A JP2015026775A JP 2015026775 A JP2015026775 A JP 2015026775A JP 2013156676 A JP2013156676 A JP 2013156676A JP 2013156676 A JP2013156676 A JP 2013156676A JP 2015026775 A JP2015026775 A JP 2015026775A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- strip
- parallel
- solder resist
- resist layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims abstract description 69
- 239000004065 semiconductor Substances 0.000 claims abstract description 46
- 229910000679 solder Inorganic materials 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000000151 deposition Methods 0.000 claims description 2
- 229920005989 resin Polymers 0.000 description 18
- 239000011347 resin Substances 0.000 description 18
- 238000000034 method Methods 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 229920001187 thermosetting polymer Polymers 0.000 description 4
- 239000000654 additive Substances 0.000 description 3
- 239000012777 electrically insulating material Substances 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
【解決手段】複数の帯状配線導体6が並設された絶縁基板1上に、各帯状配線導体6の一部を半導体素子接続パッド部7として個別に露出させる開口部9を、互いに隣接する帯状配線導体6に対して千鳥状の配列で有するソルダーレジスト層3が被着されて成る配線基板100であって、帯状配線導体6の少なくとも一部は、互いに隣接する帯状配線導体6の半導体素子接続パッド部7と並行する並行部8をソルダーレジスト層3で覆われた状態で有し、かつ並行部8の側面から隣接する開口部9までのソルダーレジスト層3の厚みTが10μm以上となるように並行部8の幅が細められている。
【選択図】図2
Description
2 配線導体
3 ソルダーレジスト層
6 帯状配線導体
7 半導体素子接続パッド部
8 並行部
9 ソルダーレジスト層の開口
S 半導体素子
T 半導体素子の電極端子
Claims (2)
- 絶縁基板上に半導体素子接続用の複数の帯状配線導体が並設されており、かつ前記絶縁基板上および前記帯状配線導体上に、各前記帯状配線導体の一部を半導体素子接続パッド部として個別に露出させる開口部を、互いに隣接する前記帯状配線導体に対して千鳥状の配列で有するソルダーレジスト層が被着されて成る配線基板であって、前記帯状配線導体の少なくとも一部は、互いに隣接する前記帯状配線導体の前記半導体素子接続パッド部と並行する並行部を前記ソルダーレジスト層で覆われた状態で前記開口部に隣接して有し、該並行部から隣接する前記開口部までの前記ソルダーレジスト層の厚みが10μm以下となるように前記並行部の幅が細められていることを特徴とする配線基板。
- 前記開口部は、前記半導体素子接続パッドを横切る方向の側壁の断面形状が該開口部の内側に3μm以下膨出する鼓形状をしていることを特徴とする請求項1記載の配線基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013156676A JP6121831B2 (ja) | 2013-07-29 | 2013-07-29 | 配線基板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013156676A JP6121831B2 (ja) | 2013-07-29 | 2013-07-29 | 配線基板 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016212781A Division JP6259045B2 (ja) | 2016-10-31 | 2016-10-31 | 配線基板の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2015026775A true JP2015026775A (ja) | 2015-02-05 |
JP6121831B2 JP6121831B2 (ja) | 2017-04-26 |
Family
ID=52491189
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013156676A Expired - Fee Related JP6121831B2 (ja) | 2013-07-29 | 2013-07-29 | 配線基板 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP6121831B2 (ja) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0718467U (ja) * | 1993-09-03 | 1995-03-31 | 株式会社ピーエフユー | プリント配線板 |
JP2007335803A (ja) * | 2006-06-19 | 2007-12-27 | Toppan Printing Co Ltd | 配線基板の製造方法 |
-
2013
- 2013-07-29 JP JP2013156676A patent/JP6121831B2/ja not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0718467U (ja) * | 1993-09-03 | 1995-03-31 | 株式会社ピーエフユー | プリント配線板 |
JP2007335803A (ja) * | 2006-06-19 | 2007-12-27 | Toppan Printing Co Ltd | 配線基板の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP6121831B2 (ja) | 2017-04-26 |
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