CN103227202A - FinFET体接触件及其制造方法 - Google Patents
FinFET体接触件及其制造方法 Download PDFInfo
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- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
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Abstract
一种半导体器件可以包括用于ESD保护的位于finFET器件上的体接触件。半导体器件包括半导体鳍状件、源极/漏极区和体接触件。源极/漏极区和体接触件位于半导体鳍状件中。鳍状件的一部分在横向上位于源极/漏极区和体接触件之间。半导体鳍状件位于衬底上。本发明还提供了一种FinFET体接触件及其制造方法。
Description
技术领域
本发明涉及半导体领域,更具体地,本发明涉及一种FinFET体接触件及其制造方法。
背景技术
晶体管是现代集成电路的关键组件。为了满足日益增加的更快速度的要求,晶体管的驱动电流需要日益增大。由于晶体管的驱动电流与晶体管的栅极宽度成比例,优选具有较大宽度的晶体管。
然而,栅极宽度的增加与减小半导体器件的尺寸的要求冲突。从而,开发了鳍状件场效应晶体管(finFET)。
finFET的引入具有增加驱动电流而不以占用更多芯片面积为代价的有利特征。然而,finFET晶体管产生关于静电放电(ESD)性能的大量问题。
发明内容
为了解决现有技术中所存在的问题,根据本发明的一个方面,提供了一种半导体器件,包括:衬底;位于所述衬底之上凸起的鳍状件;所述鳍状件包括:所述鳍状件中的第一源极/漏极区;所述鳍状件中的第一体接触件;以及所述鳍状件的第一部分,所述第一部分在横向上位于所述第一源极/漏极区和所述第一体接触件之间。
在该半导体器件中,所述第一部分仅包括鳍状件材料。
在该半导体器件中,所述鳍状件包含第一导电类型的掺杂物,所述第一源极/漏极区包含第二导电类型的掺杂物,所述第一体接触件包含所述第一导电类型的掺杂物。
在该半导体器件中,所述第一导电类型是p型,并且所述第二导电类型是n型。
在该半导体器件中,所述鳍状件进一步包括:位于所述鳍状件上方的第一栅极结构,其中,所述第一栅极结构直接位于所述鳍状件的所述第一部分的上方。
在该半导体器件中,所述鳍状件进一步包括:所述鳍状件中的第二源极/漏极区,所述第二源极/漏极区在与所述第一体接触件相反的方向上与所述第一源极/漏极区分横向隔开;以及位于所述鳍状件上方的第二栅极结构,其中,所述第二栅极结构在横向上位于所述第一源极/漏极区和所述第二源极/漏极区之间。
在该半导体器件中,所述鳍状件进一步包括:所述鳍状件中的第三源极/漏极区,所述第三源极/漏极区在与所述第一源极/漏极区相反的方向上与所述第二源极/漏极区分横向隔开;位于所述鳍状件上方的第三栅极结构,其中,所述第三栅极结构在横向上位于所述第二源极/漏极区和所述第三源极/漏极区之间;所述鳍状件中的第二体接触件;所述鳍状件的第二部分,所述第二部分在横向上位于所述第三源极/漏极区和所述第二体接触件之间;以及位于所述鳍状件上方的第四栅极结构,其中,所述第四栅极结构直接位于所述鳍状件的第二部分的上方。
在该半导体器件中,所述鳍状件进一步包括:所述鳍状件中的第一隔离区,其中,所述第一隔离区邻近所述鳍状件的所述第一部分的相对侧上的所述第一体接触件;位于所述鳍状件上方的第五栅极结构,其中,所述第五栅极结构部分位于所述第一体接触件的上方并且部分位于所述第一隔离区的上方;所述鳍状件中的第二隔离区,其中,所述第二隔离区邻近所述鳍状件的所述第二部分的相对侧上的所述第二体接触件;以及位于所述鳍状件上方的第六栅极结构,其中,所述第六栅极结构部分位于所述第二体接触件的上方并且部分位于所述第二隔离区的上方。
在该半导体器件中,所述第一栅极结构、所述第四栅极结构、所述第五栅极结构和所述第六栅极结构是伪栅极结构。
根据本发明的另一方面,提供了一种半导体器件,包括:衬底;从所述衬底延伸的第一半导体鳍状件,其中,所述第一半导体鳍状件包括:所述第一半导体鳍状件中的第一源极/漏极区;所述第一半导体鳍状件中的第二源极/漏极区;第一栅极结构,位于所述第一半导体鳍状件的顶面和侧壁上,其中,所述第一栅极结构在横向上位于所述第一源极/漏极区和所述第二源极/漏极区之间;第一体接触件,位于所述第一半导体鳍状件中;以及第二栅极结构,位于所述第一半导体鳍状件的顶面和侧壁上,其中,所述第二栅极结构在横向上位于所述第一源极/漏极区和所述第一体接触件之间。
在该半导体器件中,所述第一半导体鳍状件包含第一导电类型的掺杂物,所述第一源极/漏极区和所述第二源极/漏极区包含第二导电类型的掺杂物,并且所述第一体接触件包含所述第一导电类型的掺杂物。
在该半导体器件中,所述第一导电类型是p型,并且所述第二导电类型是n型。
在该半导体器件中,所述第一半导体鳍状件进一步包括:所述鳍状件中的第二体接触件;以及第三栅极结构,位于所述鳍状件的顶面和侧壁上,其中,所述第三栅极结构横向隔离所述第二源极/漏极区和所述第二体接触件。
在该半导体器件中,所述第一半导体鳍状件进一步包括:所述鳍状件中的第一隔离区,其中,所述第一隔离区邻近所述第一源极/漏极区的相对侧上的所述第一体接触件;位于所述鳍状件上方的第四栅极结构,其中,所述第四栅极结构部分位于所述第一体接触件的上方并且部分位于所述第一隔离区的上方;所述鳍状件中的第二隔离区,其中,所述第二隔离区邻近所述第二源/漏极区的相对侧上的所述第二体接触件;以及位于所述鳍状件上方的第五栅极结构,其中,所述第五栅极结构部分位于所述第二体接触件的上方并且部分位于所述第二隔离区的上方。
在该半导体器件中,所述第二栅极结构、所述第三栅极结构、所述第四栅极结构和所述第五栅极结构是伪栅极结构。
在该半导体器件中,所述半导体器件进一步包括:所述衬底中的第三体接触件,其中,所述第三体接触件在横向上与所述第一半导体鳍状件分隔开并且平行于所述第一半导体鳍状件;以及所述衬底中的第三隔离区,其中,所述第三隔离区在横向上位于所述第一半导体鳍状件和所述第三体接触件之间。
在该半导体器件中,所述半导体器件进一步包括:从所述衬底延伸的第二半导体鳍状件,其中,所述第二半导体鳍状件在与所述第三体接触件相反的方向上与所述第一半导体鳍状件横向分隔开,所述第二半导体鳍状件平行于所述第一半导体鳍状件,并且所述第一栅极结构、所述第二栅极结构、所述第三栅极结构、所述第四栅极结构和所述第五栅极结构位于所述第二半导体鳍状件的顶面和侧壁上;从所述衬底延伸的第三半导体鳍状件,其中,所述第三半导体鳍状件在与所述第一半导体鳍状件相反的方向上与所述第二半导体鳍状件横向分隔开,所述第三半导体鳍状件平行于所述第二半导体鳍状件,并且所述第一栅极结构、所述第二栅极结构、所述第三栅极结构、所述第四栅极结构和所述第五栅极结构位于所述第三半导体鳍状件的顶面和侧壁上;从所述衬底延伸的第四半导体鳍状件,其中,所述第四半导体鳍状件在与所述第二半导体鳍状件相反的方向上与所述第三半导体鳍状件横向分隔开,所述第四半导体鳍状件平行于所述第三半导体鳍状件,并且所述第一栅极结构、所述第二栅极结构、所述第三栅极结构、所述第四栅极结构和所述第五栅极结构位于所述第四半导体鳍状件的顶面和侧壁上;从所述衬底延伸的第五半导体鳍状件,其中,所述第五半导体鳍状件在与所述第三半导体鳍状件相反的方向上与所述第四半导体鳍状件横向分隔开,所述第五半导体鳍状件平行于所述第四半导体鳍状件,并且所述第一栅极结构、所述第二栅极结构、所述第三栅极结构、所述第四栅极结构和所述第五栅极结构位于所述第五半导体鳍状件的顶面和侧壁上;所述衬底中的第四体接触件,其中,所述第四体接触件在横向上与所述第五半导体鳍状件分隔开并且平行于所述第五半导体鳍状件;以及所述衬底中的第四隔离区,其中,所述第四隔离区在横向上位于所述第五半导体鳍状件和所述第四体接触件之间。
根据本发明的又一方面,提供了一种形成半导体结构的方法,所述方法包括:在衬底上形成半导体鳍状件;在所述半导体鳍状件的顶面和侧壁上形成第一栅极结构;在所述半导体鳍状件的顶面和侧壁上形成第二栅极结构,其中,所述第二栅极结构在横向上与所述第一栅极结构分隔开;在所述半导体鳍状件的顶面和侧壁上形成第三栅极结构,其中,所述第三栅极结构在与所述第二栅极结构相反的方向上与所述第一栅极结构横向分隔开;在所述半导体鳍状件中形成第一源极/漏极区,其中,所述第一源极/漏极区在横向上位于所述第一栅极结构和所述第二栅极结构之间;在所述半导体鳍状件中形成第二源极/漏极区,其中,所述第二源极/漏极区在横向上位于所述第一栅极结构和所述第三栅极结构之间;以及在所述半导体鳍状件中形成第一体接触件,其中,所述第一体接触件在横向上与第一源极/漏极区分隔开,并且所述第二栅极结构在横向上位于所述第一源极/漏极区和所述第一体接触件之间。
在该方法中,形成所述第一源极/漏极区包括:图案化所述半导体鳍状件,以形成第一凹部;以及在所述第一凹部中外延生长所述第一源极/漏极区。
在该方法中,形成所述半导体结构进一步包括:在所述半导体鳍状件中形成第二体接触件,其中,所述第二体接触件在横向上与第二源极/漏极区分隔开,并且所述第三栅极结构在横向上位于所述第二源/漏极区和所述第二体接触件之间。
附图说明
为了全面理解本公开及其优点,现在结合附图进行以下描述作为参考,其中:
图1A和图1B分别在立体图和横截面图中示出根据实施例的finFET;
图2A至图8示出图1A和图1B中所示的结构的制造的步骤;
图9在横截面图中示出finFET器件结构的第二示意性实施例;以及
图10A和图10B分别在俯视图和横截面图中示出finFET器件结构的第二示意性实施例。
具体实施方式
将参考图2A至图8描述形成鳍状件器件的多个步骤。现在对附图中所示的实施例详细地作出参考。当可能时,在图和说明书中使用相同参考数字,以指示相同或类似部分。在图中,为了清楚和方便起见,形状和厚度可以被放大。该说明将特别用于形成根据本发明的方法和装置的部件或者与其更直接结合的元件。将理解,未特别示出或描述的元件可以采用本领域技术人员熟知的多种形式。一旦由本发明进行了说明,多种改变和修改对于本领域技术人员来说是显而易见的。
贯穿本说明书,“一个实施例”或“一实施例”的参考意味着,结合实施例描述的特定特征、结构或特性包括在至少一个实施例中。从而,贯穿本说明书,在多个地方出现的短语“在一个实施例中”或“在一实施例中”不必须所有都指相同实施例。而且,特定特征、结构或特性可以以任何合适方式结合在一个或多个实施例中。将想到,以下图不按比例绘制,而是,这些图仅用于说明。
图1A示出finFET器件50的立体图,其包括衬底110、衬底110之上的鳍状件120、围绕鳍状件120的隔离区130、鳍状件120之上的栅极180、源极/漏极区140、以及体接触件150。在一个实施例中,衬底110可以是体衬底(bulk substrate),诸如在CMOS制造处理中通常采用的体硅晶圆。可替换地,衬底110可以是化合物衬底(诸如,绝缘体上硅(SOI)衬底)、或由诸如锗、砷化镓、III-V材料等的其他材料形成的另一个体衬底或化合物半导体衬底。在图中仅示出衬底110的一部分,这足以充分描述示意性实施例。
鳍状件120被形成为在衬底110之上延伸的垂直硅鳍状件,并且被用于形成源极/漏极区140、源极和漏极区之间的沟道区(未示出)、以及体接触件150。栅极介电层(未示出)可以在沟道区中形成。然后,栅极180围绕鳍状件120形成并且围绕沟道区中的鳍状件120。FinFET器件150还可以包括在鳍状件120之上的四个伪栅极182(为了清楚起见,在图1A中未示出),两个伪栅极182在栅极180的每一侧上。
隔离区130可以是浅沟槽隔离(STI)区,并且可以通过蚀刻衬底110以形成沟槽并且用介电材料填充沟槽形成。根据一个实施例,隔离区可以用介电材料填充,诸如,氧化物材料、高密度等离子体(HDP)氧化物等。
图1B是从沿着图1的X-X线的Z平面的finFET器件50的实施例的横截面图。图1B示出finFET器件50的实施例,其包括栅极180和在鳍状件120之上的四个伪栅极182,每个栅极都包括栅极和鳍状件120之间的介电层170和栅极的两侧上的栅极隔离结构190。在可选实施例中,鳍状件材料是掺杂有合适掺杂杂质的硅。在栅极180的每侧上存在两个伪栅极182。最接近栅极180的两个伪栅极182可以用于源极/漏极区140和体接触件150的自对准掺杂物注入。源极/漏极区140被掺杂,以使鳍状件120的这些部分导电。体接触件150也被掺杂,以使鳍状件120的这些部分导电,但是它们可以通过与源极/漏极区140相反的导电类型被掺杂。例如,如果源极/漏极区140被掺杂有n型掺杂物,体接触件150可以掺杂有p型掺杂物。在另一个实施例中,源极/漏极区140和体接触件150可以通过首先形成凹部并且然后通过选择性外延生长(SEG)外延生长源极/漏极区140和体接触件150形成。在一个实施例中,可以采用非选择性外延生长。源极/漏极区140和体接触件150可以通过下述注入方法或者通过随着材料生长进行原位掺杂而被掺杂。源极/漏极区140和体接触件150可以包括电极层160。电极层160可以包括导电材料,并且可以选自包括多晶硅(poly-Si)、多晶硅锗(poly-SiGe)、金属氮化物、金属硅化物、金属氧化物、以及金属的组。
外侧伪栅极182可以部分位于隔离区130上并且部分位于体接触件150上。在另一个实施例中,外侧伪栅极182可以整体位于隔离区130上。在又一个实施例中,外侧伪栅极182可以整体位于体接触件150上。四个伪栅极182可以用于提供诸如化学机械抛光(CMP)的栅极的平坦化处理的更均匀密度。
图2A至图8示出根据一个实施例的形成finFET器件的工艺。附图是从沿着图1中的Y-Y线或X-X线的Z平面的横截面图。每个附图都显示横截面图来源于的轴。虽然本实施例通过以特定顺序执行的步骤论述,但是步骤可以以任何逻辑顺序执行。
图2A和图2B示出在处理期间的一些点处的finFET器件。器件包括衬底110上的半导体层210。如上所述,半导体层210可以包括体硅或绝缘体上硅(SOI)衬底的有源层。半导体层210可以通过注入处理220被掺杂,以将p型或n型杂质引入半导体层210中。
在图3A和图3B中,鳍状件120通过图案化半导体层210形成。鳍状件图案化工艺可以通过在半导体层210之上沉积诸如光刻胶或氧化硅的通用掩模材料(未示出)实现。然后,掩模材料被图案化,并且半导体层210根据图案被蚀刻。以此方式,可以形成在衬底之上的半导体鳍状件的半导体结构。如图3B中所示,鳍状件120沿着图1的线X-X延伸。在可选实施例中,鳍状件120可以在图案化层顶部衬底110中形成的沟槽或开口内从衬底110的顶面外延生长。由于该工艺在本领域中已知,所以在此不再重复详情。在一个实施例中,如图3A和图3B中所示,鳍状件120可以具有约2nm和20nm之间的宽度320和7nm和50nm之间的高度310。
图4A和图4B示出栅极介电层170的形成。栅极介电层170可以通过热氧化、CVD、溅射、或本领域中已知和使用的用于形成栅极电介质的任何其他方法形成。在其他实施例中,栅极介电层170包括具有高介电常数(k值)的介电材料,例如,大于3.9。材料可以包括氮化硅、氮氧化物、诸如HfO2、HfZrOx、HfSiOx、HfTiOx、HfAlOx等的金属氧化物、以及其结合和多层。在另一个实施例中,栅极介电层170可以具有选自诸如氮化钛、氮化钽、或氮化钼的金属氮化物材料的覆盖层,厚度从1nm到20nm。
在图5A和图5B中,栅电极层510可以形成在栅极介电层170上方。栅电极层510可以包括导电材料并且可以选自由多晶硅(poly-Si)、多晶硅-锗(poly-SiGe)、金属氮化物、金属硅化物、金属氧化物、以及金属的组。金属氮化物的实例包括氮化钨、氮化钼、氮化钛、以及氮化钽、或其组合。金属硅化物的实例包括硅化钨、硅化钛、硅化钴、硅化镍、硅化铂、硅化铒、或其组合。金属氧化物的实例包括氧化钌、氧化铟锡、或其组合。金属的实例包括钨、钛、铝、铜、钼、镍、铂等。
栅电极层510可以通过CVD、溅射沉积、或本领域中已知并且使用用于沉积导电材料的其他技术来沉积。栅电极层510的厚度可以在约200埃至约4000埃的范围内。栅电极层510的顶面通常具有非平坦顶面,并且可以在栅电极层510的图案化或栅极蚀刻之前被平坦化。这里,离子可以引入或可以不被引入到栅电极层510中。离子可以例如通过离子注入技术被引入。
图6示出栅电极层510和栅电极层170的图案化,以形成栅极180和伪栅极182。栅极可以通过使用例如本领域中已知的沉积和光刻技术在栅电极层510上沉积和图案化栅极掩模(未示出)形成。栅极掩模可以结合通常使用的掩模材料(masking material),诸如(但不限于)光刻材料、氧化硅、氮氧化硅、和/或氮化硅。栅电极层510和栅极介电层170可以使用等离子体蚀刻被蚀刻,以形成如图6中所示的经过图案化的栅极。在另一个实施例中,不形成外侧伪栅极182,而是仅形成源极/漏极区140和体接触件150之间的伪栅极182。
在图7中,示出源极/漏极区140和体接触件150的形成。源极/漏极区140和体接触件150可以通过执行注入处理710以注入合适掺杂物而被掺杂,以补充鳍状件120中的掺杂物。在一个实施例中,鳍状件120被注入(如以上参考图2A和图2B论述的)p型掺杂物,诸如硼、镓、铟等,源极/漏极区被注入n型掺杂物,诸如磷、砷、锑等,体接触件150被注入p型掺杂物。源极/漏极区140使用栅极180作为掩模被注入,并且体接触件150使用伪栅极182作为掩模被注入。在一些实施例中,经过掺杂的源极/漏极区140和经过掺杂的体接触件150可以被退火,以促进掺杂杂质到鳍状件120的扩散。在一个实施例中,如图7中所示,源极/漏极区140和最接近的体接触件150可以具有约80nm和400nm之间的距离720。
体接触件150有助于提供用于源极/漏极区140的静电放电(ESD)保护。当体接触件150被p型掺杂并且源极/漏极区140被n型掺杂时,在源极/漏极区140和最接近的体接触件150之间的鳍状件120区域中形成pn结。该pn结形成从体接触件150到源极/漏极区140的寄生体二极管,其允许体接触件150通过低导通电阻执行ESD保护。体接触件150可以连接至ESD放电电路,诸如,接地或电源电压。例如,在示意性实施例中,鳍状件120被p型掺杂,源极/漏极区140被n型掺杂,体接触件150被p型掺杂,并且源极/漏极区140和体接触件150之间的距离720(参见图7)约为200nm。如本领域技术人员能想到的,距离720可以根据器件的技术节点和电路的要求而改变。
在另一个实施例中,源极/漏极区140和体接触件150可以通过在鳍状件120中形成凹部(未示出)并且在凹部中外延生长材料形成。在一个实施例中,凹部可以通过各向异性蚀刻形成。可选地,凹部可以通过各向同性定向依赖性蚀刻工艺(isotropic orientation dependent etching process)形成,其中,四甲基氢氧化铵(TMAH)等可以被用作蚀刻剂。在形成凹部之后,源极/漏极区140和体接触件150可以通过在凹部中外延生长材料形成。在外延工艺期间,诸如HCl气体的蚀刻气体可以被添加(作为蚀刻气体)到工艺气体中,使得源极/漏极区140和体接触件150在凹部中但不在栅极上被选择性地生长。在可选实施例中,不添加蚀刻气体,或者蚀刻气体的量很小,使得存在源极/漏极区140的薄层和形成在衬底栅极上的体接触件150。在又一个实施例中,栅极180和伪栅极182可以用牺牲层(sacrificial layer,未示出)覆盖,以防止在其上外延生长。源极/漏极区140和体接触件150可以通过如上所述的注入方法或者通过随着生长材料进行原位掺杂而被掺杂。
源极/漏极区140和体接触件150的形成方法可以包括原子层沉积(ALD)、化学汽相沉积(CVD),诸如减压CVD(RPCVD)、有机金属化学汽相沉积(MOCVD)、或其他可应用方法。根据源极/漏极区140和体接触件150的期望成分,用于外延的前体可以包括含Si气体和含Ge气体,诸如,SiH4和GeH4等,并且含Si气体和含Ge气体的部分压力被调节,以修改锗与硅的原子比率。
在另一个实施例中,源极/漏极区140被形成,以在栅极180下面的沟道区上施加应变。在鳍状件120包括硅的实施例中,然后,源极/漏极区140可以通过诸如硅锗、碳化硅等具有不同于硅的晶格常数的材料经由SEG工艺形成。应激源材料源极/漏极区140和栅极180下面形成的沟道区之间的晶格错位将应力施加到沟道区中,这将增加载流子移动性和器件的整体性能。源极/漏极区140可以通过上述注入方法或者通过随着生长材料进行原位掺杂而被掺杂。
图8示出在栅极的相对侧上的栅极隔离结构190的形成和电极层160的形成。栅极隔离结构190通常通过在先前形成的结构中覆盖沉积隔离结构层(未示出)形成。隔离结构层可以包括SiN、氮氧化物、SiC、SiON、氧化物等形成,并且可以通过用于形成这样的层的方法形成,诸如,化学汽相沉积(CVD)、等离子体增强CVD、溅射、以及本领域中已知的其他方法。然后,栅极隔离结构190优选通过各向异性蚀刻被图案化,以从结构的水平面去除隔离结构层。
电极层160可以包括导电材料,并且可以选自包括多晶硅(poly-Si)、多晶硅锗(poly-SiGe)、金属氮化物、金属硅化物、金属氧化物、以及金属的组。电极层160可以通过CVD、溅射沉积、或用于沉积导电材料的本领域中已知和使用的其他技术进行沉积。
在另一个实施例中,源极/漏极区140可以包括轻掺杂区和重掺杂区。在该实施例中,在形成栅极隔离结构190之前,源极/漏极区140可以被轻掺杂。在形成栅极隔离结构190之后,源极/漏极区140可以被重掺杂。这样形成轻掺杂区和重掺杂区。轻掺杂区主要在栅极隔离结构190之下,同时重掺杂区在沿着鳍状件120的栅极隔离结构190的外侧。
图9示出第二实施例的横截面图,其中,finFET器件包括具有三个源极/漏极区140的双栅配置。在该实施例中,一个源极/漏极区140横向分隔开两个栅极180,并且两个其他源极/漏极区在两个栅极180的外侧上。类似于图7中的实施例,外部源极/漏极区140在横向上与最接近的体接触件150隔离距离720。
图9中的实施例可以开始如图2A至图5B中所示那样形成。在沉积栅电极层510(参见图5A和图5B)之后,栅电极层510被图案化,以形成两个栅极180和四个伪栅极182(参见图9)。在形成栅极180和伪栅极182之后,源极/漏极区140、体接触件150、栅极隔离结构190、以及电极层160可以被形成。源极/漏极区140、体接触件150、栅极隔离结构190、以及电极层160的形成在以上参考图7和图8进行了描述,因此在此不再重复。
图10A示出finFET器件的实施例的俯视图(top-down view),其中,器件具有在鳍状件结构之上和之下的衬底体接触件910。如图10A中所示,衬底体接触件910与鳍状件120和栅极180和182通过隔离区130分隔开。衬底体接触件910有助于提供对finFET器件的ESD保护。图10A示出相互基本平行的相互隔离的五个鳍状件120。每个鳍状件120都具有源极/漏极区140和体接触件150。另外,每个鳍状件120的源极/漏极区140和体接触件150都在伪栅极182的相对侧上。栅极180和伪栅极182基本相互平行并且垂直于鳍状件120。图10B是沿着图10A的线YY的横截面图。图10B示出衬底体接触件910与鳍状件120和伪栅极182通过隔离区130分隔开。
尽管已经详细地描述了本发明及其优势,但应该理解,可以在不背离所附权利要求限定的本发明主旨和范围的情况下,做各种不同的改变,替换和更改。而且,本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解,通过本发明,现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造,材料组分、装置、方法或步骤根据本发明可以被使用。因此,所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。
Claims (10)
1.一种半导体器件,包括:
衬底;
位于所述衬底之上凸起的鳍状件;所述鳍状件包括:
所述鳍状件中的第一源极/漏极区;
所述鳍状件中的第一体接触件;以及
所述鳍状件的第一部分,所述第一部分在横向上位于所述第一源极/漏极区和所述第一体接触件之间。
2.根据权利要求1所述的半导体器件,其中,所述第一部分仅包括鳍状件材料。
3.根据权利要求1所述的半导体器件,其中,所述鳍状件包含第一导电类型的掺杂物,所述第一源极/漏极区包含第二导电类型的掺杂物,所述第一体接触件包含所述第一导电类型的掺杂物。
4.根据权利要求3所述的半导体器件,其中,所述第一导电类型是p型,并且所述第二导电类型是n型。
5.根据权利要求1所述的半导体器件,其中,所述鳍状件进一步包括:位于所述鳍状件上方的第一栅极结构,其中,所述第一栅极结构直接位于所述鳍状件的所述第一部分的上方。
6.根据权利要求5所述的半导体器件,其中,所述鳍状件进一步包括:
所述鳍状件中的第二源极/漏极区,所述第二源极/漏极区在与所述第一体接触件相反的方向上与所述第一源极/漏极区分横向隔开;以及
位于所述鳍状件上方的第二栅极结构,其中,所述第二栅极结构在横向上位于所述第一源极/漏极区和所述第二源极/漏极区之间。
7.根据权利要求6所述的半导体器件,其中,所述鳍状件进一步包括:
所述鳍状件中的第三源极/漏极区,所述第三源极/漏极区在与所述第一源极/漏极区相反的方向上与所述第二源极/漏极区分横向隔开;
位于所述鳍状件上方的第三栅极结构,其中,所述第三栅极结构在横向上位于所述第二源极/漏极区和所述第三源极/漏极区之间;
所述鳍状件中的第二体接触件;
所述鳍状件的第二部分,所述第二部分在横向上位于所述第三源极/漏极区和所述第二体接触件之间;以及
位于所述鳍状件上方的第四栅极结构,其中,所述第四栅极结构直接位于所述鳍状件的第二部分的上方。
8.根据权利要求7所述的半导体器件,其中,所述鳍状件进一步包括:
所述鳍状件中的第一隔离区,其中,所述第一隔离区邻近所述鳍状件的所述第一部分的相对侧上的所述第一体接触件;
位于所述鳍状件上方的第五栅极结构,其中,所述第五栅极结构部分位于所述第一体接触件的上方并且部分位于所述第一隔离区的上方;
所述鳍状件中的第二隔离区,其中,所述第二隔离区邻近所述鳍状件的所述第二部分的相对侧上的所述第二体接触件;以及
位于所述鳍状件上方的第六栅极结构,其中,所述第六栅极结构部分位于所述第二体接触件的上方并且部分位于所述第二隔离区的上方。
9.一种半导体器件,包括:
衬底;
从所述衬底延伸的第一半导体鳍状件,其中,所述第一半导体鳍状件包括:
所述第一半导体鳍状件中的第一源极/漏极区;
所述第一半导体鳍状件中的第二源极/漏极区;
第一栅极结构,位于所述第一半导体鳍状件的顶面和侧壁上,其中,所述第一栅极结构在横向上位于所述第一源极/漏极区和所述第二源极/漏极区之间;
第一体接触件,位于所述第一半导体鳍状件中;以及
第二栅极结构,位于所述第一半导体鳍状件的顶面和侧壁上,其中,所述第二栅极结构在横向上位于所述第一源极/漏极区和所述第一体接触件之间。
10.一种形成半导体结构的方法,所述方法包括:
在衬底上形成半导体鳍状件;
在所述半导体鳍状件的顶面和侧壁上形成第一栅极结构;
在所述半导体鳍状件的顶面和侧壁上形成第二栅极结构,其中,所述第二栅极结构在横向上与所述第一栅极结构分隔开;
在所述半导体鳍状件的顶面和侧壁上形成第三栅极结构,其中,所述第三栅极结构在与所述第二栅极结构相反的方向上与所述第一栅极结构横向分隔开;
在所述半导体鳍状件中形成第一源极/漏极区,其中,所述第一源极/漏极区在横向上位于所述第一栅极结构和所述第二栅极结构之间;
在所述半导体鳍状件中形成第二源极/漏极区,其中,所述第二源极/漏极区在横向上位于所述第一栅极结构和所述第三栅极结构之间;以及
在所述半导体鳍状件中形成第一体接触件,其中,所述第一体接触件在横向上与第一源极/漏极区分隔开,并且所述第二栅极结构在横向上位于所述第一源极/漏极区和所述第一体接触件之间。
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Also Published As
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KR20130088704A (ko) | 2013-08-08 |
US9312384B2 (en) | 2016-04-12 |
CN103227202B (zh) | 2015-11-18 |
US8928093B2 (en) | 2015-01-06 |
US8735993B2 (en) | 2014-05-27 |
US20130193526A1 (en) | 2013-08-01 |
US20140193959A1 (en) | 2014-07-10 |
KR101372052B1 (ko) | 2014-03-25 |
US20150137264A1 (en) | 2015-05-21 |
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