CN103872102B - 具有嵌入式MOS变容二极管的FinFET及其制造方法 - Google Patents

具有嵌入式MOS变容二极管的FinFET及其制造方法 Download PDF

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CN103872102B
CN103872102B CN201310083982.0A CN201310083982A CN103872102B CN 103872102 B CN103872102 B CN 103872102B CN 201310083982 A CN201310083982 A CN 201310083982A CN 103872102 B CN103872102 B CN 103872102B
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CN103872102A (zh
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陈万得
陈重辉
洪照俊
康伯坚
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明实施例公开了半导体器件、FinFET器件以及形成FinFET器件的方法。一种实施例为包括位于衬底上方的第一FinFET的半导体器件，其中所述第一FinFET包括第一组半导体鳍。所述半导体器件还包括位于衬底上方的用于第一FinFET的第一体接触部，其中第一体接触部包括第二组半导体鳍，并且所述第一体接触部横向地与所述第一FinFET相邻。本发明还公开了具有嵌入式MOS变容二极管的鳍式场效应晶体管FinFET及其制造方法。

Description

具有嵌入式MOS变容二极管的FinFET及其制造方法
技术领域
本发明涉及半导体技术领域，更具体地，涉及一种具有嵌入式MOS变容二极管的鳍式场效应晶体管及其制造方法。
背景技术
晶体管是现代集成电路的关键部件。为了满足逐渐增快的速度需求，晶体管的驱动电流需要逐渐地增大。由于晶体管的驱动电流与晶体管的栅极宽度成比例，因此优选具有更大宽度的晶体管。然而，栅极宽度的增加与半导体器件尺寸减小的需求相矛盾。因而开发鳍式场效应晶体管(FinFET)。
在当前最先进的电路中，集成电路的操作频率为大约几百兆赫兹(MHz)至几吉赫兹(GHz)之间。在此类电路中，时钟信号的上升时间非常短，因此供电线中的电压波动可能非常大。对电路进行供电的供电线路中的不期望的电压波动可导致在其内部信号上的噪声并会使噪声容限降级。噪声容限的降级会降低电路可靠性甚至导致电路故障。
为减小供电线路中的电压波动的幅度，可以使用滤波或去耦电容器。去耦电容器用作在需要阻止供给电压瞬间下降时额外提供电流给电路的电荷储存器。
在试图将去耦电容器与其他电路相合并时，去耦电容器已被布置在片上。使用片上去耦电容器的一种尝试是使用薄膜平面电容器。然而，为使这些电容器通常具有充分足够大的电容，电容器通常需要较大区域并且难于设计和制造。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种半导体器件，包括：
位于衬底上方的第一FinFET，所述第一FinFET包括第一组半导体鳍；以及
位于所述衬底上方的用于所述第一FinFET的第一体接触部，所述第一体接触部包括第二组半导体鳍，并且所述第一体接触部横向地与所述第一FinFET相邻。
在可选实施例中，所述第一组半导体鳍包括至少两个半导体鳍，而所述第二组半导体鳍包括至少两个半导体鳍。
在可选实施例中，所述第一组半导体鳍与所述第二组半导体鳍平行。
在可选实施例中，所述第一FinFET还包括位于所述第一组半导体鳍上方的至少一个具有第一宽度和第一长度的有源栅极以及位于所述第一组半导体鳍上方的至少一个伪栅极，并且所述第一体接触部还包括位于所述第二组半导体鳍上方的至少一个具有第二宽度和第二长度的伪栅极。
在可选实施例中，所述第一宽度等于所述第二宽度并且所述第一长度等于所述第二长度。
在可选实施例中，所述第一FinFET还包括至少两个源极区和至少两个漏极区，其中，所述源极区和所述漏极区通过有源栅极分隔开。
在可选实施例中，所述半导体器件还包括：位于所述衬底上方的第二FinFET，所述第二FinFET包括第三组半导体鳍，并且所述第二FinFET在与所述第一体接触部相对的方向上横向地与所述第一FinFET相邻；以及，位于所述衬底上方的用于所述第二FinFET的第二体接触部，所述第二体接触部包括第四组半导体鳍，所述第二体接触部在与所述第一FinFET相对的方向上横向地与所述第二FinFET相邻接。
在可选实施例中，所述第一组鳍具有与所述第二组鳍相同的宽度和长度。
根据本发明的另一方面，还提供了一种FinFET器件，包括：
位于衬底上方的第一FinFET，所述第一FinFET包括：
多个第一鳍；和
位于所述多个第一鳍上方的至少两个有源栅极；以及
位于所述衬底上方的用于所述第一FinFET的第一体接触部，所述第一体接触部包括：
多个第二鳍；和
位于所述多个第二鳍上方的至少两个有源栅极。
在可选实施例中，位于所述多个第二鳍上方的所述至少两个有源栅极形成MOS变容二极管。
在可选实施例中，所述第一FinFET还包括位于所述多个第一鳍上方的至少两个伪栅极，并且所述第一体接触部还包括位于所述多个第二鳍上方的至少两个伪栅极。
在可选实施例中，所述第一FinFET的有源栅极的数量与所述第一体接触部的有源栅极的数量相同。
在可选实施例中，所述第一FinFET的有源栅极与所述第一体接触部的有源栅极横向相邻并对准。
在可选实施例中，所述第一体接触部的至少两个有源栅极电连接至偏压节点，从而形成去耦电容器。
在可选实施例中，所述第一体接触部的至少两个有源栅极电连接至接地节点或电源节点，从而形成去耦电容器。
在可选实施例中，所述FinFET器件还包括：位于衬底上方的第二FinFET，所述第二FinFET包括多个第三鳍，和，位于所述多个第三鳍上方的至少两个有源栅极；以及，位于所述衬底上方的用于所述第二FinFET的第二体接触部，所述第二体接触部包括多个第四鳍，和，位于所述多个第四鳍上方的至少两个有源栅极，其中所述多个第一鳍、所述多个第二鳍、所述多个第三鳍以及所述多个第四鳍相互平行。
根据本发明的又一方面，还提供了一种用于形成FinFET器件的方法，所述方法包括：
形成第一FinFET，包括：
在衬底上方形成多个第一鳍；
在所述多个第一鳍上方形成至少两个有源栅极；和
在所述多个第一鳍中形成至少两个源极区和至少两个漏极区；以及
形成用于所述第一FinFET的第一体接触部，包括：
在衬底上方形成多个第二鳍；
在所述多个第二鳍上方形成至少两个伪栅极；和
在所述多个第二鳍中形成至少两个体接触区。
在可选实施例中，所述方法还包括形成第一MOS变容二极管，形成所述第一MOS变容二极管包括在所述多个第二鳍上方形成至少两个有源栅极。
在可选实施例中，所述方法还包括形成去耦电容器，形成所述去耦电容器包括将位于所述多个第二鳍上方的至少两个有源栅极电连接至偏压节点。
在可选实施例中，所述方法还包括：形成第二FinFET，包括：在衬底上方形成多个第三鳍，在所述多个第三鳍上方形成至少两个有源栅极，和在所述多个第三鳍中形成至少两个源极区和至少两个漏极区；以及，形成用于所述第二FinFET的第二体接触部，包括：在所述衬底上方形成多个第四鳍，在所述多个第四鳍上方形成至少两个伪栅极，和在所述多个第四鳍中形成至少两个体接触区。
附图说明
为更完整的理解实施例及其优点，现将结合附图所进行的以下描述作为参考，其中：
图1至图5B以横截面视图和俯视图示出了根据实施例的在制造FinFET器件结构中的多个阶段；
图6A和6B示出了分别表示图5A所示出的FinFET器件的PMOS结构和NMOS结构的原理图；
图7以俯视图示出了根据另一实施例的具有嵌入式变容二极管的FinFET器件；以及
图8A和8B示出了分别表示图7所示出的FinFET器件的PMOS结构和NMOS结构的原理图。
具体实施方式
现将详细说明随附附图示出的实施例。只要可能，附图和说明书中使用相同的附图标记以指代相同或相似的部分。在附图中，为了清楚和简明的目的，可能增大形状和厚度。说明书将特别指向形成根据本发明的方法和装置部分的元件，或直接与根据本发明的方法和设备直接相配合的元件。可以理解，没有特别示出或描述的元件可采用本领域技术人员熟知的多种形式。一旦知晓本公开部分，对本领域技术人员来讲，许多替代选择和修改将变得明显。
本说明书中提及的“一个实施例”或“实施例”意味着所描述的与该实施例相关的特定的特征、结构或特性被包括在至少一个实施例中。因此，整个说明书中多处出现的“在一个实施例中”或“在实施例中”并不必须都指代相同的实施例。此外，特定的特征、结构或特性可以任何适合的方式相结合在一个或多个实施例中。优选地，附图并非按比例绘制，而是仅做示例的目的。
将针对特定环境来描述实施例，也即，具有基体接触部的FinFET器件。然而，其他实施例也可应用至具有包括嵌入式变容二极管的FinFET结构的其他器件。
图1示出在工艺的中间阶段的FinFET器件的100横截面示图。FinFET器件100包括半导体衬底20上的半导体层22。半导体衬底20可包括掺杂或不掺杂的体硅，或绝缘硅片(SOI)衬底的有源层。通常地，SOI衬底包括诸如硅、锗、硅锗、SOI、绝缘体上锗硅(SGOI)或上述组合的半导体材料层。可使用其他衬底包括多层衬底、梯度衬底或混合取向的衬底。
半导体衬底20可包括有源器件(为简明起见，图1中未示出)。作为本领域普通技术人员会知道，可使用诸如晶体管、电容器、电阻器及它们的组合等多种器件以为FinFET器件100产生满足结构和功能需求的设计。可使用任何适当的方法来形成这些器件。有源FinFET 28可电连接至有源或无源器件。由于已经能够充分说明所示出的实施例，因此图中仅示出了半导体衬底20的一部分。
可由诸如硅、锗、硅锗等的半导体材料来形成半导体层22。在实施例中，半导体层22是硅。然后，可通过注入工艺来对半导体层22进行掺杂以将p型或n型杂质引入到该半导体层22中。
在图2A和2B中示出了半导体层22成为有源鳍24和体接触鳍26的图案化。图2A是FinFET器件100的俯视图，图2B是沿着图2A中的线2B的横截面视图。鳍图案化工艺可通过在半导体层22上沉积例如光刻胶或氧化硅的掩模材料(未示出)来完成。然后，图案化掩模材料并根据图案对半导体层22进行蚀刻。所产生的结构包括形成在半导体层22中的多个有源鳍24和体接触鳍26。多个有源鳍24和体接触鳍26中的每个鳍具有与半导体衬底20的顶面大致垂直的侧壁。在一些实施例中，对半导体层22蚀刻特定的深度，这意味着形成一定高度的有源鳍24和体接触鳍26，有源鳍24的高度h2为大约10nm至大约500nm之间，体接触鳍26的高度h1为大约10nm至500nm之间。在一个特定实施例中，形成高度h2为大约110nm的有源鳍24，并形成高度h1为大约110nm的体接触鳍26。有源鳍24可具有大约5nm至50nm之间的宽度w2并且体接触鳍26可具有大约5nm至50nm之间的宽度w1。如图3a所示，有源鳍24可具有大约0.01um至10um之间的长度L2并且体接触鳍26可具有大约0.1um至10um之间的长度L1。在可选实施例中，可在形成在半导体衬底20上的图案化层中的沟槽或开口中从半导体衬底20的顶面外延生长有源鳍24和体接触鳍26。由于该工艺是本领域所熟知的，因此在此处不重复细节。
有源鳍24用作要形成的FinFET 28的鳍结构，并且体接触鳍26用作体接触部30的鳍结构。每个FinFET 28可包括单个有源鳍24至如用于FinFET器件100的必需的有源鳍24。图1至图5B示出了两个FinFET 28的形成，作为非限制的示例性实施例每个FinFET 28具有四个有源鳍24。同样地，体接触部30可包括单个体接触鳍26至用于FinFET器件100的必需的体接触鳍26，而非图2A至5B所示出的三个体接触鳍26。
现参考图3A至3B，介电层32均厚沉积在FinFET器件100上。介电层32由一种或多种合适的电介质材料(诸如氧化硅、氮化硅)、低k电介质(诸如掺杂碳的氧化物)、极低k电介质(诸如掺杂多孔碳的二氧化硅)、聚合物(诸如聚酰亚胺)以及它们的组合等构成。介电层32可通过例如化学气相沉积(CVD)工艺或旋涂式玻璃(spin-on-glass)工艺来沉积，然而可以利用任何可接受的工艺。
图4A和4B示出了制造工艺中接下来的步骤，其中介电层32被减薄以低于有源鳍24的顶部和体接触鳍26的顶部的水平。介电层32可以各种方式背面减薄。在一个实施例中，这是第一步骤涉及化学机械抛光(CMP)的多步骤工艺，其中介电层32起反应，然后使用研磨料研磨。该工艺可持续直至露出有源鳍24的顶部和体接触鳍26的顶部。接下来的减薄介电层32至有源鳍24的顶部和体接触鳍26的顶部以下的步骤可以各种方式来实施。一种这样的方式是通过进行稀氢氟酸(DHF)处理或者蒸汽氢氟酸(VHF)处理并持续一段合适的时间。在另一实施例中，可跳过CMP工艺步骤并且在不移除有源鳍24和体接触鳍26的情况下可选择性地背面减薄介电层32。该选择性地减薄可通过上述的DHF处理或VHF处理来实施。
图5A和5B示出了有源鳍24上的有源栅极38、有源鳍24和体接触鳍26的端部上的伪栅极34以及体接触鳍26上的伪栅极36的形成。伪栅极34和36的宽度和长度可以与有源栅极38不同(参见图5A)，或者伪栅极34和36可以具有与有源栅极38相同的宽度和长度。有源栅极38和伪栅极34和36可包括栅极介电层(未示出)、栅电极(未示出)以及栅极间隔件(未示出)。可通过热氧化、CVD、溅射或任何其他在本领域已知或已经使用的用于形成栅电介质的方法来形成栅极介电层。在其他实施例中，栅极介电层包括具有高介电常数(k值)例如大于3.9的介电材料。材料可包括硅氮化物、氮氧化物、诸如HfO2、HfZrOx、HfSiOx、HfTiOx、HfAlOx等金属氧化物、或者它们的组合和多层。
栅电极层可形成于栅极介电层之上。栅电极层可包括半导体材料并可选自包括多晶硅(poly-Si)、多晶硅锗(poly-SiGe)、金属氮化物、金属硅化物、金属氧化物以及金属的组。可通过CVD、溅射沉积或其他在本领域已知或已经使用的用于沉积半导体材料的技术来来沉积栅电极层。栅电极层的顶面通常具有非平坦的顶面，并可在对栅电极层的图案化或栅极蚀刻之前进行平坦化。此时，可以将离子引入或者不引入栅电极层。离子可通过例如离子注入技术来引入。栅电极层和栅极介电层可被图案化以形成有源栅极38和伪栅极34和36。栅极图案化工艺可通过在栅电极层上涂覆例如光刻胶或氧化硅的掩模材料(未示出)来完成。然后图案化掩模材料并且根据所得到的图案蚀刻栅电极层。
在形成有源栅极38和伪栅极34和36之后，将源极区40和漏极区42形成于有源鳍上。源极区40和漏极区42可通过实施注入工艺来注入合适的掺杂剂以在有源鳍24中补充掺杂剂来进行掺杂。在另一实施例中，可通过在有源鳍24中形成凹槽(未示出)并在凹槽中外延生长材料来形成源极区40和漏极区42。可通过上述注入方法或者通过在材料生长时原位掺杂来形成源极区40和漏极区42。有源栅极24和体接触鳍26的端部上的伪栅极34可用于控制源极区40和漏极区42以及体接触部40的外延生长。在实施例中，连续金属层可覆盖每个源极区40中的四个有源鳍24以在每个FinFET28中形成三个源极区40。此外，连续金属层可覆盖每个漏极区42中的四个有源鳍24以在每个FinFET 28中形成两个漏极区42。
在图5A和5B示出的实施例中，FinFET 28可配置在PMOS或NMOS结构中。在PMOS结构中，有源鳍24可掺杂n型掺杂剂，体接触鳍26可掺杂n型掺杂剂，源极区40和漏极区42可掺杂p型掺杂剂，并且体接触部44可掺杂n型掺杂剂。在NMOS结构中，有源鳍24可掺杂p型掺杂剂、体接触鳍26可掺杂p型掺杂剂、源极区40和漏极区42可掺杂n型掺杂剂，并且体接触部44可掺杂p型掺杂剂。
栅极间隔件可形成在有源栅极38和伪栅极34和36的相对侧。该栅极间隔件(未示出)典型地通过在前面形成的结构上均厚沉积间隔层(未示出)来形成。间隔层可包括SiN、氮氧化物、SiC、SiON、氧化物等并可通过所利用的形成这种层的方法来形成，例如CVD、等离子体增强CVD、溅射和其他本领域已知的其他方法。然后，栅极间隔件被图案化，优选通过各向异性蚀刻以从该结构的水平表面去除间隔层。
在另一实施例中，源极区40和漏极区42可包括轻掺杂区域和重掺杂区域。在该实施例中，在栅极间隔件形成之前，可以轻掺杂源极区40和漏极区42。在栅极间隔件形成之后，然后可重掺杂源极区40和漏极区42。这形成了轻掺杂区域和重掺杂区域。轻掺杂区域主要位于栅极间隔件的下面，而重度掺杂区域位于沿着有源鳍24的栅极间隔件的外部。
图6A和6B分别示出如图5A和5B所示的用于FinFET 28的PMOS结构和NMOS结构的原理表征图。两原理表征图都示出了连接至栅极端子的有源栅极38、连接至源极端子的源极区40、连接至漏极端子的漏极区42以及连接至基体端子的体接触部44。
图7示出了FinFET器件100的另一实施例，其中体接触鳍26具有形成于其上方的有源栅极46。有源栅极46的宽度和长度可与有源栅极38不同，或者有源栅极46可具有与有源栅极38相同的宽度和长度(参见图7)。体接触鳍26之上的有源栅极46可形成嵌入式MOS变容二极管50，该变容二极管可用作去耦电容器。在嵌入式MOS变容二极管50被配置为用作去耦电容器的实施例中，有源栅极46可连接至可使嵌入式MOS变容二极管50的电容变化的偏压节点。此外，在嵌入式MOS变容二极管50的NMOS结构中，有源栅极46可连接至接地节点以用作去耦电容器。在嵌入式MOS变容二极管50的PMOS结构中，有源栅极46可连接至电源节点以用作去耦电容器。
在图7示出的实施例中，FinFET 28和嵌入式MOS变容二极管50可各自配置在PMOS或NMOS结构中。在FinFET 28为PMOS并且嵌入式MOS变容二极管50为NMOS的一实施例中，有源鳍24可掺杂n型掺杂剂、体接触鳍26可掺杂n型掺杂剂、源极区40和漏极区42可掺杂p型掺杂剂，并且体接触部48可掺杂n型掺杂剂。在FinFET 28为NMOS并且嵌入式MOS变容二极管50为PMOS的另一实施例中，有源鳍24可掺杂p型掺杂剂、体接触鳍26可掺杂p型掺杂剂、源极区40和漏极区42可掺杂n型掺杂剂，并且体接触部44可掺杂p型掺杂剂。
图8A和8B示出了图7中所示的FinFET 28以及嵌入式MOS变容二极管50的PMOS和NMOS结构的原理表征图。在图8A中，FinFET 28为PMOS并且嵌入式MOS变容二极管50为NMOS。在图8B中，FinFET 28为NMOS并且嵌入式MOS变容二极管50为PMOS。这两个原理表征图都示出了连接至FinFET 28的栅极端子的有源栅极38、连接至FinFET 28的源极端子的源极区40、连接至FinFET 28的漏极端子的漏极区42、以及连接至FinFET 28的基体端子的体接触部48。在FinFET 28为PMOS并且嵌入式MOS变容二极管50为NMOS(参见图8A)的一实施例中，有源栅极46可连接至偏压节点或接地节点以形成去耦电容器。在FinFET 28为NMOS并且嵌入式MOS变容二极管50为PMOS(参见图8B)的另一实施例中，有源栅极46可连接至偏压节点或电源节点以形成去耦电容器。
通过在体接触鳍26上用有源栅极46来替换伪栅极36以形成嵌入式MOS变容二极管50，由于用于有源栅极46的材料可被利用作为去耦电容器，因此降低了FinFET器件100的成本。此外，通过在已存在体接触鳍26和体接触鳍之上的栅极的结构中嵌入必要的电容器，可减少FinFET器件100的总面积。
一实施例为一种半导体器件，其包括位于衬底上方的第一FinFET，其中第一FinFET包括第一组半导体鳍。半导体器件还包括位于衬底上方用于第一FinFET的第一体接触部，其中第一体接触部包括第二组半导体鳍，并且该第一体接触部横向地与第一FinFET相邻。
另一实施例为一种FinFET器件，其包括位于衬底上方的第一FinFET，该第一FinFET包括多个第一鳍以及位于多个第一鳍上方的至少两个有源栅极。该FinFET器件还包括位于衬底上方的用于第一FinFET的第一体接触部，其中第一体接触部包括多个第二鳍以及位于多个第二鳍上方的至少两个有源栅极。
又一实施例为一种用于形成FinFET器件的方法，该方法包括：形成第一FinFET，形成第一FinFET包括在衬底上方形成多个第一鳍，在多个第一鳍上方形成至少两个有源栅极，并形成在该多个第一鳍中形成至少两个源极区和两个漏极区。该方法包括形成用于第一FinFET的第一体接触部，形成用于第一FinFET的第一体接触部包括在衬底上方形成多个第二鳍，在多个第二鳍上形成至少两个伪栅极，以及在多个第二鳍中形成至少两个体触区。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该将这样的工艺、机器、制造、材料组分、装置、方法或步骤包括在范围内。

Claims (20)

1.一种半导体器件，包括：
位于衬底上方的第一FinFET，所述第一FinFET包括第一组半导体鳍；
位于所述衬底上方的用于所述第一FinFET的第一体接触部，所述第一体接触部包括第二组半导体鳍，并且所述第一体接触部横向地与所述第一FinFET相邻；以及
位于所述第二组半导体鳍上方的至少两个伪栅极，其中，体接触区介于所述至少两个伪栅极中的第一伪栅极与所述至少两个伪栅极中的第二伪栅极之间。
2.根据权利要求1所述的半导体器件，其中，所述第一组半导体鳍包括至少两个半导体鳍，而所述第二组半导体鳍包括至少两个半导体鳍。
3.根据权利要求1所述的半导体器件，其中，所述第一组半导体鳍与所述第二组半导体鳍平行。
4.根据权利要求1所述的半导体器件，其中，所述第一FinFET还包括位于所述第一组半导体鳍上方的至少一个具有第一宽度和第一长度的有源栅极以及位于所述第一组半导体鳍上方的至少一个伪栅极，并且所述至少两个伪栅极中的第一伪栅极具有第二宽度和第二长度。
5.根据权利要求4所述的半导体器件，其中，所述第一宽度等于所述第二宽度并且所述第一长度等于所述第二长度。
6.根据权利要求1所述的半导体器件，其中，所述第一FinFET还包括至少两个源极区和至少两个漏极区，其中，所述源极区和所述漏极区通过有源栅极分隔开。
7.根据权利要求1所述的半导体器件，还包括：
位于所述衬底上方的第二FinFET，所述第二FinFET包括第三组半导体鳍，并且所述第二FinFET在与所述第一体接触部相对的方向上横向地与所述第一FinFET相邻；以及
位于所述衬底上方的用于所述第二FinFET的第二体接触部，所述第二体接触部包括第四组半导体鳍，所述第二体接触部在与所述第一FinFET相对的方向上横向地与所述第二FinFET相邻接。
8.根据权利要求1所述的半导体器件，其中，所述第一组鳍具有与所述第二组鳍相同的宽度和长度。
9.一种FinFET器件，包括：
位于衬底上方的第一FinFET，所述第一FinFET包括：
多个第一鳍；和
位于所述多个第一鳍上方的至少两个有源栅极；以及
位于所述衬底上方的用于所述第一FinFET的第一体接触部，所述第一体接触部包括：
多个第二鳍；和
位于所述多个第二鳍上方的至少两个有源栅极。
10.根据权利要求9所述的FinFET器件，其中，位于所述多个第二鳍上方的所述至少两个有源栅极形成MOS变容二极管。
11.根据权利要求9所述的FinFET器件，其中，所述第一FinFET还包括位于所述多个第一鳍上方的至少两个伪栅极，并且所述第一体接触部还包括位于所述多个第二鳍上方的至少两个伪栅极。
12.根据权利要求9所述的FinFET器件，其中，所述第一FinFET的有源栅极的数量与所述第一体接触部的有源栅极的数量相同。
13.根据权利要求12所述的FinFET器件，其中，所述第一FinFET的有源栅极与所述第一体接触部的有源栅极横向相邻并对准。
14.根据权利要求9所述的FinFET器件，其中，所述第一体接触部的至少两个有源栅极电连接至偏压节点，从而形成去耦电容器。
15.根据权利要求9所述的FinFET器件，其中，所述第一体接触部的至少两个有源栅极电连接至接地节点或电源节点，从而形成去耦电容器。
16.根据权利要求9所述的FinFET器件，还包括：
位于衬底上方的第二FinFET，所述第二FinFET包括：
多个第三鳍；和
位于所述多个第三鳍上方的至少两个有源栅极；以及
位于所述衬底上方的用于所述第二FinFET的第二体接触部，所述第二体接触部包括：
多个第四鳍，和
位于所述多个第四鳍上方的至少两个有源栅极，其中所述多个第一鳍、所述多个第二鳍、所述多个第三鳍以及所述多个第四鳍相互平行。
17.一种用于形成FinFET器件的方法，所述方法包括：
形成第一FinFET，包括：
在衬底上方形成多个第一鳍；
在所述多个第一鳍上方形成至少两个有源栅极；和
在所述多个第一鳍中形成至少两个源极区和至少两个漏极区；以及
形成用于所述第一FinFET的第一体接触部，包括：
在衬底上方形成多个第二鳍；
在所述多个第二鳍上方形成至少两个伪栅极；和
在所述多个第二鳍中形成至少两个体接触区。
18.根据权利要求17所述的方法，其中，所述方法还包括形成第一MOS变容二极管，形成所述第一MOS变容二极管包括在所述多个第二鳍上方形成至少两个有源栅极。
19.根据权利要求18所述的方法，其中，所述方法还包括形成去耦电容器，形成所述去耦电容器包括将位于所述多个第二鳍上方的至少两个有源栅极电连接至偏压节点。
20.根据权利要求17所述的方法，其中，还包括：
形成第二FinFET，包括：
在衬底上方形成多个第三鳍；
在所述多个第三鳍上方形成至少两个有源栅极；和
在所述多个第三鳍中形成至少两个源极区和至少两个漏极区；以及
形成用于所述第二FinFET的第二体接触部，包括：
在所述衬底上方形成多个第四鳍；
在所述多个第四鳍上方形成至少两个伪栅极；和在所述多个第四鳍中形成至少两个体接触区。
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Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9299699B2 (en) * 2013-03-13 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate and complementary varactors in FinFET process
CN105493264B (zh) * 2013-08-23 2018-06-01 株式会社索思未来 半导体集成电路装置
CN108922887B (zh) * 2013-09-04 2022-12-09 株式会社索思未来 半导体装置
US9941271B2 (en) * 2013-10-04 2018-04-10 Avago Technologies General Ip (Singapore) Pte. Ltd. Fin-shaped field effect transistor and capacitor structures
US9196499B2 (en) * 2014-03-26 2015-11-24 Globalfoundries Inc. Method of forming semiconductor fins
US9450079B2 (en) * 2014-04-09 2016-09-20 International Business Machines Corporation FinFET having highly doped source and drain regions
KR102208063B1 (ko) 2014-04-22 2021-01-27 삼성전자주식회사 반도체 장치 및 그 제조 방법
CN106415838B (zh) 2014-06-27 2023-04-07 英特尔公司 去耦电容器和布置
US9614023B2 (en) 2014-12-29 2017-04-04 Globalfoundries Inc. Substrate resistor with overlying gate structure
US20160190120A1 (en) * 2014-12-29 2016-06-30 Globalfoundries Inc. Fin resistor with overlying gate structure
US9607988B2 (en) * 2015-01-30 2017-03-28 Qualcomm Incorporated Off-center gate cut
US9397038B1 (en) 2015-02-27 2016-07-19 Invensas Corporation Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates
US9443853B1 (en) 2015-04-07 2016-09-13 International Business Machines Corporation Minimizing shorting between FinFET epitaxial regions
US9722043B2 (en) * 2015-06-15 2017-08-01 International Business Machines Corporation Self-aligned trench silicide process for preventing gate contact to silicide shorts
KR102372001B1 (ko) * 2015-06-24 2022-03-08 르네사스 일렉트로닉스 가부시키가이샤 반도체 장치
US9570388B2 (en) 2015-06-26 2017-02-14 International Business Machines Corporation FinFET power supply decoupling
US9853112B2 (en) * 2015-07-17 2017-12-26 Qualcomm Incorporated Device and method to connect gate regions separated using a gate cut
WO2017052558A1 (en) * 2015-09-24 2017-03-30 Intel Corporation Techniques for revealing a backside of an integrated circuit device, and associated configurations
US9728624B2 (en) * 2015-10-28 2017-08-08 International Business Machines Corporation Semiconductor testing devices
US9520392B1 (en) 2015-11-30 2016-12-13 International Business Machines Corporation Semiconductor device including finFET and fin varactor
KR102421730B1 (ko) 2016-04-05 2022-07-18 삼성전자주식회사 레이아웃 방법 및 반도체 소자
US10269793B2 (en) 2016-04-28 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain regions in fin field effect transistors (FinFETs) and methods of forming same
US10522534B2 (en) 2016-04-29 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET varactor with low threshold voltage and method of making the same
US10002923B2 (en) 2016-06-06 2018-06-19 International Business Machines Corporation Techniques for forming finFET transistors with same fin pitch and different source/drain epitaxy configurations
CN107564953B (zh) * 2016-07-01 2021-07-30 中芯国际集成电路制造(上海)有限公司 变容晶体管及其制造方法
US9911736B1 (en) * 2017-06-14 2018-03-06 Globalfoundries Inc. Method of forming field effect transistors with replacement metal gates and contacts and resulting structure
US20190115342A1 (en) * 2017-10-16 2019-04-18 Qualcomm Incorporated High quality factor fin metal oxide semiconductor varactor with improved number of fins
KR102403031B1 (ko) * 2017-10-19 2022-05-27 삼성전자주식회사 반도체 장치
CN109994471B (zh) * 2017-12-29 2020-12-22 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US10332819B1 (en) * 2018-03-29 2019-06-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method for manufacturing the same
JP6674056B2 (ja) * 2019-02-05 2020-04-01 ルネサスエレクトロニクス株式会社 半導体装置
CN112786704B (zh) * 2020-12-31 2023-04-07 泉芯集成电路制造(济南)有限公司 鳍式场效应管制程中变容二极管及其制作方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1706027A (zh) * 2002-10-18 2005-12-07 因芬尼昂技术股份公司 包含电容器的集成电路装置及制造方法
CN103227202A (zh) * 2012-01-31 2013-07-31 台湾积体电路制造股份有限公司 FinFET体接触件及其制造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7115920B2 (en) 2004-04-12 2006-10-03 International Business Machines Corporation FinFET transistor and circuit
US7241649B2 (en) 2004-10-29 2007-07-10 International Business Machines Corporation FinFET body contact structure
TWI283925B (en) 2005-11-22 2007-07-11 Taiwan Semiconductor Mfg A FinFET with a body contact
US7446001B2 (en) * 2006-02-08 2008-11-04 Freescale Semiconductors, Inc. Method for forming a semiconductor-on-insulator (SOI) body-contacted device with a portion of drain region removed
US9455348B2 (en) 2007-02-01 2016-09-27 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET for device characterization
JP2010040630A (ja) 2008-08-01 2010-02-18 Toshiba Corp 半導体装置
JP2010199161A (ja) * 2009-02-23 2010-09-09 Renesas Electronics Corp 半導体集積回路装置及びその製造方法
US8420476B2 (en) 2010-05-27 2013-04-16 International Business Machines Corporation Integrated circuit with finFETs and MIM fin capacitor
US8860107B2 (en) * 2010-06-03 2014-10-14 International Business Machines Corporation FinFET-compatible metal-insulator-metal capacitor
JP5614333B2 (ja) * 2011-03-01 2014-10-29 富士通セミコンダクター株式会社 半導体装置
US8236634B1 (en) 2011-03-17 2012-08-07 International Business Machines Corporation Integration of fin-based devices and ETSOI devices
US8703553B2 (en) * 2012-05-15 2014-04-22 International Business Machines Corporation MOS capacitors with a finFET process
US8969974B2 (en) * 2012-06-14 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET device
US8841185B2 (en) * 2012-08-13 2014-09-23 International Business Machines Corporation High density bulk fin capacitor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1706027A (zh) * 2002-10-18 2005-12-07 因芬尼昂技术股份公司 包含电容器的集成电路装置及制造方法
CN103227202A (zh) * 2012-01-31 2013-07-31 台湾积体电路制造股份有限公司 FinFET体接触件及其制造方法

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