CN103545371A - 用于功率mos晶体管的装置和方法 - Google Patents

用于功率mos晶体管的装置和方法 Download PDF

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CN103545371A
CN103545371A CN201210468800.7A CN201210468800A CN103545371A CN 103545371 A CN103545371 A CN 103545371A CN 201210468800 A CN201210468800 A CN 201210468800A CN 103545371 A CN103545371 A CN 103545371A
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drain
conductivity
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semiconductor device
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CN103545371B (zh
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伍震威
周学良
苏柏智
柳瑞兴
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种MOS晶体管，包括衬底、形成在衬底上方的第一区、从第一区生长的第二区、形成在第二区中的第三区、形成在第三区中的第一漏极/源极区、形成在第一沟槽中的第一栅电极、形成在第二区中并且在第一沟槽的第一漏极/源极区的相对侧上的第二漏极/源极区以及耦合第二漏极/源极区和第二区的第二沟槽，其中第二沟槽具有与第一沟槽相同的深度。本发明还提供了用于功率MOS晶体管的装置和方法。

Description

用于功率MOS晶体管的装置和方法
技术领域
本发明一般地涉及半导体技术领域，更具体地来说，涉及半导体器件及其形成方法。
背景技术
由于诸如晶体管、二极管、电阻器、电容器等的各种电子部件的集成密度的改进，半导体工业经历了快速增长。通常，这种集成密度的改进源于半导体工艺节点的缩小(例如，工艺节点缩小到20nm以下的节点)。随着半导体器件按比例缩小，需要新技术来维持从一代到下一代的电子元件的性能。例如，可以期望用于功率应用的晶体管的较低的栅极与漏极电容和较低的导通阻抗。
随着半导体技术发展，金属氧化物半导体场效应晶体管(MOSFET)广泛用于当今的集成电路中。MOSFET是电压控制器件。当控制电压施加给MOSFET的栅极并且控制电压大于MOSFET的阈值时，在MOSFET的漏极和源极之间建立了导电通道。因此，电流流经MOSFET的漏极和源极之间。另一方面，当控制电压小于MOSFET的阈值时，MOSFET相应地截止。
MOSFET可以包括两大类。一种是n沟道MOSFET，另一种是p沟道MOSFET。根据结构差异，MOSFET可以被进一步划分为两个子类，即，沟道功率MOSFET和横向功率MOSFET。在沟道功率MOSFET中，采用p体区以形成耦合在形成在p体区上方的源极区和形成在p体区下方的漏极区之间的沟道。此外，在沟道功率MOSFET中，漏极和源极位于晶圆的相对侧上。可以存在包括形成在沟道功率MOSFET的漏极和源极之间的栅电极的沟道结构。
沟道功率MOSFET通常被称为垂直功率MOSFET。由于其较低的栅极驱动功率、快速开关速度和较低导通阻抗，垂直功率MOSFET广泛应用于高电压和大电流的应用中。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种半导体器件，包括：衬底，具有第一导电性；第一区，具有第二导电性并形成在所述衬底上方；第二区，具有所述第二导电性并从所述第一区生长；第三区，具有所述第一导电性并形成在所述第二区中；第一漏极/源极区，具有所述第二导电性并形成在所述第三区中；第一沟槽，包括：介电层，形成在所述第一沟槽的底部中；和栅极区，形成在所述第一沟槽的上部中；第二漏极/源极区，具有所述第二导电性，形成在所述第二区中并位于所述第一沟槽与所述第一漏极/源极区相对的一侧；以及第二沟槽，耦合在所述第二漏极/源极区和所述第二区之间，所述第二沟槽具有与所述第一沟槽相同的深度。
在该半导体器件中，所述第二沟槽的宽度大于所述第一沟槽的宽度。
在该半导体器件中，所述第二沟槽被配置成沿着所述第二沟槽的侧壁生成积累层。
在该半导体器件中，所述第一区是隐埋层。
在该半导体器件中，所述第二区是外延层。
在该半导体器件中，所述第三区是体区。
该半导体器件进一步包括：第四区，具有所述第一导电性并形成在所述第三区中，其中，所述第四区耦合至所述第一漏极/源极区。
在该半导体器件中，所述栅极区耦合至所述第二沟槽。
在该半导体器件中，所述介电层包括氧化物。
在该半导体器件中，所述第一漏极/源极区是源极；以及所述第二漏极/源极区是漏极。
根据本发明的另一方面，提供了一种器件，包括：第一漏极/源极区，具有第一导电性；第一栅极，形成在第一沟槽中，其中，所述第一沟槽包括形成在所述第一栅极下方的介电层；第二漏极/源极区，具有所述第一导电性，其中，所述第一漏极/源极区和所述第二漏极/源极区形成在所述第一栅极的相对侧；以及第二沟槽，其中：所述第二沟槽具有与所述第一沟槽相同的深度；并且所述第二沟槽和所述第一沟槽形成在所述第二漏极/源极区的相对侧。
该器件进一步包括：衬底，具有第二导电性；第一区，具有所述第一导电性并形成在所述衬底上方；第二区，具有所述第一导电性并从所述第一区生长，其中，所述第二漏极/源极区形成在所述第二区中；以及第三区，具有所述第二导电性并形成在所述第二区中，其中，所述第一漏极/源极区形成在所述第三区中。
该器件进一步包括：具有所述第二导电性的体区，其中，所述体区耦合至所述第一漏极/源极区。
在该器件中，所述第一栅极包括：第一栅极介电层，形成在所述第一沟槽中，所述第一栅极介电层形成在所述第一沟槽的侧壁和所述介电层的顶面上方；以及第一栅电极，形成在所述栅极介电层上方。
在该器件中，所述第二沟槽包括多晶硅。
根据又一方面，提供了一种方法，包括：在具有第二导电性的衬底上方形成具有第一导电性的隐埋层；从所述隐埋层生长具有所述第一导电性的外延层；形成延伸到所述外延层和所述隐埋层中的第一沟槽和第二沟槽，其中：所述第一沟槽和所述第二沟槽具有相同的深度；并且所述第二沟槽的宽度大于所述第一沟槽的宽度；在所述第一沟槽的底部中形成介电层；在所述第一沟槽的上部中形成第一栅电极；将具有所述第二导电性的离子注入到位于所述第一沟槽的第一侧的所述外延层中以形成体区；在位于所述第一沟槽的第一侧的所述体区上方形成第一漏极/源极区；以及在位于所述第一沟槽的第二侧的所述外延层上方形成第二漏极/源极区。
在该方法中：所述第一侧和所述第二侧位于所述第一沟槽的相对侧。
该方法进一步包括：紧邻所述第一漏极/源极区形成体接触件，其中，所述体接触件耦合至所述第一漏极/源极区。
该方法进一步包括：在所述第一沟槽和所述第二沟槽中沉积介电材料，直到所述第一沟槽完全填充有所述介电材料以及所述第二沟槽部分填充有所述介电材料为止。
在该方法中：所述第一漏极/源极区、所述第二漏极/源极区和所述第一栅电极形成功率金属氧化物半导体晶体管。
附图说明
为了更好地理解本发明及其优点，现在将结合附图所进行的以下描述作为参考，其中：
图1示出了根据一个实施例的准垂直沟道MOS晶体管的简化截面图；
图2示出了根据一个实施例在衬底上方形成N-型外延层和NBL层之后的半导体器件的截面图；
图3示出了根据一个实施例的在衬底上方形成介电层和硬掩模层之后的图2所示的半导体器件的截面图；
图4示出了根据一个实施例的在合适的蚀刻工艺应用于介电层和硬掩模层之后的图3所示的半导体器件的截面图；
图5示出了根据一个实施例的在蚀刻工艺应用于N-型外延层上之后的图4所示的半导体器件的截面图；
图6示出了根据一个实施例的在氧化物沉积工艺应用于第一沟槽和第二沟槽之后的图5所示的半导体器件的截面图；
图7示出了根据一个实施例的在蚀刻工艺应用于氧化层之后的图6所示的半导体器件的截面图；
图8示出了根据一个实施例的在硬掩模去除工艺应用于半导体器件的顶面之后的图7所示的半导体器件的截面图；
图9示出了根据一个实施例的在沟槽中形成栅极介电层之后的图8所示的半导体器件的截面图；
图10示出了根据一个实施例的在沟槽中形成栅电极层之后的图9所示的半导体器件的截面图；以及
图11示出了根据一个实施例的在各种离子注入工艺应用于半导体器件的顶面之后的在图10所示的半导体器件的截面图。
除非另有说明，否则不同附图中的相应数字和符号通常指的是相应部件。为了清楚地说明各个实施例的相关方面绘制这些附图，并且没有必要按比例绘制。
具体实施方式
以下详细讨论了本实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的创造性概念。所讨论的具体实施例仅为制造和使用本发明的实施例的具体方式，并且没有限定本发明的范围。
将结合具体上下文中的实施例，即，准垂直功率金属氧化物半导体(MOS)晶体管器件来描述本发明。然而，本发明的实施例也可以应用于各种半导体器件。下文中，将参考附图说明各个实施例。
图1示出了根据一个实施例的准垂直沟道MOS晶体管的简化截面图。准垂直沟道MOS晶体管100包括第一导电类型的衬底102。根据一个实施例，第一导电类型是P型。准垂直沟道MOS晶体管100进一步包括形成在衬底102上方的N型隐埋层(NBL)104和形成在NBL层104上方的N型外延层106。准垂直沟道MOS晶体管100进一步包括包含氧化物区110和栅极区112的第一沟槽。如图1所示，在氧化物区110上方形成栅极区112。准垂直沟道MOS晶体管100可以进一步包括形成在N型外延层106中的P型体(PB)区108、P+区126、第一N+区122和第二N+区124。
如图1所示，P+区126和第一N+区122形成在PB区108中。第二N+区124形成在N型外延层106中。根据一个实施例，第一N+区122是准垂直沟道MOS晶体管100的源极区。第二N+区124是准垂直沟道MOS晶体管100的漏极区。PB区108是耦合在准垂直沟道MOS晶体管100的源极和漏极之间的沟道。如图1所示，在栅极区112的相对侧上形成第一N+区122和第二N+区124。第二N+区124用作漏极区，该第二N+区124通过N-型外延层106和NBL层104耦合至沟道区(PB区108)。
准垂直沟道MOS晶体管100包括具有与第一沟槽相同深度的第二沟槽。具体地，第二沟槽包括深沟槽114和沿着深沟槽114的侧壁形成的积累层(未示出)。如图1所示，紧邻第二N+区124形成第二沟槽。根据一个实施例，深沟槽114可以电耦合至栅极区112。当栅极控制电压施加给栅极区112和深沟槽114时，栅极控制电压可以吸引大部分的载流子并沿着深沟槽114的侧壁生成积累层(未示出)。积累层可以是更多数的载流子。因此，在NBL层104和第二N+区124之间建立了低阻抗漏极电流导电通路。
如图1所示，尽管N型外延层106可以将来自NBL层104的漏极电流运载至第二N+区124，但是N型外延层106的阻抗高于沿着深沟槽114的侧壁形成的积累层的阻抗。通过采用耦合在第二N+区124和NBL层104之间的积累层，改善了电流传输。此外，通过耦合NBL层104与第二N+区124，可以从NBL层104拾取漏极电流。因此，准垂直沟道MOS晶体管100的漏极可以置于与源极相同的一侧。
准垂直MOS晶体管100的一个有利特征是图1中的准垂直结构可以很容易地集成在横向制造工艺中。准垂直MOS晶体管100的另一个有利特征是沿着第二沟槽的侧壁形成的积累层有助于提供用于漏极电流的低导通阻抗沟道。因此，尽管采用准垂直结构，但改善了MOS晶体管100的导通阻抗。
图2至图11示出了根据一个实施例制造图1所示的准垂直沟道MOS晶体管100的中间步骤。图2示出了根据一个实施例的在衬底上方形成N型外延层和NBL层之后的半导体器件的截面图。如图2所示，在P型衬底102上方形成NBL层104。在NBL层104上方形成N型外延层106。应该注意，虽然图2示出了衬底102的导电类型是P-型，但其仅仅是实例。衬底102可以是N型。本领域技术人员应该意识到，响应衬底102的导电类型改变其他层的导电类型可以改变。
衬底102可以由硅、硅锗、碳化硅等形成。可选地，衬底102可以是绝缘体上硅(SOI)衬底。SOI衬底可以包括在绝缘体层(例如，隐埋氧化物等)上方形成的半导体材料(例如，硅、锗等)层，该半导体材料层形成在硅衬底中。可以使用的其他衬底包括多层衬底、梯度衬底、混合定向衬底等。
可以通过将诸如磷等的N-型掺杂材料注入到衬底102中来形成NBL层104。可选地，可以通过扩散工艺形成NBL层104。根据一个实施例，NBL层104的掺杂密度在约1019/cm3至约1020/cm3的范围内。
从NBL层104生长N-型外延层106。可以通过使用诸如化学汽相沉积(CVD)、超高真空化学汽相沉积(UHV-CVD)等的任意合适的半导体制造工艺来实施N型外延层106的外延生长。根据一个实施例，N型外延层106具有在的掺杂密度在约1015/cm3至约1018/cm3的范围内。
图3示出了根据一个实施例的在衬底上方形成介电层和硬掩模层之后的图2所示的半导体器件的截面图。介电层302可以包括氧化层。可以通过在包括氧化物、H2O、NO或者它们的组合的周围环境中的诸如湿或者干热氧化的任意氧化工艺，或者通过使用四乙基正硅酸盐(TEOS)和氧气作为前体的CVD技术来形成介电层302。
根据一个实施例，在介电层302上沉积硬掩模层304。硬掩模层304可以由氮化硅形成。通过诸如CVD等的合适制造技术在介电层302的顶部上沉积硬掩模层304。
图4示出了根据一个实施例的在合适的蚀刻工艺应用于介电层和硬掩模层之后的图3所示的半导体器件的截面图。考虑准垂直功率MOS晶体管100(在图1中所示)的第一沟槽和第二沟槽的位置来图案化硬掩模层304和介电层302。此后，实施诸如反应离子蚀刻(RIE)或其他干蚀刻、各向异性湿蚀刻、或者任意其他合适的各向异性蚀刻或图案化工艺的蚀刻工艺以形成图4所示的开口402和404。应该注意，根据一个实施例，开口404的宽度大于开口402的宽度。
图5示出了根据一个实施例的在蚀刻工艺应用于N-型外延层之后的图4所示的半导体器件的截面图。诸如RIE、干蚀刻、湿蚀刻或者任意其他合适的各向异性蚀刻技术的应用于N型外延层106以形成沟槽502和沟槽504。如图5所示，在同一制造步骤中形成第一沟槽502和第二沟槽504。第一沟槽502和第二沟槽504的这种单步骤形成有助于减小MOS晶体管100的制造成本。
如图5所示，蚀刻工艺可以蚀刻穿透N-型外延层106和部分蚀刻NBL层104。此外，图5示出了第一沟槽502的深度大致等于第二沟槽504的深度。应该注意，如图5所示，第二沟槽504的宽度大于第一沟槽502的宽度。第二沟槽504的相对较大的开口有助于在后续氧化物沉积工艺期间保持开口。下面结合图6详细描述氧化物沉积工艺。
图6示出了根据一个实施例的在氧化物沉积工艺应用于第一沟槽和第二沟槽之后的图5所示的半导体器件的截面图。如图6所示，介电层602填充第一沟槽502(在图5中所示)，但部分地填充第二沟槽504。在介电沉积工艺之后，可以存在位于沟槽504中的开口604。如以上关于图5所述，第二沟槽504的宽度大于第一沟槽502的宽度。因此，通过控制介电沉积工艺，介电层602可以部分地填充第二沟槽504。
根据一个实施例，介电层602可以由氧化物形成。在通篇描述中，介电层602可以可选地称为氧化层602。可以通过使用合适的热处理技术、湿处理技术或者诸如PVD、CVD、ALD等沉积技术来形成氧化层602。应该注意，图6所示的氧化层602仅仅是实例。可以可选地使用其他介电材料，诸如氮化物、氮氧化物、高k材料、它们的组合和它们的多层。
图7示出了根据一个实施例的在蚀刻工艺应用于氧化层之后的图6所示的半导体器件的截面图。实施诸如RIE、各向异性湿蚀刻或者任何其他合适的各向异性蚀刻工艺的蚀刻工艺以去除位于第一沟槽中的氧化层的上部，从而形成图7所示的氧化层110。
此外，控制蚀刻工艺使得完全去除位于第二沟槽中的氧化层。换句话说，第二沟槽没有氧化物。根据一个实施例，图7所示的氧化层110具有厚度H1。H1在约0.5μm至约5μm的范围内。应该注意，在通篇描述中所引用的尺寸仅仅是实例，并且可以改变为不同值。应该进一步注意，图7所示的氧化层110用作有助于减小表面电场的场板(field plate)。此外，沿着氧化层110减小的表面电场可以提高MOS晶体管100的额定电压。
图8示出了根据一个实施例的在硬掩模去除工艺应用于半导体器件的顶面之后的图7所示的半导体器件的截面图。如图8所示，已通过诸如湿蚀刻工艺的合适的硬掩模层去除工艺去除图7所示的硬掩模层和氧化层。去除工艺应用于半导体器件的顶面，直到暴露N型外延层106为止。
图9示出了根据一个实施例的在沟道中形成栅极介电层之后的图8所示的半导体器件的截面图。如图9所示，栅极介电层902形成在第一沟槽和第二沟槽中。栅极介电层902可以由通常使用诸如氧化物、氮化物、氮氧化物、高k材料、它们的组合和它们的多层的介电材料形成。
根据一个实施例，栅极介电层902是氧化层。可以通过使用合适的热处理技术、湿处理技术或者诸如PVD、CVD、ALD等沉积技术来形成栅极介电层902。
图10示出了根据一个实施例的在沟槽中形成栅电极层之后的图9所示的半导体器件的截面图。可以通过同一制造工艺用相同材料填充栅极区112和深沟槽114。
栅极区112和深沟槽114可以包括导电材料，诸如金属材料(例如，钽、钛、钼、钨、铂、铝、铪、钌)、金属硅化物(例如，硅化钛、硅化钴、硅化镍、硅化钽)、金属氮化物(例如，氮化钛、氮化钽)、掺杂多晶硅、其他导电材料或者它们的组合。根据一个实施例，沉积和再结晶非晶硅以生成多晶体硅(多晶硅)。
根据一个实施例，栅极区112和深沟槽114可以由多晶硅形成。可以通过利用低压化学汽相沉积(LPCVD)沉积掺杂的或者未掺杂的多晶硅来形成栅极区112和深沟槽114。根据另一个实施例，栅极区112和深沟槽114由诸如氮化钛、氮化钽、氮化钨、钛、钽和/或它们的组合的金属材料形成。可以使用诸如ALD、CVD、PVD等的合适沉积技术来形成金属栅电极层。上面的沉积技术是本领域众所周知的，因此本文中没有进行讨论。
图11示出了根据一个实施例的在各种离子注入工艺应用于半导体器件的顶面之后的图10所示的半导体器件的截面图。如图11所示，在N型外延层106中形成PB区108。根据一个实施例，PB区的掺杂浓度在约1016/cm3至约1018/cm3的范围内。可以通过注入诸如浓度在约1019/cm3和约1020/cm3之间的硼的p型掺杂剂来形成P+区126。
在PB区108上方形成第一N+区122。根据一个实施例，第一N+区122用作MOS晶体管100的源极。可以通过注入诸如浓度在约1019/cm3和约1020/cm3之间的磷的n型掺杂剂来形成源极区。此外，可以在第一N+区122上方形成源极接触件(未示出)。
在N型外延层中形成第二N+区124。根据一个实施例，第二N+区124可以是MOS晶体管100的漏极。可以通过注入诸如浓度在约1019/cm3和约1020/cm3之间的磷的n型掺杂剂来形成漏极区。如图1所示，在与源极区(第一N+区122)的相对侧上形成漏极区。
可以通过注入诸如浓度在约1019/cm3至约1020/cm3之间的硼的n型掺杂剂来形成P+区126。P+区126可以与MOS晶体管100的P型体接触。为了消除体效应(body effect)，P+区126可以直接通过源极接触件(未示出)耦合至第一N+区122(MOS晶体管100的源极)。
在图11所示的半导体器件的顶面上方形成层间介电(ILD)层(未示出)。ILD层可以由氮化硅掺杂硅酸盐玻璃形成，但是可以可选地使用诸如掺硼磷硅酸盐玻璃等的其他材料。可以通过蚀刻工艺在ILD层中形成接触开口(未示出)。在蚀刻工艺之后，ILD层的一部分保留并成为栅极-源极介电层132。此外，在开口中沉积导电材料以形成源极接触件(未示出)。
尽管已经详细地描述了本发明的实施例及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变、替换和更改。
而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造、材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。

Claims (10)

1.一种半导体器件，包括：
衬底，具有第一导电性；
第一区，具有第二导电性并形成在所述衬底上方；
第二区，具有所述第二导电性并从所述第一区生长；
第三区，具有所述第一导电性并形成在所述第二区中；
第一漏极/源极区，具有所述第二导电性并形成在所述第三区中；
第一沟槽，包括：
介电层，形成在所述第一沟槽的底部中；和
栅极区，形成在所述第一沟槽的上部中；
第二漏极/源极区，具有所述第二导电性，形成在所述第二区中并位于所述第一沟槽与所述第一漏极/源极区相对的一侧；以及
第二沟槽，耦合在所述第二漏极/源极区和所述第二区之间，所述第二沟槽具有与所述第一沟槽相同的深度。
2.根据权利要求1所述的半导体器件，其中，所述第二沟槽的宽度大于所述第一沟槽的宽度。
3.根据权利要求1所述的半导体器件，其中，所述第二沟槽被配置成沿着所述第二沟槽的侧壁生成积累层。
4.根据权利要求1所述的半导体器件，其中，所述第一区是隐埋层。
5.根据权利要求1所述的半导体器件，其中，所述第二区是外延层。
6.根据权利要求1所述的半导体器件，其中，所述第三区是体区。
7.根据权利要求1所述的半导体器件，进一步包括：
第四区，具有所述第一导电性并形成在所述第三区中，其中，所述第四区耦合至所述第一漏极/源极区。
8.根据权利要求1所述的半导体器件，其中，所述栅极区耦合至所述第二沟槽。
9.一种器件，包括：
第一漏极/源极区，具有第一导电性；
第一栅极，形成在第一沟槽中，其中，所述第一沟槽包括形成在所述第一栅极下方的介电层；
第二漏极/源极区，具有所述第一导电性，其中，所述第一漏极/源极区和所述第二漏极/源极区形成在所述第一栅极的相对侧；以及
第二沟槽，其中：
所述第二沟槽具有与所述第一沟槽相同的深度；并且
所述第二沟槽和所述第一沟槽形成在所述第二漏极/源极区的相对侧。
10.一种方法，包括：
在具有第二导电性的衬底上方形成具有第一导电性的隐埋层；
从所述隐埋层生长具有所述第一导电性的外延层；
形成延伸到所述外延层和所述隐埋层中的第一沟槽和第二沟槽，其中：
所述第一沟槽和所述第二沟槽具有相同的深度；并且
所述第二沟槽的宽度大于所述第一沟槽的宽度；
在所述第一沟槽的底部中形成介电层；
在所述第一沟槽的上部中形成第一栅电极；
将具有所述第二导电性的离子注入到位于所述第一沟槽的第一侧的所述外延层中以形成体区；
在位于所述第一沟槽的第一侧的所述体区上方形成第一漏极/源极区；以及
在位于所述第一沟槽的第二侧的所述外延层上方形成第二漏极/源极区。
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