CN100505218C - 半导体结构及其制作方法 - Google Patents
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Abstract
在同一衬底的应变层区域和无应变层区域中制作半导体器件。第一半导体器件,如存储单元,例如深沟槽存储单元形成在衬底的无应变层区域中。应变层区域选择性地形成在同一衬底中。第二半导体器件(66、68、70),如FET,例如MOSFET逻辑器件形成在应变层区域中。
Description
技术领域
本发明的领域是半导体处理。具体地,本发明涉及在同一衬底的应变层区域和无应变层区域中形成半导体器件。
背景技术
形成在应变硅沟道上的半导体器件,如金属氧化物半导体场效应晶体管(MOSFET)已经表现出在迁移率和性能方面提供显著的改善。还没有实现在用于嵌入DRAM应用的同一半导体芯片上成功地集成高性能的应变硅逻辑型MOSFET和诸如致密的、低漏电的动态随机存取存储器(DRAM)阵列的存储器,这是由于需要在DRAM阵列区域中保持高质量的、无缺陷的硅,而在逻辑支持(support)区域中提供应变硅。应变硅和用于内禀地产生应变所需的衬底导致硅位错的大量增加,这使得它与低漏电的DRAM单元不相容。并且,超过对于DRAM单元形成所需的某种温度的半导体处理可能与当前应用的应变硅形成不相容。
需要在与低漏电的、高密度的DRAM单元的同一衬底上形成高性能应变硅的支持MOSFET。
发明内容
因此,本发明的一个目的是在与低漏电的、高密度的DRAM单元的同一衬底上形成高性能应变硅的支持MOSFET。
本发明提供了一种半导体结构,包括:具有无应变层区和应变层区的半导体衬底;在半导体衬底的无应变层区中形成的第一器件;以及在半导体衬底的应变层区中形成的第二器件;其中,所述第一器件包括存储单元,所述第二器件包括FET。
本发明还提供了一种制作半导体结构的方法,包括以下步骤:a).提供具有无应变层区的半导体衬底;b).在半导体衬底的无应变层区中形成第一器件;c).在半导体衬底中选择性地形成应变层区;以及d).在应变层区中形成第二器件;其中,所述第一器件包括存储单元,所述第二器件包括FET。
本发明公开了形成在半导体衬底的无应变层区域中的一种第一半导体器件,例如低漏电的DRAM单元。在同一半导体衬底上,与无应变层的区域隔开在半导体衬底中选择性地形成应变层区域,以及在应变层区域中形成第二半导体器件,例如高性能的MOSFET。
附图说明
在阅读如下对本发明的详细描述时,本发明的前述和其它特征将更明显。在如下的描述中,将参照一些附图,其中:
图1-8是在根据本发明的方法各步骤期间呈现的半导体结构的截面图。
具体实施方式
参照图1,p型硅衬底10被提供有形成在衬底10的无应变层区域中的存储单元12。在图1中,存储单元12是具有沟槽存储电容器14和垂直MOSFET16的DRAM单元,这可以按例如在共同受让的美国专利6,225,158B1中所描述的方法而形成,该专利在此引用为参考。尽管在图1中,存储单元12被表示成具有沟槽存储电容器14和垂直MOSFET16,但应当注意,存储单元12可以采用其它类型的电容器和FET形成,如堆叠的电容器或平面的MOSFET。在该例子中,沟槽存储电容器14包括:深沟槽18、n+埋置板20、氮化物/氧化物节点介质22、n+多晶硅24和26、颈圈氧化物28和n+埋置带圈扩散(strapdiffusion)30。并且,垂直MOSFET16包括:沟槽顶部氧化物32、形成在深沟槽18侧壁上的栅氧化物34、以及n+多晶硅栅导体36。应当注意,在图1-8的阵列区域中示出了两个存储单元12。然而,应当理解,可以在阵列区域中形成任意数目的一个或更多个存储单元12。
在衬底10的无应变层区域中形成存储单元12之后,在衬底10中形成应变层区域,用于随后的高性能MOSFET的形成。因而,因为应变层区域和MOSFET在形成存储单元之后而形成,工艺不相容性,如在形成存储单元中使用的高温得以避免。
如图2所示,在衬垫膜38(它可包括例如衬垫氮化物和衬垫氧化物层)和栅导体36的暴露部分上沉积薄层40(例如氧化硅)。氧化物层40在随后的处理中用作腐蚀停止层。
然后在氧化物层40上沉积另一层42(例如氮化硅),在氮化硅层42上沉积硬掩模层44(例如氧化硅)。
在氧化物硬掩模层44上图案化阻挡抗蚀剂(未示出),采用反应离子腐蚀,该腐蚀穿过层38、40、42、44的暴露部分并进入衬底10内,达到大约100纳米到大约400纳米的优选深度,更优选地为大约200纳纳米,以形成如图2所示的沟槽46。在形成沟槽46之后从氧化物硬掩模层44上去除任何剩余的阻挡抗蚀剂。
参照图3,通过标准的工艺去除氧化物硬掩模层44,如对氮化硅层42和由沟槽46暴露的硅有选择性的反应离子腐蚀。如通过传统的沉积和RIE,在沟槽46的侧壁表面50上形成包括硅或硅锗(SiGe)将不在其上形核的材料的间隔层48,如氧化硅或氮化硅。线性渐变缓冲层技术可用于在沟槽46中生长低位错密度(~105cm-2)的SiGe层52。生长条件有利于选择性地在衬底10上形成SiGe层52,而不在间隔层48上形成该层。优选地,SiGe层52从沟槽46的暴露底表面54开始向上外延生长,直至SiGe层52达到氮化硅层42的顶表面之上。通过如化学机械抛光(CMP)的工艺,对过生长的SiGe层52平面化至氮化硅层42的顶表面。可以采用本领域公知的硅CMP工艺平面化SiGe层52。
可选地,可以省略间隔层48,但是,间隔层48防止SiGe层52从侧壁表面50形核并向外外延生长,这会导致在SiGe层52中有两个生长前端。此外,间隔层48隔离了由衬底10中的SiGe层52对芯片的支持区域产生的应变,因而使得阵列中的存储电容器单元与应变隔离。
接着,如图4所示,通过腐蚀工艺,如使用SF6气体的反应离子腐蚀或HF湿刻之后的氧化,选择性地凹进SiGe层52的上表面56,达到低于氮化硅层42的上表面的深度。可选地,可以省略SiGe层52的凹进,因为随后生长的应变层很薄。
参照图5,在SiGe层52的上表面56上选择性地生长外延硅薄层58。外延硅层58被生长到优选小于大约50纳米的厚度,更优选地在从大约2.5纳米到大约10纳米的厚度。由于SiGe层52和薄外延硅层58之间的晶格错配,外延硅层58经受了拉伸晶格应变,这增强了随后形成的FET的迁移率。在生长外延硅层58之后,通过本领域公知的工艺,如包括热磷酸的湿刻,相对于氧化物层40和外延硅层58选择性地去除氮化硅层42。应当注意,应变层58也可以采用其它的方法形成,例如,在SiGe层52的上表面56上沉积钛(Ti)或钴(Co)金属,并形成硅化钛或硅化钴的薄层。形成应变层58的另一个例子包括向SiGe层52的上表面56中注入晶格常数不同于SiGe的元素,例如碳(C)或锗(Ge)。
参照图6,在氧化物层40和应变硅层58上沉积氮化硅层60,然后对其图案化以暴露支持区域,同时阵列仍被覆盖。支持区域中的有源区被图案化以形成浅沟槽隔离(STI)62,该浅沟槽在平面化之后采用公知的方法来填充,如TEOS CVD氧化物或HDP氧化物。牺牲氧化物(未示出)被生长在支持部分中,并且形成阱注入区(未示出)。去除牺牲氧化物,并通过生长介质薄膜,如热氧化物或氮化的氧化物,在应变硅层58上形成支持栅介质64。在应变层区(支持区)中形成支持栅导体66,采用阻挡掩模去除在应变层区(阵列)中剩余的部分栅导体66。
参照图7,通过本领域公知的方法,如包括热磷酸的湿刻,相对于氧化物层40选择性地从阵列去除氮化硅层60。然后相对于氮化硅层38选择性地去除氧化物层40。在支持区和阵列区中沉积字线导体68,如钨/硅化钨,并沉积盖层,如氮化硅70。
参照图8,采用公共掩模同时图案化并腐蚀支持栅66、字线68和盖层70。可选地,可以使用两个掩模以形成支持栅66和字线68。例如,可以使用一个掩模形成支持栅66,同时可以使用另一个掩模形成字线68,从而独立地优化各自的特定性能,如从性能方面考虑的线宽。
随后是标准的处理,包括:支持区S/D扩展、晕圈(halo)和接触注入;栅侧壁氧化以恢复由于栅腐蚀而造成的任何损伤;间隔层形成;支持和位线接触柱;层间介质;以及沉积和图案化上层的布线,包括位线导体。
此外,如果关注硅位错从应变层SiGe区传播进入无应变层的存储阵列,可以使用虚拟深存储沟槽作为应变层(支持区)和无应变层(阵列区)区域之间的缓冲。
尽管参照其优选实施方式描述了本发明,但应当理解本发明的精神和范围不因此受到限制。而是,如上所述,可以对本发明进行各种变更,而不背离如上所述并由本申请的权利要求提出的本发明的总的范围。
Claims (14)
1.一种半导体结构,包括:
具有无应变层区和应变层区的半导体衬底;
在半导体衬底的无应变层区中形成的第一器件;以及
在半导体衬底的应变层区中形成的第二器件;
其中,所述第一器件包括存储单元,所述第二器件包括FET。
2.权利要求1的半导体结构,其中所述存储单元是低漏电的DRAM单元,所述FET是MOSFET逻辑器件。
3.权利要求1的半导体结构,其中所述应变层区具有在衬底中选择性地形成的沟槽,并包括:形成在沟槽中的SiGe层,以及形成在SiGe层上的外延硅层。
4.权利要求3的半导体结构,其中所述外延硅层的厚度为2.5纳米至10纳米。
5.权利要求3的半导体结构,其中所述SiGe层是外延生长的。
6.权利要求3的半导体结构,其中所述应变层区还包括在沟槽的侧壁上形成的间隔层,该间隔层将应变层区中产生的应变与无应变层区隔开。
7.权利要求3的半导体结构,其中所述沟槽的深度为100纳米至400纳米。
8.一种制作半导体结构的方法,包括以下步骤:
a).提供具有无应变层区的半导体衬底;
b).在半导体衬底的无应变层区中形成第一器件;
c).在半导体衬底中选择性地形成应变层区;以及
d).在应变层区中形成第二器件;
其中,所述第一器件包括存储单元,所述第二器件包括FET。
9.权利要求8的方法,其中步骤c)还包括:
i)形成具有底表面和侧壁表面的沟槽;
ii)在沟槽中形成SiGe层;以及
iii)在SiGe层上形成硅层。
10.权利要求8的方法,其中步骤ii)包括外延生长SiGe层。
11.权利要求8的方法,其中步骤iii)包括外延生长硅层。
12.权利要求8的方法,其中所述硅层的厚度为2.5纳米至10纳米。
13.权利要求8的方法,其中在步骤i)之后,在侧壁表面上形成间隔层。
14.权利要求8的方法,其中所述存储单元是低漏电的DRAM单元,所述FET是MOSFET逻辑器件。
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PCT/US2003/000562 WO2004064148A1 (en) | 2003-01-08 | 2003-01-08 | High performance embedded dram technology with strained silicon |
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JP (1) | JP4524190B2 (zh) |
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WO2003017336A2 (en) * | 2001-08-13 | 2003-02-27 | Amberwave Systems Corporation | Dram trench capacitor and method of making the same |
JP4322706B2 (ja) * | 2004-02-27 | 2009-09-02 | 株式会社東芝 | 半導体装置の製造方法 |
JP4177775B2 (ja) * | 2004-03-16 | 2008-11-05 | 株式会社東芝 | 半導体基板及びその製造方法並びに半導体装置 |
US7384829B2 (en) * | 2004-07-23 | 2008-06-10 | International Business Machines Corporation | Patterned strained semiconductor substrate and device |
US7704844B2 (en) | 2007-10-04 | 2010-04-27 | International Business Machines Corporation | High performance MOSFET |
DE102011005639B4 (de) * | 2011-03-16 | 2016-05-25 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | Reduzieren der Defektrate während des Abscheidens einer Kanalhalbleiterlegierung in ein in-situ-abgesenktes aktives Gebiet |
TWI508139B (zh) * | 2011-08-17 | 2015-11-11 | United Microelectronics Corp | 製作半導體裝置的方法 |
US9130060B2 (en) | 2012-07-11 | 2015-09-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit having a vertical power MOS transistor |
US8669611B2 (en) | 2012-07-11 | 2014-03-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and method for power MOS transistor |
CN109687864A (zh) * | 2017-10-19 | 2019-04-26 | 成都海存艾匹科技有限公司 | 含有可编程计算单元的可编程门阵列 |
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DE4102888A1 (de) * | 1990-01-31 | 1991-08-01 | Toshiba Kawasaki Kk | Verfahren zur herstellung eines miniaturisierten heterouebergang-bipolartransistors |
JPH05144834A (ja) * | 1991-03-20 | 1993-06-11 | Hitachi Ltd | バイポーラトランジスタ及びその製造方法 |
US5212110A (en) * | 1992-05-26 | 1993-05-18 | Motorola, Inc. | Method for forming isolation regions in a semiconductor device |
US5399507A (en) * | 1994-06-27 | 1995-03-21 | Motorola, Inc. | Fabrication of mixed thin-film and bulk semiconductor substrate for integrated circuit applications |
JP2953567B2 (ja) * | 1997-02-06 | 1999-09-27 | 日本電気株式会社 | 半導体装置の製造方法 |
JP4258034B2 (ja) * | 1998-05-27 | 2009-04-30 | ソニー株式会社 | 半導体装置及び半導体装置の製造方法 |
US6333532B1 (en) * | 1999-07-16 | 2001-12-25 | International Business Machines Corporation | Patterned SOI regions in semiconductor chips |
JP4074051B2 (ja) * | 1999-08-31 | 2008-04-09 | 株式会社東芝 | 半導体基板およびその製造方法 |
JP3512701B2 (ja) * | 2000-03-10 | 2004-03-31 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2001338988A (ja) * | 2000-05-25 | 2001-12-07 | Hitachi Ltd | 半導体装置及びその製造方法 |
CA2316480A1 (en) * | 2000-08-18 | 2002-02-18 | Tim Mccarthy | Adjustable partition assembly |
US6350653B1 (en) * | 2000-10-12 | 2002-02-26 | International Business Machines Corporation | Embedded DRAM on silicon-on-insulator substrate |
JP3875040B2 (ja) * | 2001-05-17 | 2007-01-31 | シャープ株式会社 | 半導体基板及びその製造方法ならびに半導体装置及びその製造方法 |
KR100414204B1 (ko) * | 2001-05-31 | 2004-01-07 | 삼성전자주식회사 | 캐퍼시터 소자를 갖는 반도체 메모리 장치 및 그 형성 방법 |
WO2003017336A2 (en) * | 2001-08-13 | 2003-02-27 | Amberwave Systems Corporation | Dram trench capacitor and method of making the same |
JP2004165197A (ja) * | 2002-11-08 | 2004-06-10 | Renesas Technology Corp | 半導体集積回路装置およびその製造方法 |
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