JP4148518B2 - 隆起外部ベースを有するBiCMOSの集積方式 - Google Patents
隆起外部ベースを有するBiCMOSの集積方式 Download PDFInfo
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- 230000010354 integration Effects 0.000 title description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 123
- 238000000034 method Methods 0.000 claims description 93
- 150000004767 nitrides Chemical class 0.000 claims description 43
- 229920005591 polysilicon Polymers 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 21
- 238000002955 isolation Methods 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 15
- 125000006850 spacer group Chemical group 0.000 claims description 14
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 10
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 7
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 230000000295 complement effect Effects 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- 238000000407 epitaxy Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 125
- 238000005229 chemical vapour deposition Methods 0.000 description 15
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 238000005137 deposition process Methods 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 10
- 238000001459 lithography Methods 0.000 description 8
- 239000010408 film Substances 0.000 description 7
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 239000000945 filler Substances 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000003631 wet chemical etching Methods 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000012876 topography Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 238000000224 chemical solution deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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Description
基板上に設けられたゲート誘電体の表面上に多結晶シリコン層を形成するステップであって、前記基板が、少なくとも1個のバイポーラ・トランジスタを形成するデバイス区域と、少なくとも1個の相補型金属酸化物半導体(CMOS)トランジスタを形成するデバイス区域とを有するステップと、
前記多結晶シリコン層をパターン化して、少なくとも1個のバイポーラ・トランジスタを形成する前記デバイス区域の上に犠牲多結晶シリコン層を設け、一方、少なくとも1個のCMOSトランジスタを形成する前記デバイス区域に少なくとも1個のゲート導体を同時に設けるステップと、
少なくとも1個のゲート導体のそれぞれのまわりに少なくとも1対のスペーサを形成して、前記少なくとも1個のCMOSトランジスタを設けるステップと、
少なくとも1個のバイポーラ・トランジスタを形成する前記デバイス区域の上の前記犠牲多結晶シリコン層の一部を選択的に除去して、少なくとも1個の開口部を設けるステップと、
少なくとも1個の開口部に、隆起外部ベースを有する少なくとも1個のバイポーラ・トランジスタを形成するステップと
を含む方法、すなわちBiCMOS集積方式を提供する。
12 分離領域
14 バイポーラ・トランジスタ区域
16 CMOSトランジスタ・デバイス区域
18 ゲート誘電体
20 多結晶シリコン層
22 犠牲多結晶シリコン層
24 多結晶シリコン・ゲート誘電体
24’ 多結晶シリコン・ゲート誘電体
26 酸化物層
28 窒化物層(または多層)
30 酸化物スペーサ
32 各多結晶シリコン・ゲート間に存在するスペース
34 多結晶シリコン位置設定材料
36 第2酸化物層
38 第2多結晶シリコン層
40 キャップ酸化物層
41 開口部
42 ベース層
44 酸化物層
46 CVD多結晶シリコン層
48 開口部内のCVD多結晶シリコン層
50 フォトレジスト・マスク
52 CMPストップ層
54 エミッタ・ペデスタル・スタック
56 窒化物外部スペーサ
58 隆起外部ベース
60 酸化物分離層
62 置換内部窒化物スペーサ
63 コレクタ・コンタクト区域
64 フォトレジスト・マスク
66 エミッタ・多結晶シリコン層
68 窒化物層
Claims (13)
- BiCMOS集積回路の製作方法であって、
(1)基板上に設けられたゲート誘電体の表面上に多結晶シリコン層を形成するステップであって、前記基板が、少なくとも1個のバイポーラ・トランジスタを形成するデバイス区域と、少なくとも1個の相補型金属酸化物半導体(CMOS)トランジスタを形成するデバイス区域とを有するステップと、
(2)前記多結晶シリコン層をパターン化して、少なくとも1個のバイポーラ・トランジスタを形成する前記デバイス区域に犠牲多結晶シリコン層を設け、一方、少なくとも1個のCMOSトランジスタを形成する前記デバイス区域に少なくとも1個のゲート導体を同時に設けるステップと、
(3)少なくとも1個のゲート導体のそれぞれのまわりに少なくとも1対のスペーサを形成して、前記少なくとも1個のCMOSトランジスタを設けるステップと、
(4)少なくとも1個のバイポーラ・トランジスタを形成する前記デバイス区域の上の前記犠牲多結晶シリコン層の一部を選択的に除去して、少なくとも1個の開口部を設けるステップと、
(5)少なくとも1個の開口部に、隆起外部ベースを有する少なくとも1個のバイポーラ・トランジスタを形成するステップであって、下記ステップ(i)〜(ix)を含むステップと、
(i)前記少なくとも1個の開口部に、エピタキシャル層を形成するステップ、
(ii)エピタキシャル層の上に酸化物を形成するステップ、
(iii)酸化物の上に多結晶シリコン層を形成するステップ、
(iv)多結晶シリコン層の上面が、前記開口部以外の部分の上面と同じ平面になるように、該多結晶シリコンを除去するステップ、
(v)CMPストップ層をブランケット付着するステップ、
(vi)隆起外部ベースを形成する領域のCMPストップ層とその下の多結晶シリコンを除去して、エミッタを形成する領域のCMPストップ層とその下の多結晶シリコンからなるエミッタ・ペデスタル・スタックを形成するステップ、
(vii)前記多結晶シリコンの除去により露出された酸化物層を除去し、その跡に隆起外部ベースを形成するステップ、
(viii)ブランケット酸化物層を付着させ、CMPプロセスを用いて、開口部内のブランケット酸化物層の上面が、開口部以外の部分に残存するCMPストップ層の上面と同じ平面になるようにブランケット酸化物層を除去することによって、前記隆起外部ベースの上に酸化物分離層を形成するステップ、
(ix)前記エミッタ・ペデスタル・スタックを除去した後、該エミッタ・ペデスタル・スタックが以前占めていた区域にエミッタ・多結晶シリコンを形成するステップ、
を含む方法。 - ステップ(2)と(3)の間に、多結晶シリコンの露出したすべての垂直および水平表面及びゲート誘電体上に、酸化物層を形成し、次いで、該酸化物層の上に窒化物層を形成するステップをさらに含む、請求項1記載の方法。
- ステップ(3)と(4)の間に、CMOSゲート間及びCMOSゲートと犠牲多結晶シリコン層の間のスペースに多結晶シリコンを充填した後、該多結晶シリコンの上面が前記窒化物層の上面と同じ平面になるように該多結晶シリコンを除去するステップをさらに含む、請求項2に記載の方法。
- ステップ(4)の前に、前記窒化物層と多結晶シリコン上に、第2酸化物層、第2多結晶シリコン層、次いで、キャップ酸化物層を順次積層するステップをさらに含む請求項3記載の方法。
- ステップ(4)の後に、開口部において露出された、基板上に設けられた前記ゲート誘電体を除去するステップをさらに含み、ステップ(i)においてエピタキシャル層が該ゲート誘電体の前記除去によって露出された基板上に形成されると共に、多結晶シリコン層が第2多結晶シリコン層上に形成される、請求項4記載の方法。
- ステップ(ix)において、エミッタ・多結晶シリコンの付着前に、犠牲多結晶シリコン層上の酸化物層と窒化物層をまず除去し、エミッタ・多結晶シリコンを付着し、次いで、エミッタ・多結晶シリコンのエッチング時にエミッタ・多結晶シリコンと一緒に犠牲多結晶シリコン層を除去するステップをさらに含む、請求項2〜5のいずれか1項に記載の方法。
- 前記隆起外部ベースがシリコンまたはSiGeからなる、請求項1〜6のいずれか1項に記載の方法。
- ステップ(vii)において、隆起外部ベースが、まず多結晶シリコンまたはSiGeをブランケット付着させ、CMPプロセスを用いて該多結晶シリコンまたはSiGeの上面がCMPストップ層の上面と同じ平面になるまで該多結晶シリコンまたはSiGeを除去し、残った多結晶シリコンまたはSiGeを隆起外部ベース層の目標厚みまでリセスさせることによって隆起外部ベースを形成する、請求項1〜7のいずれか1項に記載の方法。
- ステップ(vii)において、隆起外部ベースが、SiまたはSiGeの選択的エピタキシによって形成される、請求項1〜7のいずれか1項記載の方法。
- CMPストップ層が窒化物からなる、請求項1〜9のいずれか1項に記載の方法。
- ステップ(ix)において、前記エミッタ・ペデスタル・スタックが以前占めていた区域の露出側壁に置換内部窒化物スペーサを形成するステップをさらに含む、請求項1〜10のいずれか1項に記載の方法。
- CMOSゲート間及びCMOSゲートと犠牲多結晶シリコン層の間のスペースに充填された多結晶シリコンが、前記ステップ(ix)においてエミッタを形成するために多結晶シリコンをエッチングする工程中に除去される、請求項3〜11のいずれか1項に記載の方法。
- ステップ(ii)において、酸化物が、少なくとも1個のバイポーラ・トランジスタを形成するデバイス区域と、少なくとも1個の相補型金属酸化物半導体(CMOS)トランジスタを形成するデバイス区域に形成され、ステップ(iii)において、多結晶シリコン層が前記酸化物上にブランケット付着され、ステップ(iv)において、開口部以外の部分に在る多結晶シリコン層を除去して前記酸化物上で停止させて、開口部内の多結晶シリコン層の上面をCMOSゲートと犠牲多結晶シリコン上の前記酸化物の上面と同じ平面にする、請求項3〜12のいずれか1項記載の方法。
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US20050145953A1 (en) * | 2004-01-05 | 2005-07-07 | Chartered Semiconductor Manufacturing Ltd | Heterojunction BiCMOS integrated circuits and method therefor |
US7291541B1 (en) | 2004-03-18 | 2007-11-06 | National Semiconductor Corporation | System and method for providing improved trench isolation of semiconductor devices |
US7060551B2 (en) * | 2004-06-18 | 2006-06-13 | Macronix International Co., Ltd. | Method of fabricating read only memory and memory cell array |
TW200849556A (en) * | 2006-06-14 | 2008-12-16 | Nxp Bv | Semiconductor device and method of manufacturing such a device |
JP4947692B2 (ja) * | 2006-07-11 | 2012-06-06 | 旭化成エレクトロニクス株式会社 | 半導体装置の製造方法及び半導体装置 |
JP5027457B2 (ja) * | 2006-07-11 | 2012-09-19 | 旭化成エレクトロニクス株式会社 | 半導体装置の製造方法 |
US7892910B2 (en) * | 2007-02-28 | 2011-02-22 | International Business Machines Corporation | Bipolar transistor with raised extrinsic self-aligned base using selective epitaxial growth for BiCMOS integration |
US7927958B1 (en) | 2007-05-15 | 2011-04-19 | National Semiconductor Corporation | System and method for providing a self aligned bipolar transistor using a silicon nitride ring |
US7910447B1 (en) | 2007-05-15 | 2011-03-22 | National Semiconductor Corporation | System and method for providing a self aligned bipolar transistor using a simplified sacrificial nitride emitter |
US7642168B1 (en) * | 2007-05-18 | 2010-01-05 | National Semiconductor Corporation | System and method for providing a self aligned bipolar transistor using a sacrificial polysilicon external base |
US7846806B1 (en) * | 2007-05-25 | 2010-12-07 | National Semiconductor Corporation | System and method for providing a self aligned silicon germanium (SiGe) heterojunction bipolar transistor using a mesa emitter-base architecture |
US7838375B1 (en) | 2007-05-25 | 2010-11-23 | National Semiconductor Corporation | System and method for providing a polyemit module for a self aligned heterojunction bipolar transistor architecture |
US7645666B2 (en) * | 2007-07-23 | 2010-01-12 | Infineon Technologies Ag | Method of making a semiconductor device |
US7790542B2 (en) * | 2008-06-18 | 2010-09-07 | International Business Machines Corporation | CMOS devices having reduced threshold voltage variations and methods of manufacture thereof |
CN102738153B (zh) * | 2012-07-16 | 2016-03-30 | 西安电子科技大学 | 一种SiGe HBT双应变平面BiCMOS集成器件及制备方法 |
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