JP2004319983A - 隆起外部ベースを有するBiCMOSの集積方式 - Google Patents
隆起外部ベースを有するBiCMOSの集積方式 Download PDFInfo
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- 239000004020 conductor Substances 0.000 claims abstract description 9
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- 239000010703 silicon Substances 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 123
- 229920005591 polysilicon Polymers 0.000 claims description 92
- 150000004767 nitrides Chemical class 0.000 claims description 44
- 239000000463 material Substances 0.000 claims description 22
- 238000002955 isolation Methods 0.000 claims description 17
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- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 3
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- 229910052732 germanium Inorganic materials 0.000 description 1
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Abstract
【解決手段】バイポーラ・トランジシスタを形成するデバイス区域14と、CMOSトランジスタを形成するデバイス区域16とを有する基板上に設けられたゲート誘電体18の表面上に多結晶シリコン層を形成するステップを含む。次いで、多結晶シリコン層をパターン化して、バイポーラ・トランジスタを形成するデバイス区域とその周囲の区域の上に犠牲多結晶シリコン層を設け、一方、CMOSトランジスタを形成するデバイス区域にゲート導体を同時に設ける。次いで、ゲート導体それぞれのまわりにスペーサ30を設け、次いで、バイポーラ・デバイス区域上の犠牲多結晶シリコン層の一部を選択的に除去して、バイポーラ・トランジスタを形成するデバイス区域に開口部を設ける。次いで、開口部に、隆起外部ベース58を有するバイポーラ・トランジスタを形成する。
【選択図】図20
Description
基板上に設けられたゲート誘電体の表面上に多結晶シリコン層を形成するステップであって、前記基板が、少なくとも1個のバイポーラ・トランジスタを形成するデバイス区域と、少なくとも1個の相補型金属酸化物半導体(CMOS)トランジスタを形成するデバイス区域とを有するステップと、
前記多結晶シリコン層をパターン化して、少なくとも1個のバイポーラ・トランジスタを形成する前記デバイス区域の上に犠牲多結晶シリコン層を設け、一方、少なくとも1個のCMOSトランジスタを形成する前記デバイス区域に少なくとも1個のゲート導体を同時に設けるステップと、
少なくとも1個のゲート導体のそれぞれのまわりに少なくとも1対のスペーサを形成して、前記少なくとも1個のCMOSトランジスタを設けるステップと、
少なくとも1個のバイポーラ・トランジスタを形成する前記デバイス区域の上の前記犠牲多結晶シリコン層の一部を選択的に除去して、少なくとも1個の開口部を設けるステップと、
少なくとも1個の開口部に、隆起外部ベースを有する少なくとも1個のバイポーラ・トランジスタを形成するステップと
を含む方法、すなわちBiCMOS集積方式を提供する。
12 分離領域
14 バイポーラ・トランジスタ区域
16 CMOSトランジスタ・デバイス区域
18 ゲート誘電体
20 多結晶シリコン層
22 犠牲多結晶シリコン層
24 多結晶シリコン・ゲート誘電体
24’ 多結晶シリコン・ゲート誘電体
26 酸化物層
28 窒化物層(または多層)
30 酸化物スペーサ
32 各多結晶シリコン・ゲート間に存在するスペース
34 多結晶シリコン位置設定材料
36 第2酸化物層
38 第2多結晶シリコン層
40 キャップ酸化物層
41 開口部
42 ベース層
44 酸化物層
46 CVD多結晶シリコン層
48 開口部内のCVD多結晶シリコン層
50 フォトレジスト・マスク
52 CMPストップ層
54 エミッタ・ペデスタル・スタック
56 窒化物外部スペーサ
58 隆起外部ベース
60 酸化物分離層
62 置換内部窒化物スペーサ
63 コレクタ・コンタクト区域
64 フォトレジスト・マスク
66 エミッタ・多結晶シリコン層
68 窒化物層
Claims (21)
- BiCMOS集積回路の製作方法であって、
基板上に設けられたゲート誘電体の表面上に多結晶シリコン層を形成するステップであって、前記基板が、少なくとも1個のバイポーラ・トランジスタを形成するデバイス区域と、少なくとも1個の相補型金属酸化物半導体(CMOS)トランジスタを形成するデバイス区域とを有するステップと、
前記多結晶シリコン層をパターン化して、少なくとも1個のバイポーラ・トランジスタを形成する前記デバイス区域の上に犠牲多結晶シリコン層を設け、一方、少なくとも1個のCMOSトランジスタを形成する前記デバイス区域に少なくとも1個のゲート導体を同時に設けるステップと、
少なくとも1個のゲート導体のそれぞれのまわりに少なくとも1対のスペーサを形成して、前記少なくとも1個のCMOSトランジスタを設けるステップと、
少なくとも1個のバイポーラ・トランジスタを形成する前記デバイス区域の上の前記犠牲多結晶シリコン層の一部を選択的に除去して、少なくとも1個の開口部を設けるステップと、
少なくとも1個の開口部に、隆起外部ベースを有する少なくとも1個のバイポーラ・トランジスタを形成するステップと
を含む方法。 - 選択的に除去するステップを行う前に、CMOSゲートと犠牲多結晶シリコン層を含むパターン化多結晶シリコン層間のスペースを充填するステップをさらに含み、前記充填材料を後のステップで除去する、請求項1に記載の方法。
- 隆起外部ベースCMP工程の後で前記犠牲多結晶シリコン層を除去する、請求項1に記載の方法。
- 前記犠牲多結晶シリコン層を除去しない、請求項1に記載の方法。
- エミッタ・多結晶シリコンの付着前に犠牲多結晶シリコン層上の酸化物層と窒化物層をまず除去し、エミッタ・多結晶シリコンのエッチング時にエミッタ・多結晶シリコンと一緒に犠牲多結晶シリコン層を除去することによって、前記犠牲多結晶シリコン層を除去してエミッタを形成する、請求項3に記載の方法。
- 少なくとも1個のバイポーラ・トランジスタを形成することが、
前記少なくとも1個の開口部にエピタキシャル層を形成するステップと、
エピタキシャル層の上に酸化物を形成するステップと、
酸化物の上に誘電体層を形成するステップと、
開口部内にない誘電体層とその下にある膜の一部を除去し、保護酸化物層上で停止させて、開口部内の誘電体層の上面を、CMOSゲートと犠牲多結晶シリコンの上の保護酸化物層の上面と同じ高さにするステップと、
多結晶シリコン層の上にCMPストップ層を設けるステップと、
CMPストップ層の選択部分を保護するステップと、
隆起外部ベースと、この開口部に取り囲まれた、エミッタを形成する場所を保持するスタックとを形成するために、保護されていないCMPストップ層とその下の誘電体層の一部を除去するステップと、
露出した酸化物層を除去し、除去した区域に前記隆起外部ベースを形成するステップと、
まずブランケット酸化物層を付着させ、CMPプロセスを用いてCMPストップ層上の酸化膜を除去することによって、前記隆起外部ベースの上に酸化物分離層を形成するステップと、
前記スタックと前記下にある酸化物を除去するステップと、
前記スタックが以前占めていた区域にエミッタ・多結晶シリコンを形成するステップと
を含む、請求項1に記載の方法。 - 前記隆起外部ベースがシリコンまたはSiGeからなる、請求項6に記載の方法。
- まずブランケット外部ベース膜を付着させ、CMPプロセスを用いてCMPストップ層上の膜部分を除去し、前記膜を隆起外部ベース層の目標厚みまでリセスさせることによって隆起外部ベースを形成する、請求項6に記載の方法。
- 隆起外部ベースを選択的エピタキシによって形成する、請求項6に記載の方法。
- CMPストップ層が窒化物であり、CMPストップ層の付着前に付着させる誘電体層が多結晶シリコンまたは窒化物である、請求項6に記載の方法。
- 前記スタックが以前占めていた区域の露出側壁に置換内部窒化物スペーサを形成するステップをさらに含む、請求項6に記載の方法。
- 充填材料が多結晶シリコンであり、エミッタを形成するために多結晶シリコン・エッチング工程中に除去される、請求項2に記載の方法。
- 隆起外部ベースのCMP工程後に前記犠牲多結晶シリコン層を除去する、請求項2に記載の方法。
- 前記犠牲多結晶シリコン層を除去しない、請求項2に記載の方法。
- エミッタ・多結晶シリコンの付着前に犠牲多結晶シリコン層上の酸化物層と窒化物層をまず除去し、エミッタ・多結晶シリコンのエッチング時にエミッタ・多結晶シリコンと一緒に犠牲多結晶シリコン層を除去することによって、犠牲多結晶シリコン層を除去してエミッタを形成する、請求項13に記載の方法。
- 少なくとも1個のバイポーラ・トランジスタを形成することが、
少なくとも1個の開口部にエピタキシャル層を形成するステップと、
エピタキシャル層の上に酸化物を形成するステップと、
酸化物の上に誘電体層を形成するステップと、
開口部内にない誘電体層とその下にある膜の一部を除去し、保護酸化物層上で停止させて、開口部内の誘電体層の上面を、CMOSゲートと犠牲多結晶シリコン層の上の保護酸化物層の上面と同じ高さにするステップと、
犠牲多結晶シリコン層の上にCMPストップ層を設けるステップと、
前記CMPストップ層の選択部分を保護するステップと、
隆起外部ベースと、この開口部に取り囲まれた、エミッタを形成する場所を保持するスタックとを形成するために、保護されていないCMPストップ層とその下の誘電体層の一部を除去するステップと、
露出した酸化物層を除去し、除去した区域に前記隆起外部ベースを形成するステップと、
まずブランケット酸化物層を付着させ、CMPプロセスを用いてCMPストップ層上の酸化膜を除去することによって、前記隆起外部ベースの上に酸化物分離層を形成するステップと、
前記スタックと前記下にある酸化物を除去するステップと、
前記スタックが以前占めていた区域にエミッタ・多結晶シリコンを形成するステップと
を含む、請求項2に記載の方法。 - 前記隆起外部ベースがシリコンまたはSiGeからなる、請求項16に記載の方法。
- まずブランケット外部ベース膜を付着させ、CMPプロセスを用いてCMPストップ層上の膜部分を除去し、前記膜を隆起外部ベース層の目標厚みまでリセスさせることによって隆起外部ベースを形成する、請求項16に記載の方法。
- 隆起外部ベースを選択的エピタキシによって形成する、請求項16に記載の方法。
- CMPストップ層が窒化物であり、CMPストップ層の付着前に付着させる誘電体層が多結晶シリコンまたは窒化物である、請求項16に記載の方法。
- 前記スタックが以前占めていた区域の露出側壁に置換内部窒化物スペーサを形成するステップをさらに含む、請求項16に記載の方法。
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Cited By (3)
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JP2008021747A (ja) * | 2006-07-11 | 2008-01-31 | Asahi Kasei Electronics Co Ltd | 半導体装置の製造方法及び半導体装置 |
JP2008021746A (ja) * | 2006-07-11 | 2008-01-31 | Asahi Kasei Electronics Co Ltd | 半導体装置の製造方法 |
JP2009540596A (ja) * | 2006-06-14 | 2009-11-19 | エヌエックスピー ビー ヴィ | 半導体デバイスおよびこのようなデバイスの製造方法 |
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US20050145953A1 (en) * | 2004-01-05 | 2005-07-07 | Chartered Semiconductor Manufacturing Ltd | Heterojunction BiCMOS integrated circuits and method therefor |
US7291541B1 (en) | 2004-03-18 | 2007-11-06 | National Semiconductor Corporation | System and method for providing improved trench isolation of semiconductor devices |
US7060551B2 (en) * | 2004-06-18 | 2006-06-13 | Macronix International Co., Ltd. | Method of fabricating read only memory and memory cell array |
US7892910B2 (en) * | 2007-02-28 | 2011-02-22 | International Business Machines Corporation | Bipolar transistor with raised extrinsic self-aligned base using selective epitaxial growth for BiCMOS integration |
US7927958B1 (en) | 2007-05-15 | 2011-04-19 | National Semiconductor Corporation | System and method for providing a self aligned bipolar transistor using a silicon nitride ring |
US7910447B1 (en) | 2007-05-15 | 2011-03-22 | National Semiconductor Corporation | System and method for providing a self aligned bipolar transistor using a simplified sacrificial nitride emitter |
US7642168B1 (en) * | 2007-05-18 | 2010-01-05 | National Semiconductor Corporation | System and method for providing a self aligned bipolar transistor using a sacrificial polysilicon external base |
US7838375B1 (en) | 2007-05-25 | 2010-11-23 | National Semiconductor Corporation | System and method for providing a polyemit module for a self aligned heterojunction bipolar transistor architecture |
US7846806B1 (en) * | 2007-05-25 | 2010-12-07 | National Semiconductor Corporation | System and method for providing a self aligned silicon germanium (SiGe) heterojunction bipolar transistor using a mesa emitter-base architecture |
US7645666B2 (en) * | 2007-07-23 | 2010-01-12 | Infineon Technologies Ag | Method of making a semiconductor device |
US7790542B2 (en) * | 2008-06-18 | 2010-09-07 | International Business Machines Corporation | CMOS devices having reduced threshold voltage variations and methods of manufacture thereof |
CN102738153B (zh) * | 2012-07-16 | 2016-03-30 | 西安电子科技大学 | 一种SiGe HBT双应变平面BiCMOS集成器件及制备方法 |
DE102017216214B4 (de) * | 2017-09-13 | 2019-05-09 | Infineon Technologies Ag | Verfahren zur Herstellung eines kombinierten Halbleiterbauelements |
EP3671856B1 (en) | 2018-12-21 | 2023-01-25 | IMEC vzw | A method for forming a group iii-v heterojunction bipolar transistor on a group iv substrate and corresponding heterojunction bipolar transistor device |
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JP3003632B2 (ja) * | 1997-06-27 | 2000-01-31 | 日本電気株式会社 | 半導体集積回路およびその製造方法 |
US6117717A (en) * | 1999-06-07 | 2000-09-12 | Fairchild Semiconductor Corporation | Method for after gate implant of threshold adjust with low impact on gate oxide integrity |
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JP2008021747A (ja) * | 2006-07-11 | 2008-01-31 | Asahi Kasei Electronics Co Ltd | 半導体装置の製造方法及び半導体装置 |
JP2008021746A (ja) * | 2006-07-11 | 2008-01-31 | Asahi Kasei Electronics Co Ltd | 半導体装置の製造方法 |
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JP4148518B2 (ja) | 2008-09-10 |
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TWI283481B (en) | 2007-07-01 |
KR20040090695A (ko) | 2004-10-26 |
US6780695B1 (en) | 2004-08-24 |
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