JP4322706B2 - 半導体装置の製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 48
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims description 105
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 38
- 238000000034 method Methods 0.000 claims description 26
- 238000005468 ion implantation Methods 0.000 claims description 14
- 230000002093 peripheral effect Effects 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 181
- 239000010408 film Substances 0.000 description 35
- 239000013078 crystal Substances 0.000 description 18
- 230000008569 process Effects 0.000 description 14
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- 230000008859 change Effects 0.000 description 9
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- 238000010438 heat treatment Methods 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000000926 separation method Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000001451 molecular beam epitaxy Methods 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910052777 Praseodymium Inorganic materials 0.000 description 3
- 229910052787 antimony Inorganic materials 0.000 description 3
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- 238000009792 diffusion process Methods 0.000 description 3
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- 229910000420 cerium oxide Inorganic materials 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
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- 229910052732 germanium Inorganic materials 0.000 description 2
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- 229910052759 nickel Inorganic materials 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 229910052684 Cerium Inorganic materials 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910003855 HfAlO Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910021193 La 2 O 3 Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 229910004541 SiN Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
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- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- -1 oxygen ions Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910001404 rare earth metal oxide Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76267—Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
Description
J.Welser, J.L.Hoyl,S.Tagkagi, and J.F.Gibbons, IEDM 94-373 T.Mizuno et al., 11-3, 2002 Symposia on VLSI Tech.
図1は、本発明の第1の実施形態に係わる半導体装置の素子構造を示す断面図である。
図4は、本発明の第2の実施形態に係わる半導体装置の素子構造を示す断面図である。なお、図1と同一部分には同一符号を付して、その詳しい説明は省略する。
図5は、本発明の第3の実施形態に係わる半導体装置の素子構造を示す断面図である。なお、図1と同一部分には同一符号を付して、その詳しい説明は省略する。
図6は、本発明の第4の実施形態に係わる半導体装置の素子構造を示す断面図である。なお、図1と同一部分には同一符号を付して、その詳しい説明は省略する。
図7は、本発明の第5の実施形態に係わる半導体装置の素子構造を示す断面図である。なお、図1と同一部分には同一符号を付して、その詳しい説明は省略する。
図8は、本発明の第6の実施形態に係わる半導体装置の素子構造を示す断面図である。なお、図1と同一部分には同一符号を付して、その詳しい説明は省略する。
図9は、本発明の第7の実施形態に係わる半導体装置の素子構造を示す断面図である。なお、図1と同一部分には同一符号を付して、その詳しい説明は省略する。
なお、本発明は上述した各実施形態に限定されるものではない。実施形態では、半導体基板としてSi基板を用いたが、これに限らず他の半導体材料を用いることができる。即ち、半導体基板としては、Si,Ge,Ga,As,P,B,N,Sb,C,W,Ti,Ni,Ce,Sr,Pr,In,Al,N,Oの少なくとも一つを含む単層、或いは複数の層から形成されるものであればよい。より具体的には、SiGe,SiGeC,SiC,InGaAs,AlGaAs,GaN,GaAs,InAs,SiN等を用いることができる。さらに、追加の半導体層としても同様に、Si,Ge,Ga,As,P,B,N,Sb,C,W,Ti,Ni,Ce,Sr,Pr,In,Al,N,Oの少なくとも一つを含む単層、或いは複数の層から形成されるものを用いることが可能である。
11…絶縁層(第1の絶縁膜)
12…絶縁層(第2の絶縁膜)
13…Si分離層(島状半導体領域)
15…マスク
21,31…ゲート絶縁層
22,32…ゲート電極
23,33…ソース・ドレイン
24,34…層間絶縁膜
25,35…配線電極
41,51…再成長層
71…緩和SiGe層
72…歪みSi層
81…緩和SiGe層
82…歪みSi層
91…緩和SiGe層
92…低濃度Ge層
Claims (3)
- Si基板の表面部にSiGe層又はGe層を形成する工程と、
前記SiGe層又はGe層上に一部開口を有するマスクを形成する工程と、
前記基板の前記マスクで覆われていない露出表面から該基板内の所定深さ位置に酸素をイオン注入する工程と、
前記基板にアニール処理を施して前記イオン注入領域を酸化することにより、前記基板の表面から所定深さの位置に第1の絶縁膜を部分的に設けると共に、該第1の絶縁膜の周辺部から基板表面まで第2の絶縁膜を延長して設け、且つ前記第1及び第2の絶縁膜で囲まれた島状領域をSiGe層又はGe層にし、島状領域以外では前記SiGe層又はGe層のGeを前記基板中に拡散させることにより前記基板の表面部のGe濃度を1%以下にする工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記マスクの厚みを500〜2000nmに設定し、前記開口の側壁面を前記基板の表面と垂直に形成することを特徴とする請求項1記載の半導体装置の製造方法。
- 前記イオン注入に際して、前記基板の表面に対し斜め方向からイオン注入することを特徴とする請求項1又は2に記載の半導体装置の製造方法。
Priority Applications (2)
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JP2004053395A JP4322706B2 (ja) | 2004-02-27 | 2004-02-27 | 半導体装置の製造方法 |
US11/064,001 US20050189610A1 (en) | 2004-02-27 | 2005-02-24 | Semiconductor device and method of manufacturing the same |
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JP2004053395A JP4322706B2 (ja) | 2004-02-27 | 2004-02-27 | 半導体装置の製造方法 |
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JP2005244021A JP2005244021A (ja) | 2005-09-08 |
JP4322706B2 true JP4322706B2 (ja) | 2009-09-02 |
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DE102006015076B4 (de) * | 2006-03-31 | 2014-03-20 | Advanced Micro Devices, Inc. | Halbleiterbauelement mit SOI-Transistoren und Vollsubstrattransistoren und ein Verfahren zur Herstellung |
WO2007126907A1 (en) * | 2006-03-31 | 2007-11-08 | Advanced Micro Devices, Inc. | Semiconductor device comprising soi transistors and bulk transistors and a method of forming the same |
US7550795B2 (en) * | 2006-06-30 | 2009-06-23 | Taiwan Semiconductor Manufacturing | SOI devices and methods for fabricating the same |
CN102683289B (zh) * | 2012-05-04 | 2014-04-02 | 上海华力微电子有限公司 | 一种提高静态随机存储器写入冗余度的方法 |
US9929053B2 (en) | 2014-06-18 | 2018-03-27 | X-Celeprint Limited | Systems and methods for controlling release of transferable semiconductor structures |
US9613803B2 (en) * | 2015-04-30 | 2017-04-04 | International Business Machines Corporation | Low defect relaxed SiGe/strained Si structures on implant anneal buffer/strain relaxed buffer layers with epitaxial rare earth oxide interlayers and methods to fabricate same |
US10297502B2 (en) * | 2016-12-19 | 2019-05-21 | X-Celeprint Limited | Isolation structure for micro-transfer-printable devices |
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US5399507A (en) * | 1994-06-27 | 1995-03-21 | Motorola, Inc. | Fabrication of mixed thin-film and bulk semiconductor substrate for integrated circuit applications |
JP2806286B2 (ja) * | 1995-02-07 | 1998-09-30 | 日本電気株式会社 | 半導体装置 |
US5747860A (en) * | 1995-03-13 | 1998-05-05 | Nec Corporation | Method and apparatus for fabricating semiconductor device with photodiode |
US5847419A (en) * | 1996-09-17 | 1998-12-08 | Kabushiki Kaisha Toshiba | Si-SiGe semiconductor device and method of fabricating the same |
JP4258034B2 (ja) * | 1998-05-27 | 2009-04-30 | ソニー株式会社 | 半導体装置及び半導体装置の製造方法 |
US6246094B1 (en) * | 1998-10-20 | 2001-06-12 | Winbond Electronics Corporation | Buried shallow trench isolation and method for forming the same |
US6333532B1 (en) * | 1999-07-16 | 2001-12-25 | International Business Machines Corporation | Patterned SOI regions in semiconductor chips |
JP3998408B2 (ja) * | 2000-09-29 | 2007-10-24 | 株式会社東芝 | 半導体装置及びその製造方法 |
US6410371B1 (en) * | 2001-02-26 | 2002-06-25 | Advanced Micro Devices, Inc. | Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer |
JP4322453B2 (ja) * | 2001-09-27 | 2009-09-02 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP3943932B2 (ja) * | 2001-12-27 | 2007-07-11 | 株式会社東芝 | 半導体装置の製造方法 |
US6630714B2 (en) * | 2001-12-27 | 2003-10-07 | Kabushiki Kaisha Toshiba | Semiconductor device formed in semiconductor layer arranged on substrate with one of insulating film and cavity interposed between the substrate and the semiconductor layer |
JP2003203967A (ja) * | 2001-12-28 | 2003-07-18 | Toshiba Corp | 部分soiウェーハの製造方法、半導体装置及びその製造方法 |
JP2003243528A (ja) * | 2002-02-13 | 2003-08-29 | Toshiba Corp | 半導体装置 |
JP3506694B1 (ja) * | 2002-09-02 | 2004-03-15 | 沖電気工業株式会社 | Mosfetデバイス及びその製造方法 |
US6878611B2 (en) * | 2003-01-02 | 2005-04-12 | International Business Machines Corporation | Patterned strained silicon for high performance circuits |
AU2003202254A1 (en) * | 2003-01-08 | 2004-08-10 | International Business Machines Corporation | High performance embedded dram technology with strained silicon |
JP3974542B2 (ja) * | 2003-03-17 | 2007-09-12 | 株式会社東芝 | 半導体基板の製造方法および半導体装置の製造方法 |
JP2005072084A (ja) * | 2003-08-28 | 2005-03-17 | Toshiba Corp | 半導体装置及びその製造方法 |
US7034362B2 (en) * | 2003-10-17 | 2006-04-25 | International Business Machines Corporation | Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures |
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2004
- 2004-02-27 JP JP2004053395A patent/JP4322706B2/ja not_active Expired - Fee Related
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2005
- 2005-02-24 US US11/064,001 patent/US20050189610A1/en not_active Abandoned
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US20050189610A1 (en) | 2005-09-01 |
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