TW201424003A - 半導體裝置、鰭式場效電晶體裝置及其製造方法 - Google Patents

半導體裝置、鰭式場效電晶體裝置及其製造方法 Download PDF

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TW201424003A
TW201424003A TW102144553A TW102144553A TW201424003A TW 201424003 A TW201424003 A TW 201424003A TW 102144553 A TW102144553 A TW 102144553A TW 102144553 A TW102144553 A TW 102144553A TW 201424003 A TW201424003 A TW 201424003A
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field effect
effect transistor
fins
fin field
substrate
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TWI515904B (zh
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Wan-Te Chen
Chung-Hui Chen
Jaw-Juinn Horng
Po-Zeng Kang
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Taiwan Semiconductor Mfg
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Abstract

本發明實施例係揭露一種半導體裝置、一種鰭式場效電晶體裝置及一種鰭式場效電晶體裝置之製造方法。在一實施例中，半導體裝置包含一第一鰭式場效電晶體於一基材上，其中此第一鰭式場效電晶體包含一第一組半導體鰭。此半導體裝置更包含一用於該第一鰭式場效電晶體之一第一基體接觸於此基材上，其中此第一基體接觸包含一第二組半導體鰭，且其中此第一基體接觸與此第一鰭式場效電晶體側向相鄰。

Description

半導體裝置、鰭式場效電晶體裝置及其製造方法
本揭露係有關於半導體裝置，且特別是有關於鰭式場效電晶體裝置及製造方法。
電晶體為現今積體電路之關鍵元件。為了滿足日益增快的速度，電晶體之驅動電流亦需隨之增強。既然電晶體之驅動電流與電晶體之閘極寬度呈正相關，電晶體較佳需具有較寬的寬度。然而，閘極寬度的增加與半導體裝置尺寸微縮的需求相衝突。因此，發展出了鰭式場效電晶體。
在先進電路中，積體電路之操作頻率係在數百兆赫茲(MHz)至數千兆赫茲(GHz)。在這些先進電路中，時脈訊號(clock signal)的上升時間(rising time)極為短暫，使得電源供應線中的電壓波動極大。在電源供應線中，不欲產生的電壓波動可導致其內部訊號產生雜訊及雜訊邊限的衰減。雜訊邊限的衰減可能會降低電路之可靠度或甚至導至電路故障。
濾波電容或去耦電容可用以減少電源供應線中之電壓波動幅度。去耦電容作為電荷儲存庫(charge reservoirs)，在需要時額外提供電流至電路，以防止供應電壓瞬間下降。
為了整合去耦電容至其他電路中，去耦電容係放置於晶片上，例如使用薄膜平面式電容作為晶片上去耦電容 (on-chip decoupling capacitor)。然而，如欲具有足夠大的電容值，這些電容通常需要大面積，且難以設計及製造。
本揭露實施例係揭示一種半導體裝置，包含：一第一鰭式場效電晶體，位於一基材上，其中該第一鰭式場效電晶體包含一第一組半導體鰭；一用於該第一鰭式場效電晶體之第一基體接觸，位於該基材上，其中該第一基體接觸具有一第二組半導體鰭，且其中該第一基體接觸與該第一鰭式場效電晶體側向相鄰。
本揭露實施例亦揭示一種鰭式場效電晶體裝置，包含：一第一鰭式場效電晶體於一基材上，該第一鰭式場效電晶體包含：複數個第一鰭；及至少兩主動閘極於該些第一鰭上；以及一用於該第一鰭式場效電晶體之第一基體接觸位於該基材上，該第一基體接觸包含：複數個第二鰭；及至少兩主動閘極於該些第二鰭上。
本揭露實施例更揭露一種鰭式場效電晶體之製造方法，包含：形成一第一鰭式場效電晶體，包含：形成複數個第一鰭於一基材上；形成至少兩主動閘極於該些第一鰭上；及形成至少兩源極區及至少兩汲極區於該些第一鰭中；以及形成用於該第一鰭式場效電晶體之一第一基體接觸，包含：形成複數個第二鰭於該基材上；形成至少兩虛置閘極於該些第二鰭上；及形成至少兩基體接觸區於該些第二鰭中。
20‧‧‧半導體基材
22‧‧‧半導體層
24‧‧‧主動鰭
26‧‧‧基體接觸鰭
28‧‧‧鰭式場效電晶體
30‧‧‧基體接觸
32‧‧‧介電層
34‧‧‧虛置閘極
36‧‧‧虛置閘極
38‧‧‧主動閘極
40‧‧‧源極區
42‧‧‧汲極區
44‧‧‧基體接觸
46‧‧‧主動閘極
48‧‧‧基體接觸
50‧‧‧內嵌MOS變容器
100‧‧‧鰭式場效電晶體裝置
第1、2A-2B、3A-3B、4A-4B、5A-5B圖顯示依照本揭露一實施例之FinFET裝置於各中間製造過程之剖面圖及上視圖。
第6A及6B圖個自顯示為依照第5A圖所示之FinFET裝置之PMOS結構及NMOS結構之電路圖。
第7圖顯示依照本揭露另一實施例之具有內嵌變容器之FinFET裝置之上視圖。
第8A及8B圖各自顯示第7圖所示之FinFET裝置之PMOS結構及NMOS結構之電路圖。
以下將伴隨圖式介紹本揭露之一或多個實施例。只要有可能，圖式及說明書中所使用的相同參考標號係指稱相同或相似元件。在圖式中，形狀及厚度係經誇飾以便於清楚表示。說明書將特別依照本揭露之元件之製造方法及所使用之裝置作說明。可知的是，未特別顯示或說明之元件可為本領域具有通常知識者可知的任何形式。只要本揭露有提及，本領域具有通常知識者應可知道本揭露實施例之多種變化或修飾。
本說明書中所述之“一實施例(one embodiment or an embodiment)係指與特定元件、結構或特性有關聯之實施例，其係可包含於至少一實施例中。因此，當在本說明書各處出現“一實施例”時係不限於皆指向相同實施例。此外，在一或多個實施例中的特定的元件、結構或特性亦可以合適之方式作結合。可知的是，本案之圖式係未以等比例繪示，而是僅用於作舉例。
在此所述之實施例係針對特定內容，也就是具有 基體接觸(body contact)之鰭式場效電晶體(FinFET)裝置。或者，所述實施例亦可應用於具有內嵌變容器(embedded varactor)之其他鰭式場效電晶體(FinFET)結構。
第1圖顯示FinFET裝置100於製程中間階段之剖面 圖。FinFET裝置100包含一半導體層22於半導體基材20上。半導體基材20可包含摻雜或未摻雜之塊狀矽，或包含絕緣體上覆矽(SOI)基材之主動層。通常而言，絕緣體上覆矽基材包含一半導體材料層，例如矽、鍺、鍺化矽、絕緣體上覆矽、絕緣體上覆鍺化矽(SGOI)或前述之組合。或者，亦可使用其他基材，例如多層基材、梯度基材(gradient substrate)或混合定向基材(hybrid orientation substrate)。
半導體基材20可包含主動裝置(為了簡潔表示，未 顯示於第1圖中)。如本領域具有通常知識者可知的是，可使用各種裝置，例如電晶體、電容器、電阻器、前述之組合或其類似物，以滿足FinFET裝置100於設計上之結構需求或功能需求。FinFET 28可與主動或被動裝置電性連接。在圖式中，僅顯示了一部分的半導體基材20，其係已足以詳述本揭露之實施例。
半導體層22可由半導體材料形成，例如矽、鍺、 鍺化矽或前述之組合。在一實施例中，半導體層22為矽。接著，可由佈植製程導入p型或n型雜質至半導體層22中，形成摻雜之半導體層22。
第2A及2B圖顯示為將半導體層22予以圖案化，以 形成主動鰭24及基體接觸鰭26。第2A圖顯示為FinFET裝置100 之上視圖，第2B圖顯示為第2A圖中沿線段2B之剖面圖。此鰭之圖案化製程可藉由沉積罩幕材料(未顯示)完成，例如沉積光阻或氧化矽於半導體層22上。接著，將罩幕材料圖案化，並依照罩幕材料之圖案蝕刻半導體層22，得到包含複數個主動鰭24及複數個基體接觸鰭26形成於半導體層22中之結構。主動鰭24及基體接觸鰭26中之每一鰭具有與半導體基材20之頂面實質上正交之側壁。在某些實施例中，可蝕刻半導體層22至特定深度，也就是主動鰭24及基體接觸鰭26的高度。主動鰭24之高度h2為約10 nm至500 nm，基體接觸鰭26之高度h1為約10 nm至500 nm。在特定實施例中，主動鰭24之高度h2為約110 nm，且基體接觸鰭26之高度h1為約110 nm。主動鰭24之寬度w2為約5 nm至50 nm，基體接觸鰭26之寬度w1為約5 nm至50 nm。如第3A圖所示，主動鰭24之長度L1為約0.01 μm至10 μm，基體接觸鰭26之長度L2為約0.01 μm至10 μm。在其他實施例中，主動鰭24及基體接觸鰭26可自半導體基材20之頂面磊晶成長形成，例如自半導體基材20頂部之圖案化層中之溝槽或開口中作磊晶成長。由於上述製程係屬公開常識，其細節在此係不多作贅述。
主動鰭24用以作為即將形成之FinFET 28之鰭式結 構，而基體接觸鰭26用以作為基體接觸30之鰭式結構。每一FinFET 28可依FinFET裝置100之需求包含單個或多個主動鰭24。第1至5B圖顯示為形成兩個FinFET 28，其中每一FinFET 28具有四個主動鰭24，但不以此為限。類似地，基體接觸鰭26可依FinFET裝置100之需求包含單個或多個基體接觸鰭26，而不僅是第2A至5B圖所示之三個基體接觸鰭26。
參見第3A及3B圖，毯覆性沉積介電層32於FinFET 裝置100上。介電層32可由一或多種介電材料形成，例如包含氧化矽、氮化矽、低介電常數材料(例如碳摻雜之氧化物)、極低介電常數材料(例如多孔碳摻雜之二氧化矽)、聚合物(例如聚亞醯胺)、前述之組合或其類似物。介電層32可由例如化學氣相沉積(CVD)、玻璃旋塗或其他合適製程形成。
第4A及4B圖顯示製程之下一步驟，將介電層32薄 化至低於主動鰭24之頂部及基體接觸鰭26之頂部。介電層32可由任意方式作薄化。在一實施例中，可使用多步驟製程作薄化。例如，第一步驟包含化學機械研磨。於此化學機械研磨步驟中，係使用研磨漿與介電層32反應並將其研磨，持續至暴露出主動鰭24及基體接觸鰭26。接著，再以任意方式將主動鰭24及基體接觸鰭26薄化至低於主動鰭24之頂部及基體接觸鰭26之頂部。例如可使用稀氫氟酸或氫氟酸蒸氣作薄化處理，並持續一段合適時間。在另一實施例中，可略過化學機械研磨，且在不移除主動鰭24及基體接觸鰭26之情況下，選擇性薄化介電層32。上述選擇性薄化製程可包含進行前述之稀氫氟酸或氫氟酸蒸氣處理。
第5A及5B圖顯示為形成主動閘極38於主動鰭24 上、形成虛置閘極34於主動鰭24及基體接觸鰭26之末端上，及形成虛置閘極36於基體接觸鰭26上。虛置閘極34及36可具有與主動閘極38(參見第5A圖)不同的寬度及長度，或者，虛置閘極34及36可具有與主動閘極38相同的寬度及長度。主動閘極38及虛置閘極34、36可包含閘極介電層(未顯示)、閘極電極(未顯示) 及閘極間隔物(未顯示)。閘極介電層可由熱氧化法、化學氣相沉積、濺渡或其他任意已知方法及習知技藝中用以形成閘極介電層之方法。在其他實施例中，閘極介電層包含高介電常數介電材料，其介電常數(k值)大於3.9。這些高介電常數介電材料可包含氮化矽、氮氧化矽、如HfO2、HfZrOx、HfSiOx、HfTiOx、HfAlOx之金屬氧化物、其類似物或前述之組合，及前述之多層組合。
閘極電極層可形成於閘極介電層上。閘極電極層 可包含導電材料，且此導電材料可選自多晶矽(poly-Si)、多晶矽鍺(poly-SiGe)、金屬氮化物、金屬矽化物、金屬氧化物及金屬組成之群組。閘極電極層可由化學氣相沉積、濺渡、其他已知技術或習知技藝中用以沉積導電材料之技術形成。閘極電極層之頂面通常具有非平坦之頂面。可在圖案化閘極電極層或進行閘極蝕刻之前將此非平坦之頂面平坦化。此時，可導入或不導入離子至閘極電極層中。導入離子之製程可例如為離子佈植製程。閘極電極層及閘極介電層可經圖案化以形成主動閘極38及虛置閘極34及36。閘極圖案化製程可由沉積罩幕材料(未顯示)於閘極電極層上完成，罩幕材料可例如為光阻或氧化矽。 接著，將罩幕材料圖案化，並依依罩幕材料之圖案蝕刻閘極電極層。
在形成主動閘極38及虛置閘極34及36之後，可形成源極區40及極區42於主動鰭24上。可藉由進行佈植製程佈植摻質，補充摻質至主動鰭24中，以形成摻雜之源極區40及汲極區42。在另一實施例中，源極區40及汲極區42可由形成凹陷(未 顯示)於主動鰭24中，並於凹陷中磊晶成長材料形成。源極區40及汲極區42皆可以上述之方式作摻雜，或可在磊晶成長時作原位(in-situ)摻雜。位於主動鰭24及基體接觸鰭26末端上之虛置閘極34可用以控制源極區40、汲極區42及基體接觸44之磊晶成長。在一實施例中，一連續的金屬層覆於每一汲極區42中的四個主動鰭24上，以在每一FinFET 28中形成兩汲極區。
在第5A及5B圖所示之實施例中，FinFET 28可應用 於PMOS或NMOS結構中。在PMOS結構中，主動鰭24可摻有n型摻質，基體接觸鰭26可摻有n型摻質，源極區40及汲極區42可摻有p型摻質，且基體接觸44可摻有n型摻質。在NMOS結構中，主動鰭24摻有p型摻質，基體接觸鰭26可摻有p型摻質，源極區40及汲極區42可摻有n型摻質，且基體接觸44可摻有p型摻質。
閘極間隔物可形成於主動閘極38之兩側及虛置閘 極34、36之兩側。閘極間隔物(未顯示)通常由毯覆式沉積間隔層(未顯示)形成於先前形成之結構上。間隔物可包含氮化矽、氮氧化物、碳化矽、氮氧化矽、氧化物或其類似物，其可由用以可形成膜層之方法形成，例如化學氣相沉積、電漿增強式化學氣相沉積、濺渡或其他已知之方法。接著，將閘極間隔物圖案化，較佳以非等向性蝕刻自結構之水平表面移除間隔物層。
在另一實施例中，源極區40及汲極區42可包含輕 摻雜區及重摻雜區。在此實施例中，在成閘極間隔物之前，對源極區40及汲極區42作輕摻雜。接著，在形成間隔物之後，對源極區40及汲極區42作重摻雜，形成輕摻雜區及重摻雜區。基 本上，輕摻雜區可位於閘極間隔物下方，而重摻雜區位係沿主動鰭24位於閘極間隔物之外。
第6A及6B圖各自顯示第5A及5B圖所示之FinFETs 28於PMOS結構及NMOS結構中之電路符號。兩者之電路圖皆顯示為主動電極38連接至閘極端(gate terminal)，汲極區42連接至汲極端(drain terminal)，且基體接觸44連接至基體端(body terminal)。
第7圖顯示FinFET裝置100之另一實施例，其中基 體接觸鰭26具有主動閘極46形成於其上。主動閘極46之寬度及長度可與主動閘極38不同。或者，主動閘極46之寬度及長度可與主動閘極38相同(參見第7圖)。於基體接觸鰭26上之主動閘極46可形成內嵌MOS變容器50，其可作為去耦電容。在此內嵌MOS變容器50作為去耦電容之實施例中，主動閘極46可連接至偏壓節點(bias node)，其可改變內嵌MOS變容器之電容。此外，在此內嵌MOS變容器之NMOS結構中，主動閘極46可連接至接地節點(ground node)以作為去耦電容。此外，在此內嵌MOS變容器50之PMOS結構中，主動閘極46可連接至電源節點(power node)以作為去耦電容。
在第7圖所示之實施例中，此FinFET 28及內嵌MOS 變容器50皆可應用於PMOS或NMOS結構中。在一實施例中，FinFET 28為PMOS，且內嵌MOS變容器50為NMOS，主動鰭24可摻有n型摻質，基體接觸鰭26可摻有n型摻質，源極區40及汲極區42可摻有p型摻質，基體接觸48可摻有n型摻質。在另一實施例中，FinFET 28為NMOS，且內嵌MOS變容器50為PMOS， 主動鰭24可摻有p型摻質，基體接觸鰭26可摻有p型摻質，源極區40及汲極區42可摻有n型摻質，基體接觸48可摻有p型摻質。
第8A及8B圖顯示第7圖所示之FinFET 28及內嵌之 MOS變容器50應用於PMOS及NMOS結構之電路符號。在第8A圖中，FinFET 28為PMOS，且內嵌MOS變容器50為NMOS。在第8B圖中，FinFET 28為NMOS，而內嵌MOS變容器50為PMOS。 兩電路圖皆顯示主動閘極38連接至FinFET 28之閘極端，源極區40連接至FinFET 28之源極端，汲極區42連接至FinFET 28之汲極端，基體接觸48連接至FinFET 28之基體端。在一實施例中，FinFET 28為PMOS且內嵌MOS變容器50為NMOS之實施例中(參見第8A圖)，主動閘極46可連接至偏壓節點或接地節點，以形成去耦電容。在另一實施例中，FinFET 28為NMOS且內嵌MOS變容器50為PMOS(參見第8B圖)，主動閘極46可連接至偏壓節點或電源節點，以形成去耦電容。
藉由替換基體接觸鰭26上之虛置閘極36為主動閘 極46以形成內嵌MOS變容器50，主動閘極46之材料可例如用於形成去耦電容，因而可降低FinFET裝置100之成本。此外，亦藉由將必要的電容內嵌至基體接觸鰭26及其上之閘極之已存在的結構中，FinFET裝置100之總面積得以縮減。
雖然本發明已以較佳實施例揭露如上，然其並非 用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬 技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍應以較寬廣的範圍或意義來解讀。
34‧‧‧虛置閘極
36‧‧‧虛置閘極
38‧‧‧主動閘極
40‧‧‧源極區
42‧‧‧汲極區
44‧‧‧基體接觸
100‧‧‧鰭式場效電晶體裝置

Claims (10)

  1. 一種半導體裝置，包含：一第一鰭式場效電晶體，位於一基材上，其中該第一鰭式場效電晶體包含一第一組半導體鰭；以及一用於該第一鰭式場效電晶體之第一基體接觸，位於該基材上，其中該第一基體接觸具有一第二組半導體鰭，且其中該第一基體接觸與該第一鰭式場效電晶體側向相鄰(laterally adjacent)。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該第一組半導體鰭包含至少兩半導體鰭，且其中該第二組半導體鰭包含第少兩半導體鰭，其中該第一組半導體鰭係與該第二組半導體鰭平行。
  3. 如申請專利範圍第1項所述之半導體裝置，其中該第一鰭式場效電晶體更包含至少一第一主動閘極及至少一虛置閘極於其上，其中該至少一第一主動閘極具有一第一長度及一第一寬度，且其中該第一基體接觸更包含至少一具有一第二寬度及第二長度之虛置閘極於該第二組半導體鰭上，其中該第一寬度與該第二寬度相同，該第一長度與該第二長度相同。
  4. 如申請專利範圍第1項所述之半導體裝置，其中該第一鰭式場效電晶體更包含至少兩源極區及至少兩汲極區，其中該些源極區及該些汲極區由一主動閘極所分隔。
  5. 如申請專利範圍第1項所述之半導體裝置，更包含：一第二鰭式場效電晶體，位於該基材上，其中該第二鰭式 場效電晶體包含一第三組半導體鰭，且其中該第二鰭式場效電晶體在一與該基體接觸相反之方向上與該第一鰭式場效電晶體側向相鄰；以及用於該第二鰭式場效電晶體之一第二基體接觸，位於該基材上，其中該第二基體接觸包含一第四組半導體鰭，其中該第二基體接觸在一與該第一鰭式場效電晶體相反之方向上與該第二鰭式場效電晶體側向相鄰。
  6. 一種鰭式場效電晶體裝置，包含：一第一鰭式場效電晶體於一基材上，該第一鰭式場效電晶體包含：複數個第一鰭；至少兩主動閘極於該些第一鰭上；以及一用於該第一鰭式場效電晶體之第一基體接觸位於該基材上，該第一基體接觸包含：複數個第二鰭；以及至少兩主動閘極於該些第二鰭上。
  7. 如申請專利範圍第6項所述之鰭式場效電晶體裝置，其中位於該些第二鰭上之該至少兩主動閘極形成一MOS變容器。
  8. 如申請專利範圍第6項所述之鰭式場效電晶體裝置，其中該第一基體接觸之該至少兩主動閘極與一偏壓節點電性連接，形成一去耦電容。
  9. 如申請專利範圍第6項所述之鰭式場效電晶體裝置，其中該第一基體接觸之該至少兩主動閘極係與一接地節點或一電源節點電性連接，形成一去耦電容。
  10. 一種鰭式場效電晶體之製造方法，包含：形成一第一鰭式場效電晶體，包含：形成複數個第一鰭於一基材上；形成至少兩主動閘極於該些第一鰭上；形成至少兩源極區及至少兩汲極區於該些第一鰭中；以及形成用於該第一鰭式場效電晶體之一第一基體接觸，包含：形成複數個第二鰭於該基材上；形成至少兩虛置閘極於該些第二鰭上；以及形成至少兩基體接觸區於該些第二鰭中。
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