CN103227115B - 引线框及其制造方法和半导体装置及其制造方法 - Google Patents
引线框及其制造方法和半导体装置及其制造方法 Download PDFInfo
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- CN103227115B CN103227115B CN201310031813.2A CN201310031813A CN103227115B CN 103227115 B CN103227115 B CN 103227115B CN 201310031813 A CN201310031813 A CN 201310031813A CN 103227115 B CN103227115 B CN 103227115B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 239000011347 resin Substances 0.000 claims abstract description 33
- 229920005989 resin Polymers 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims description 53
- 238000007789 sealing Methods 0.000 abstract description 17
- 238000003825 pressing Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 230000006978 adaptation Effects 0.000 description 6
- 238000004873 anchoring Methods 0.000 description 5
- 239000010949 copper Substances 0.000 description 2
- 230000000994 depressogenic effect Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012-018461 | 2012-01-31 | ||
JP2012018461A JP5833459B2 (ja) | 2012-01-31 | 2012-01-31 | リードフレーム及びその製造方法と半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103227115A CN103227115A (zh) | 2013-07-31 |
CN103227115B true CN103227115B (zh) | 2017-04-12 |
Family
ID=48837510
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201310031813.2A Active CN103227115B (zh) | 2012-01-31 | 2013-01-28 | 引线框及其制造方法和半导体装置及其制造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8778739B2 (enrdf_load_stackoverflow) |
JP (1) | JP5833459B2 (enrdf_load_stackoverflow) |
KR (1) | KR101957257B1 (enrdf_load_stackoverflow) |
CN (1) | CN103227115B (enrdf_load_stackoverflow) |
TW (1) | TWI574366B (enrdf_load_stackoverflow) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2015125352A1 (ja) * | 2014-02-24 | 2015-08-27 | 三菱電機株式会社 | パワー半導体モジュールおよびパワーユニット |
JP6408431B2 (ja) * | 2015-06-11 | 2018-10-17 | Shプレシジョン株式会社 | リードフレーム、リードフレームの製造方法、および半導体装置 |
JP2017208486A (ja) * | 2016-05-19 | 2017-11-24 | 株式会社ミスズ工業 | 表面に凹凸を有する金属部材、ヒートスプレッダ、半導体パッケージ及びそれらの製造方法 |
TWI623076B (zh) * | 2016-11-02 | 2018-05-01 | 復盛精密工業股份有限公司 | 導線架製作方法 |
US10998255B2 (en) | 2018-07-12 | 2021-05-04 | Nxp Usa, Inc. | Overmolded microelectronic packages containing knurled flanges and methods for the production thereof |
TWI690045B (zh) * | 2018-08-03 | 2020-04-01 | 欣興電子股份有限公司 | 構裝結構、其接合方法及用於其的線路板 |
SG11202102415XA (en) * | 2018-09-11 | 2021-04-29 | Rjr Technologies Inc | Air cavity package with improved connections between components |
JP2021034705A (ja) * | 2019-08-29 | 2021-03-01 | Jx金属株式会社 | 金属板、金属樹脂複合体、半導体デバイス及び、金属板の製造方法 |
CN118974917A (zh) * | 2022-10-25 | 2024-11-15 | 富士电机株式会社 | 半导体模块、半导体装置以及车辆 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04117454U (ja) * | 1991-03-29 | 1992-10-21 | サンケン電気株式会社 | 絶縁物被覆電子部品 |
JPH07161896A (ja) * | 1993-12-02 | 1995-06-23 | Hitachi Cable Ltd | リードフレームとその製造方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6378558A (ja) * | 1986-09-22 | 1988-04-08 | Hitachi Ltd | 電子装置 |
JPS6442847A (en) * | 1987-08-10 | 1989-02-15 | Toshiba Corp | Lead frame |
JPH077122A (ja) * | 1993-06-17 | 1995-01-10 | Fujitsu Ltd | Icパッケージ |
JP3339173B2 (ja) | 1994-04-01 | 2002-10-28 | 松下電器産業株式会社 | リードフレーム及びその製造方法及びそれを用いた半導体装置 |
JPH0864739A (ja) * | 1994-08-24 | 1996-03-08 | Hitachi Cable Ltd | ディンプル加工を施したリードフレームの製造方法及びそのディンプル加工金型 |
JPH0864749A (ja) * | 1994-08-25 | 1996-03-08 | Hitachi Cable Ltd | リードフレーム |
US6294409B1 (en) * | 2000-01-27 | 2001-09-25 | Siliconware Precisionware Industries Co., Ltd. | Method of forming a constricted-mouth dimple structure on a leadframe die pad |
US7091602B2 (en) * | 2002-12-13 | 2006-08-15 | Freescale Semiconductor, Inc. | Miniature moldlocks for heatsink or flag for an overmolded plastic package |
US7109570B2 (en) * | 2003-09-08 | 2006-09-19 | United Test And Assembly Test Center Ltd. | Integrated circuit package with leadframe enhancement and method of manufacturing the same |
US7476602B2 (en) * | 2005-01-31 | 2009-01-13 | Texas Instruments Incorporated | N2 based plasma treatment for enhanced sidewall smoothing and pore sealing porous low-k dielectric films |
JP2009260282A (ja) | 2008-03-18 | 2009-11-05 | Panasonic Corp | パッケージ用リードフレーム |
US7955954B2 (en) * | 2008-04-14 | 2011-06-07 | Infineon Technologies Ag | Method of making semiconductor devices employing first and second carriers |
-
2012
- 2012-01-31 JP JP2012018461A patent/JP5833459B2/ja active Active
-
2013
- 2013-01-24 KR KR1020130007821A patent/KR101957257B1/ko active Active
- 2013-01-28 CN CN201310031813.2A patent/CN103227115B/zh active Active
- 2013-01-28 TW TW102103092A patent/TWI574366B/zh active
- 2013-01-28 US US13/751,609 patent/US8778739B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04117454U (ja) * | 1991-03-29 | 1992-10-21 | サンケン電気株式会社 | 絶縁物被覆電子部品 |
JPH07161896A (ja) * | 1993-12-02 | 1995-06-23 | Hitachi Cable Ltd | リードフレームとその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
TWI574366B (zh) | 2017-03-11 |
JP2013157536A (ja) | 2013-08-15 |
KR20130088773A (ko) | 2013-08-08 |
US20130193567A1 (en) | 2013-08-01 |
CN103227115A (zh) | 2013-07-31 |
JP5833459B2 (ja) | 2015-12-16 |
TW201347123A (zh) | 2013-11-16 |
KR101957257B1 (ko) | 2019-03-13 |
US8778739B2 (en) | 2014-07-15 |
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