CN102859649B - 外延硅晶片及其制造方法、以及贴合soi晶片及其制造方法 - Google Patents
外延硅晶片及其制造方法、以及贴合soi晶片及其制造方法 Download PDFInfo
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- CN102859649B CN102859649B CN201180017235.6A CN201180017235A CN102859649B CN 102859649 B CN102859649 B CN 102859649B CN 201180017235 A CN201180017235 A CN 201180017235A CN 102859649 B CN102859649 B CN 102859649B
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- wafer
- epitaxial
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- soi
- layer
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
- H10P14/2901—Materials
- H10P14/2902—Materials being Group IVA materials
- H10P14/2905—Silicon, silicon germanium or germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
- H10P14/2926—Crystal orientations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
- H10P14/3411—Silicon, silicon germanium or germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3438—Doping during depositing
- H10P14/3441—Conductivity type
- H10P14/3442—N-type
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
- H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
Landscapes
- Recrystallisation Techniques (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010-085381 | 2010-04-01 | ||
| JP2010085381A JP5544986B2 (ja) | 2010-04-01 | 2010-04-01 | 貼り合わせｓｏｉウェーハの製造方法、及び貼り合わせｓｏｉウェーハ |
| PCT/JP2011/001175 WO2011125282A1 (ja) | 2010-04-01 | 2011-03-01 | シリコンエピタキシャルウェーハ及びその製造方法、並びに貼り合わせｓｏｉウェーハ及びその製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102859649A CN102859649A (zh) | 2013-01-02 |
| CN102859649B true CN102859649B (zh) | 2015-06-24 |
Family
ID=44762253
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201180017235.6A Active CN102859649B (zh) | 2010-04-01 | 2011-03-01 | 外延硅晶片及其制造方法、以及贴合soi晶片及其制造方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US8823130B2 (https=) |
| EP (1) | EP2555227B1 (https=) |
| JP (1) | JP5544986B2 (https=) |
| KR (1) | KR101729474B1 (https=) |
| CN (1) | CN102859649B (https=) |
| WO (1) | WO2011125282A1 (https=) |
Families Citing this family (36)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6200273B2 (ja) * | 2013-10-17 | 2017-09-20 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
| US20150270344A1 (en) * | 2014-03-21 | 2015-09-24 | International Business Machines Corporation | P-fet with graded silicon-germanium channel |
| CN103871902A (zh) | 2014-03-24 | 2014-06-18 | 上海华力微电子有限公司 | 半导体处理工艺及半导体器件的制备方法 |
| CN105869991B (zh) | 2015-01-23 | 2018-05-11 | 上海华力微电子有限公司 | 用于改善SiGe厚度的均匀性的方法和系统 |
| CN105990172B (zh) | 2015-01-30 | 2018-07-31 | 上海华力微电子有限公司 | 嵌入式SiGe外延测试块的设计 |
| CN105990342B (zh) | 2015-02-13 | 2019-07-19 | 上海华力微电子有限公司 | 具有用于嵌入锗材料的成形腔的半导体器件及其制造工艺 |
| CN104851884A (zh) | 2015-04-14 | 2015-08-19 | 上海华力微电子有限公司 | 用于锗硅填充材料的成形腔 |
| CN104821336B (zh) | 2015-04-20 | 2017-12-12 | 上海华力微电子有限公司 | 用于使用保形填充层改善器件表面均匀性的方法和系统 |
| FR3036845B1 (fr) * | 2015-05-28 | 2017-05-26 | Soitec Silicon On Insulator | Procede de transfert d'une couche d'un substrat monocristallin |
| CN105097554B (zh) | 2015-08-24 | 2018-12-07 | 上海华力微电子有限公司 | 用于减少高浓度外延工艺中的位错缺陷的方法和系统 |
| EP3179093A1 (en) * | 2015-12-08 | 2017-06-14 | Winfoor AB | Rotor blade for a wind turbine and a sub-member |
| JP6474048B2 (ja) * | 2015-12-25 | 2019-02-27 | 信越半導体株式会社 | エピタキシャルウェーハの製造方法 |
| DE112017004005B4 (de) * | 2016-08-10 | 2024-07-18 | Sumco Corporation | Verfahren zur herstellung von siliziumepitaxialwafern |
| SG11201901194SA (en) * | 2016-08-12 | 2019-03-28 | Qorvo Us Inc | Wafer-level package with enhanced performance |
| JP6662250B2 (ja) * | 2016-09-07 | 2020-03-11 | 信越半導体株式会社 | シリコンエピタキシャルウェーハの製造方法及び半導体デバイスの製造方法 |
| JP6973475B2 (ja) * | 2017-04-06 | 2021-12-01 | 株式会社Sumco | エピタキシャルシリコンウェーハの製造方法およびエピタキシャルシリコンウェーハ |
| US11152363B2 (en) | 2018-03-28 | 2021-10-19 | Qorvo Us, Inc. | Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process |
| US12062700B2 (en) | 2018-04-04 | 2024-08-13 | Qorvo Us, Inc. | Gallium-nitride-based module with enhanced electrical performance and process for making the same |
| US12046505B2 (en) | 2018-04-20 | 2024-07-23 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation |
| WO2020009759A1 (en) | 2018-07-02 | 2020-01-09 | Qorvo Us, Inc. | Rf semiconductor device and manufacturing method thereof |
| US11646242B2 (en) | 2018-11-29 | 2023-05-09 | Qorvo Us, Inc. | Thermally enhanced semiconductor package with at least one heat extractor and process for making the same |
| US12046483B2 (en) | 2019-01-23 | 2024-07-23 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
| US11387157B2 (en) | 2019-01-23 | 2022-07-12 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
| US12125825B2 (en) | 2019-01-23 | 2024-10-22 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
| WO2020153983A1 (en) | 2019-01-23 | 2020-07-30 | Qorvo Us, Inc. | Rf semiconductor device and manufacturing method thereof |
| US12057374B2 (en) | 2019-01-23 | 2024-08-06 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
| US12046570B2 (en) | 2019-01-23 | 2024-07-23 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
| US12074086B2 (en) | 2019-11-01 | 2024-08-27 | Qorvo Us, Inc. | RF devices with nanotube particles for enhanced performance and methods of forming the same |
| US11646289B2 (en) | 2019-12-02 | 2023-05-09 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
| US11923238B2 (en) | 2019-12-12 | 2024-03-05 | Qorvo Us, Inc. | Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive |
| US12129168B2 (en) | 2019-12-23 | 2024-10-29 | Qorvo Us, Inc. | Microelectronics package with vertically stacked MEMS device and controller device |
| DE102020209092A1 (de) * | 2020-07-21 | 2022-01-27 | Sicrystal Gmbh | Kristallstrukturorientierung in Halbleiter-Halbzeugen und Halbleitersubstraten zum Verringern von Sprüngen und Verfahren zum Einstellen von dieser |
| WO2022126016A2 (en) | 2020-12-11 | 2022-06-16 | Qorvo Us, Inc. | Multi-level 3d stacked package and methods of forming the same |
| US12062571B2 (en) | 2021-03-05 | 2024-08-13 | Qorvo Us, Inc. | Selective etching process for SiGe and doped epitaxial silicon |
| KR20240169859A (ko) * | 2023-05-25 | 2024-12-03 | 삼성전자주식회사 | 반도체 소자 |
| US20250069945A1 (en) * | 2023-08-24 | 2025-02-27 | Globalwafers Co., Ltd. | Methods of preparing silicon-on-insulator structures using epitaxial wafers |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06338464A (ja) * | 1993-05-31 | 1994-12-06 | Toshiba Corp | 半導体装置用基板 |
| CN101151708A (zh) * | 2005-04-06 | 2008-03-26 | 信越半导体股份有限公司 | Soi晶圆制造方法及用该方法制造的soi晶圆 |
| JP2008159667A (ja) * | 2006-12-21 | 2008-07-10 | Siltronic Ag | Ｓｏｉ基板及びｓｏｉ基板の製造方法 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62226891A (ja) * | 1986-03-28 | 1987-10-05 | Shin Etsu Handotai Co Ltd | 半導体装置用基板 |
| JPH03194921A (ja) * | 1989-12-22 | 1991-08-26 | Showa Denko Kk | 半導体エピタキシャルウェハー及びその製造方法 |
| JP2772183B2 (ja) * | 1991-11-30 | 1998-07-02 | 東芝セラミックス株式会社 | シリコンウェハの製造方法 |
| JP2000260711A (ja) * | 1999-03-11 | 2000-09-22 | Toshiba Corp | 半導体基板製造方法 |
| JP2001274049A (ja) * | 2000-03-27 | 2001-10-05 | Toshiba Microelectronics Corp | 半導体基板及びその製造方法 |
| US6743495B2 (en) * | 2001-03-30 | 2004-06-01 | Memc Electronic Materials, Inc. | Thermal annealing process for producing silicon wafers with improved surface characteristics |
| JP2003204048A (ja) | 2002-01-09 | 2003-07-18 | Shin Etsu Handotai Co Ltd | Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ |
| JP4089354B2 (ja) * | 2002-08-30 | 2008-05-28 | 株式会社Ｓｕｍｃｏ | エピタキシャルウェーハとその製造方法 |
| JP2004339003A (ja) | 2003-05-15 | 2004-12-02 | Shin Etsu Handotai Co Ltd | シリコンエピタキシャルウェーハ及びシリコンエピタキシャルウェーハの製造方法 |
| JP4423903B2 (ja) * | 2003-07-17 | 2010-03-03 | 信越半導体株式会社 | シリコンエピタキシャルウェーハ及びその製造方法 |
| JP2008171958A (ja) * | 2007-01-10 | 2008-07-24 | Hitachi Kokusai Electric Inc | 半導体装置の製造方法 |
-
2010
- 2010-04-01 JP JP2010085381A patent/JP5544986B2/ja active Active
-
2011
- 2011-03-01 WO PCT/JP2011/001175 patent/WO2011125282A1/ja not_active Ceased
- 2011-03-01 EP EP11765184.4A patent/EP2555227B1/en active Active
- 2011-03-01 KR KR1020127024972A patent/KR101729474B1/ko active Active
- 2011-03-01 US US13/582,614 patent/US8823130B2/en active Active
- 2011-03-01 CN CN201180017235.6A patent/CN102859649B/zh active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06338464A (ja) * | 1993-05-31 | 1994-12-06 | Toshiba Corp | 半導体装置用基板 |
| CN101151708A (zh) * | 2005-04-06 | 2008-03-26 | 信越半导体股份有限公司 | Soi晶圆制造方法及用该方法制造的soi晶圆 |
| JP2008159667A (ja) * | 2006-12-21 | 2008-07-10 | Siltronic Ag | Ｓｏｉ基板及びｓｏｉ基板の製造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2011125282A1 (ja) | 2011-10-13 |
| EP2555227A1 (en) | 2013-02-06 |
| JP2011216780A (ja) | 2011-10-27 |
| CN102859649A (zh) | 2013-01-02 |
| US20120326268A1 (en) | 2012-12-27 |
| US8823130B2 (en) | 2014-09-02 |
| KR20130023207A (ko) | 2013-03-07 |
| EP2555227B1 (en) | 2019-07-03 |
| EP2555227A4 (en) | 2015-08-26 |
| KR101729474B1 (ko) | 2017-04-24 |
| JP5544986B2 (ja) | 2014-07-09 |
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