CN102738040B - 用于处理半导体晶圆或裸片的方法和粒子沉积设备 - Google Patents
用于处理半导体晶圆或裸片的方法和粒子沉积设备 Download PDFInfo
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- CN102738040B CN102738040B CN201210098988.0A CN201210098988A CN102738040B CN 102738040 B CN102738040 B CN 102738040B CN 201210098988 A CN201210098988 A CN 201210098988A CN 102738040 B CN102738040 B CN 102738040B
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Classifications
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Abstract
本发明涉及用于处理半导体晶圆或裸片的方法和粒子沉积设备。根据各种实施例,提供了一种用于处理半导体晶圆或裸片的方法,包括将粒子提供到等离子体以使得通过等离子体激活所述粒子并且将激活的粒子喷射在半导体晶圆或裸片上以在半导体晶圆或裸片上生成粒子层。
Description
技术领域
实施例大体涉及用于处理半导体晶圆(wafer)或裸片(die)的方法、半导体晶圆或裸片以及粒子(particle)沉积设备。
背景技术
在半导体芯片的制造中,典型地执行涉及在现有层上沉积粒子层的处理。这可以包括金属化层以用于互连或接合(bonding)并且还包括对材料进行沉积以用于焊接等等。所希望的是用于粒子沉积和对所沉积的粒子层进行图案化(pattern)的高效方法。
附图说明
此外,在附图中,同样的附图标记贯穿不同的视图一般指代相同部分。所述附图不一定按比例绘制,而是重点主要在于说明本发明的原理。在下文的描述中,参照附图描述各种实施例,其中:
图1示出粒子沉积设备。
图2示出粒子沉积设备。
图3示出根据实施例的流程图。
图4示出根据实施例的晶圆的顶视图。
图5示出晶圆的横截面视图。
图6示出膜应力图。
图7示出使用如图3中图示的方法沉积的金属膜的结构。
图8示出了电阻率图。
图9A到9D示出了晶圆加固(reinforcement)过程的各阶段。
图10A到10E示出了晶圆加固过程的各阶段。
图11示出根据实施例的流程图。
图12示出了根据实施例的裸片的横截面。
图13图示了处理半导体晶圆的方法。
图14A到14E示出了图案化金属层形成过程的各阶段。
图15A到15E示出了图案化金属层形成过程的各阶段。
图16示出根据实施例的粒子沉积设备。
图17示出根据各种实施例的孔(aperture)形状。
图18示出根据实施例的互连形成布置。
具体实施方式
以下详细说明参照附图进行,所述附图通过例示而示出了其中可以实践本发明的具体细节和实施例。这些实施例被足够详细地描述以使得本领域技术人员能够实践本发明。可以利用其他实施例并且可以在不偏离本发明的范围的情况下做出结构、逻辑和电气改变。各种实施例不一定是互斥的,因为一些实施例可以与一个或多个其他实施例相结合以形成新的实施例。
等离子体沉积
根据各种实施例,等离子体沉积方法可以用于在例如半导体晶圆或裸片上沉积粒子。在这种根据各种实施例所使用的方法中,将粒子(即待沉积的粒子)提供到等离子体以使得通过等离子体激活所述粒子,并且在其上要沉积粒子的表面(例如半导体晶圆或裸片的表面)上喷射激活的粒子。
在各种实施例中,等离子体射流沉积方法被用作等离子体沉积方法。这意味着,根据各种实施例,等离子体射流用于在例如半导体晶圆或裸片上沉积粒子。
等离子体射流可以被理解为具有例如从生成等离子体射流的设备延伸出的射流或射束的形式的等离子体流或等离子流。射流形式的等离子体的生成可以使用介质阻挡放电或电弧放电来实现。
在下文中参考图1描述了粒子沉积设备的示例,在该设备中,将粒子(即待沉积的粒子)提供到等离子体以使得通过等离子体激活所述粒子,并且在其上要沉积粒子的表面上喷射激活的粒子。
图1示出了用于例如对表面进行处理或涂覆的粒子沉积设备100。
该示例的粒子沉积设备100基于使用介质阻挡放电生成等离子体射流。为此,向通过电介质材料而隔离的电极提供电压。在这种情况下,电介质材料是隔离管,其中一个电极提供在管内而另一电极提供在管外。
在操作中,产生辉光放电。通过提供流过该设备(具体地该管)的制程气体(processing
gas)来生成等离子体射流。该等离子体射流与(例如与周围空气隔离的)载运气体(carrier
gas)相混合。载运气体可以用于对表面的处理或可以包括用于对表面进行涂覆的粒子,即,将要沉积在表面上的粒子。
在各种实施例中,所述混合是在生成等离子体射流的设备部件外的反应区中执行的。在反应区中,等离子体的能量被转移到载运气体和/或包括在载运气体中的粒子。例如,包括在载运气体中的粒子可以通过在反应区中将载运气体与等离子体射流混合来激活,以便生成(激活的)粒子流或射流。
根据各种实施例,提供多个反应区并且向反应区提供不同的载运气体。可替换地,可以向所述反应区提供相同的载运气体。通过向反应区提供不同的载运气体,例如通过提供包含不同粒子的载运气体,可以生成具有不同的激活的气体和/或粒子的混合物。
激活的载运气体或粒子流可以分别用于对表面进行处理或涂覆。
粒子沉积设备100包括介质阻挡,在本例中为隔离管102。围绕隔离管102同心地提供外部电极103。在隔离管102的中心,提供内部电极104。在一端,隔离管102端接等离子体头105。在隔离管102的另一端,向隔离管提供制程气体106。在操作中,由于电极103、104所引起的放电而生成等离子体射流107,所述等离子体射流107通过等离子体头105的孔离开隔离管。
设备101还包括反应室108,所述反应室108包括用于等离子体射流107的第一入口109。第一入口109与等离子体头105的孔之间的汇合处可以被密封,以使得周围空气不能进入以这种方式进入反应室108。反应室108包括第二入口110,经由所述第二入口110将载运气体111提供到反应室108的内部空间112。此外,反应室108包括出口113。等离子体射流107经由第一入口109延伸到内部空间112中,在那里等离子体射流107和载运气体111被混合而产生激活的载运气体114。
激活的载运气体116(换言之,等离子体射流107和载运气体111的混合物或混合结果)经由反应室108的出口113离开反应室108,或,换言之由反应室108经由出口113发射,沿传导通道114流动并且经由孔(例如喷嘴或喷口)115离开该设备101。因此,传导通道114的一端可以被视为由出口113形成而传导通道114的另一端可以被视为由孔115形成。
粒子沉积设备还可以允许通过将其从两个入口注入来沉积不同材料的粒子的混合物。这在图2中图示。
图2示出了粒子沉积设备200。
与参考图1所描述的粒子沉积设备100类似,粒子沉积设备200包括隔离管202(制程气体206被提供到所述隔离管202)、外部电极203、内部电极204、等离子体头205(所生成的等离子体射流207经由所述等离子体头205离开隔离管202)、反应室208,所述反应室208包括用于等离子体射流207的第一入口209、第二入口210(经由第二入口210将载运气体211提供到反应室208的内部空间212)和出口213。经由第三入口221将另一载运气体219提供到反应室208。
等离子体射流207、载运气体211和另一载运气体219的混合结果经由出口213离开反应室208,沿传导通道214流动并且经由孔(例如喷嘴或喷口)215离开设备201。因此,传导通道214的一端可以被视为由出口213形成而传导通道214的另一端可以被视为由孔215形成。
根据各种实施例,对于等离子体沉积,可以使用冷活性(cold-active)大气压设备,例如所谓的等离子体刷设备,其例如具有类似参考图1和2所描述的设备100、200的结构。因此,在各种实施例中,等离子体沉积基于大气等离子体和/或基于冷活性等离子体。在各种实施例中,利用脉冲电弧放电而非振荡电路、按照逆变器原理来产生等离子体。
根据各种实施例的等离子体沉积设备可以是允许在多种基本衬底(例如纸、纸板、纺织品、陶瓷、玻璃、金属、和聚合物)上以金属、聚合物或半导体层进行涂覆过程的等离子体沉积设备。
根据各种实施例,等离子体沉积用于以下情形:其中与诸如像等离子体/火焰喷射之类的其他过程相比使用低温来生成等离子体射流和/或激活的载运气体和/或粒子流以及其中与诸如等离子体喷射和冷气喷射之类的其他程序相比激活的粒子的速度较低。
根据各种实施例,可以使用载运气体将待沉积的粒子以粉末形式提供到等离子体射流,例如,如参考图1和2所描述的。
晶圆或裸片上的等离子体沉积
根据各种实施例,例如如上所述的等离子体沉积设备用于在半导体层或裸片上产生粒子层。
在下文中将参考图3来对此进行描述。
图3示出根据实施例的流程图300。
该流程图图示了用于处理半导体晶圆或裸片的方法。
在301,将粒子提供到等离子体以使得通过等离子体激活所述粒子。
在302,将激活的粒子喷射在半导体晶圆或裸片上以在半导体晶圆或裸片上生成粒子层。
说明性地,根据各种实施例,等离子体尘埃(plasma dust)沉积方法或等离子体尘埃沉积被用于在半导体晶圆或裸片上沉积材料,例如在半导体芯片制造过程中。
根据各种实施例,用于处理半导体晶圆或裸片的方法还包括对粒子层进行图案化。
可以例如通过载运气体将所述粒子提供到等离子体,所述载运气体可以例如在大气压下提供。
在各种实施例中,用于处理半导体晶圆或裸片的方法还包括生成等离子体。
例如使用介质阻挡放电或电弧放电来生成等离子体。所述等离子体可以例如在大气压下生成。
例如将所述粒子以粉末形式提供到等离子体。所述粒子可以是电介质材料的粒子。所述粒子还可以是金属粒子。例如,所述粒子是铜、银、锡、锌、铑、钌或钽粒子。
在各种实施例中,通过粒子沉积设备的传导通道将激活的粒子喷射在半导体晶圆或裸片上,所述传导通道的一端由粒子沉积设备的至少一个孔形成,其中所述孔具有要沉积在半导体或裸片上的互连结构的形状。
用于加固接触区的等离子体沉积
根据各种实施例,将粒子喷射在衬底的层上以加固衬底的该层。衬底通常指的是半导体晶圆,例如硅、锗、SiC、GaN、GaAs等,但是还可以包括其他材料且具有其他形状。衬底的另一示例是所谓的重组晶圆,其中单独的半导体芯片被嵌入某种模塑料矩阵(mold
compound matrix)(例如,eWLB =嵌入式晶圆级球栅阵列)中。例如,可以将粒子喷射在接触垫区域上,即接触区,例如用于场效应晶体管的栅极、源极或漏极触点的接触区,用于产生加固该层(例如,接触区中的半导体晶圆的顶层,例如形成栅极、源极或漏极区或金属化层的半导体层)的粒子层,并且用于允许例如该加固层上的接合或焊接。
换言之,根据各种实施例,在以上参考图3所描述的方法中,将激活的粒子喷射在半导体晶圆或裸片的层上以生成加固该半导体晶圆或裸片的该层的至少一部分的粒子层,例如以形成加固的接触区。
在各种实施例中,将激活的粒子喷射在半导体晶圆或裸片的接触区上以使得粒子层加固所述接触区。
例如,将激活的粒子喷射在接触区上以形成接触垫。
在各种实施例中,将激活的粒子喷射在半导体晶圆或裸片的接触垫上以使得粒子层加固所述接触垫。
根据各种实施例,提供具有多孔加固层的半导体晶圆或裸片,其中多孔性在5%到50%之间。
所述多孔性可以例如在5%到30%之间或可以例如在30%到50%之间。
在各种实施例中,所述半导体晶圆包括接触垫,所述接触垫包括多孔加固层。
说明性地,在各种实施例中,参考图3所描述的方法可以被用于加固接触区(这可以被理解为在接触区上沉积粒子)并因此增加该层的稳定性和/或厚度,或者,换言之,使所产生的接触区(是原始层加上沉积的粒子层的布置)与其上已经沉积了粒子层的原始接触区相比具有增加的稳定性。
在金属(例如铜)表面上直接接合或焊接可能引起金属接合界面处的粘合问题。通过使用如上参考图3所描述的等离子体沉积,在各种实施例中,将厚的应力减小(stress-reduced)的金属层(例如铜)沉积在硅晶圆上以进行金属化。厚的铜层可以用于在半导体晶圆的正面或背面上形成低欧姆(即低电阻)接触垫和/或可以用作热接触的热沉。
由于比较高的表面粗糙度(与利用其它方法沉积的铜层相比),在这种铜层(即以这种方式沉积的铜层)上直接接合或焊接是可能的。此外,以上参考图3描述的沉积方法允许对半导体晶圆表面的表面工程(等离子体处理)。
利用用于厚金属膜(例如铜膜)的沉积技术,例如物理汽相沉积(PVD)和电化学沉积(ECD),可以以高膜内(in-film)应力值为代价产生提供低欧姆接触的金属膜。高膜应力可能导致高晶圆弯曲(bow),这可能引起处理问题以及还对下面的层的高压力,并从而引起裂缝。此外,诸如化学气相淀积(CVD)或物理汽相沉积之类的沉积技术具有高处理成本,大约三倍于以上参考图3所描述的等离子体沉积方法的成本。因此,利用这些沉积方法(例如CVD和PVD)对厚金属膜的(例如具有30 μm及以上的厚度的铜层的)沉积通常不可能以低成本进行。此外,由于高接合力,对这样的金属膜的直接接合通常引起处理问题,像接合界面处稳定性或下面的层中的裂缝。
在下文中参考图4和5描述用于加固接触区(例如金属化层,例如用于形成接合垫)的粒子层的沉积,例如通过使用如参考图3所描述的方法(例如利用大气等离子体尘埃沉积方法)在半导体晶圆的接触区上沉积厚金属膜(例如铜膜)。
图4示出根据实施例的晶圆400的顶视图。
在该晶圆上,例如使用多个图案化、沉积或去除步骤来形成多个裸片401。所述裸片可以具有接触区402,例如被暴露的并且可以用于接合的金属化层,例如用于接合导线以将接触区402连接到相应裸片402的引线框架。为了允许接合,在各种实施例中通过如参考图3所描述的等离子体沉积方法来加固接触区402。
图5示出晶圆500的横截面视图。
晶圆500例如对应于晶圆400。具体地,图5的横截面视图可以对应于包括接触区402之一的裸片401之一的一部分的横截面。
晶圆500包括衬底501、场隔离区502和在衬底501内形成的掺杂区504。栅电介质层506覆盖衬底501的部分并且栅电极508覆盖该栅电介质层506。换言之,在本例中,场效应晶体管在可以被视为晶圆500主体的部分中形成。
在各种实施例中,衬底(例如晶圆衬底)501可以由各种类型的半导体材料制成,例如包括硅、锗、III到V族或其他类型,不过在本发明的另一个实施例中,还可以使用其他适当材料。在各种实施例中,衬底501由(掺杂或无掺杂的)硅制成,在本发明的可替换的实施例中,衬底501是绝缘体上硅(SOI)晶圆的一部分。作为替换,任何其他适当的半导体材料能够被用于衬底501,例如像砷化镓(GaAs)、磷化铟(InP)之类的半导体化合物材料,而且还有任何适当的三元半导体化合物材料或四元半导体化合物材料,例如砷化铟镓(InGaAs)。
根据各种实施例,多个场效应晶体管及其他元件(例如电容器、二极管、双极晶体管、逆变器等等)可以在晶圆500中形成,类似于由掺杂区504、栅电介质层506、栅电极508和衬底501形成的场效应晶体管。
第一层间电解质层(ILD)510在栅电极508和半导体器件衬底501之上形成。第一层间电解质层510被图案化以形成双嵌入(dual inlaid)开口,所述开口被填充以粘附/阻挡层512和铜填充材料514。粘附/阻挡层512可以是耐熔金属、耐熔金属氮化物、或耐熔金属或其氮化物的组合。铜填充材料514可以例如是铜或铜合金,其中含铜量例如至少90原子百分数。铜可以与镁、硫、碳等等形成合金以改进该互连的粘附、电迁移或其他属性。在沉积该粘附/阻挡层512和铜填充材料514之后,对衬底进行抛光以去除该粘附/阻挡层512和铜填充材料514在开口外的部分。
绝缘阻挡层522在填充铜的互连和第一ILD层510之上形成。该绝缘阻挡层522可以包括氮化硅、氮氧化硅等等。使用绝缘材料来形成绝缘阻挡层522消除了对形成原本在使用导电阻挡的情况下将所述互连彼此隔离所需的附加图案化和蚀刻过程的需要。第二ILD层524在绝缘阻挡层522之上形成。包括导电的粘附/阻挡层526和铜填充材料528的双嵌入互连在第二ILD
524内形成。可以使用与用于在第一ILD层510中形成双嵌入互连结构类似的过程和材料来形成双嵌入互连。
钝化层521在第二ILD层524和双嵌入互连之上形成。钝化层可以包括氮化硅、氮氧化硅、二氧化硅等等的一个或多个膜。钝化层521的最靠近铜填充材料528的部分可以包括相对于原子氧具有较高原子氮浓度的氮化硅或氮氧化硅膜。钝化层521被图案化以形成接合垫开口523,该开口延伸通过钝化层521而到达铜填充材料528。
接合垫开口523或铜填充材料528的被接合垫开口523所暴露的部分可以被视为接触区。
铜填充材料528或铜填充材料528位于导电粘附/阻挡层526之上的部分可以被视为金属化层。
根据各种实施例,在接合垫开口523之上形成粒子层530以形成接合垫,即可以用于将相应裸片接合到引线框架并且将由接合垫开口523所暴露的铜填充材料526形成的接触区连接到引线框架的层。粒子层530可以被视为加固由铜填充材料526形成的金属化层以允许接合。
粒子层530例如是利用如上参考图3所解释的方法沉积的金属膜,例如铜膜。与其他方法相比,根据该方法所沉积的金属膜允许以减小的膜应力(减小大约30%到50%)、良好的电阻率(大约块状PVD铜的电阻率的1.5到2倍)提供对(例如用于接合的)层的加固,如图6中所示。
图6示出了膜应力图600。
在该膜应力图600中,膜厚度从左至右沿第一轴601(以μm给出的厚度)增加,并且膜应力以自下至上沿第二轴602增加的弯曲(以μm给出)来给出。
第一点603标记使用PVD沉积的铜的厚度和弯曲的数值对。第二点604标记使用如上参考图3所解释的方法在200℃沉积的铜的厚度和弯曲的数值对,并且第三点605标记使用如上参考图3所解释的方法在400℃沉积的铜的厚度和弯曲的数值对。
较低的膜应力可以被视为由如图7中所示的宽松的"海绵状的"膜结构引起。
图7示出使用如上参考图3所解释的方法沉积的金属膜的结构。具体地,金属膜是20 μm厚的铜膜。可以看到金属膜的海绵状的结构。此外,可以看到金属膜具有比较高的表面粗糙度。
金属膜中小孔(pore)的量,即多孔性,例如就小孔密度而言,即每特定体积的小孔量,可以根据特定应用情形的需要通过相应调整沉积参数(例如沉积温度)来调整。
为了降低电阻率,可以在150 ℃和500 ℃之间的温度通过合成气体来处理晶圆。这在图8中图示。
图8示出了电阻率图800。
在该电阻率图800中,膜厚度从左至右沿第一轴806(以μm给出的厚度)增加,并且电阻率以自下至上沿第二轴807增加的弯曲来给出(以μΩcm给出)。
第一点801标记使用PVD沉积的铜膜的厚度和电阻率的数值对。
第二点802标记使用以上参考图3描述的方法沉积的铜膜的厚度和电阻率的数值对,第三点803标记在200℃使用合成气体、使用以上参考图3描述的方法沉积的铜膜的厚度和电阻率的数值对,第四点804标记在300℃使用合成气体、使用以上参考图3描述的方法沉积的铜膜的厚度和电阻率的数值对,并且第五点805标记在400℃使用合成气体、使用以上参考图3描述的方法沉积的铜膜的厚度和电阻率的数值对。请注意第四点804和第五点805在图8中几乎相同。还可以在沉积本身期间使用惰性气体(例如Ar或Xe或合成气体)来实现低电阻。
能够以可接受的处理成本(大约为诸如PVD或ECD之类的其他方法的成本的20%到30%)沉积高达100 μm的厚度的膜。厚的铜膜可以提供相当大的热容并且因此改进从半导体器件散热的性能。
由于高表面粗糙度(如图7中所示)和在通过使用例如已经被用于沉积的等离子体流进行沉积之后处理沉积层的表面的可能性,在粒子层530的表面上直接接合和/或焊接应该是可能的。这可以允许进一步节约成本。
另外,(如图7中所示的)沉积的粒子层530的宽松的海绵状结构可以吸收一部分接合力,以使得增大的接合力(与利用其它方法沉积的类似厚度的金属膜相比)是可能的。因此,在粒子层530下面的层,例如在由铜填充材料528形成的金属化下面的层,受到接合过程的减小应力,从而引起更多产品稳定性以及更少处理问题(例如IMD层中的裂缝)。
用于加固晶圆的等离子体沉积
作为另一示例,为了使用如图3中所示的方法在半导体晶圆的层上喷射粒子以加固半导体晶圆的该层,可以产生粒子层以加固薄晶圆。
换言之,根据各种实施例,在以上参考图3描述的方法中,将激活的粒子喷射在半导体晶圆或裸片的层上以生成粒子层以用于加固半导体晶圆或裸片的该层的至少一部分。
在各种实施例中,将激活的粒子喷射在半导体晶圆或裸片上以完全覆盖该半导体或裸片的至少一面。
例如,将激活的粒子喷射在未加工的半导体晶圆或裸片上。例如,将激活的粒子喷射在未图案化的半导体晶圆或裸片上。
在各种实施例中,半导体晶圆具有低于100 μm的厚度。
在各种实施例中,该方法还包括在将粒子层喷射在半导体晶圆或裸片的该层上之后减小半导体晶圆或裸片的该层的厚度。
半导体晶圆或裸片的该层可以是半导体晶圆或裸片的主体层。例如,半导体晶圆或裸片的该层是半导体晶圆或裸片的半导体主体层。
在各种实施例中,将粒子喷射在半导体晶圆或裸片的正面、背面或双面上。
根据各种实施例,半导体晶圆或裸片被提供具有多孔加固层,其中多孔性在5%到50%之间。
多孔性可以例如在5%到30%之间或可以例如在30%到50%之间。
在各种实施例中,多孔加固层完全覆盖半导体晶圆或裸片的至少一面。
说明性地,在各种实施例中,如参考图3所描述的方法可以被用于加固晶圆,其可以被理解为在晶圆之上沉积粒子并因此增加晶圆的稳定性和/或厚度,或者,换言之使得所产生的晶圆(即原始晶圆加上沉积的粒子层的布置)与其上已经沉积了粒子层的原始晶圆相比具有增加的稳定性。
在现代半导体器件制造中,对薄晶圆的处理变得越来越重要。载体系统可以被用于实现薄晶圆处理以用于进一步的工序(例如薄晶圆的背面金属化)。晶圆在它具有少于100 μm的厚度时可以例如被认为是"薄的"。用于处理薄硅晶圆的载体系统(例如玻璃载体晶圆)很昂贵并且通常表现出其他缺点,例如低可容许处理温度或对复杂处理流的要求。此外,可接受的最小硅厚度典型地受限于对处理薄晶圆的要求。
根据各种实施例,使用如上参考图3所描述的方法将(例如相对)厚的膜沉积在(例如相对薄的)晶圆上以稳定晶圆以供进一步处理。
沉积的膜可以是金属膜,例如铜,但也可以由诸如聚合物、塑料或碳之类的其他材料形成。所述材料例如被选择成使得,对于该材料被沉积于其上的硅晶圆而言该材料是应力中性的并且由此在沉积之后引起最小的晶圆弯曲。
由于参考图3所描述的方法的低处理成本,根据各种实施例可以提供允许处理薄晶圆的相对便宜的可能性。此外,载体系统的制造不限于机械步骤并且与在不对晶圆进行加固的情况下对于薄晶圆使用载体系统相比硅厚度的限制少得多。例如,根据各种实施例,可以在诸如金属(例如铜)层或其他加固材料层之类的(相对厚的)加固层上处理(具有例如几μm的厚度的)非常薄的硅晶圆。
在下文中参考图9A到9D(第一示例)和10A到10E(第二示例)来描述用于使用参考图3所描述的等离子体沉积方法来加固(薄)晶圆的两个示例。
图9A示出了晶圆加固过程的第一阶段。
将晶圆901(例如薄的硅晶圆)安装在安装框架902上,例如箔。
晶圆901例如具有低于100 μm的厚度。然而,可容许的厚度可以取决于晶圆901的尺寸。例如,对于较大的晶圆,必须高于100 μm,而对于较小的晶圆,厚度可以低于100 μm。
图9B示出了晶圆加固过程的第二阶段。
在第二阶段,将粒子层903沉积在晶圆901上。使用如上参考图3所描述的等离子体沉积方法来沉积粒子层903。粒子层903可以是金属层(例如铜层)或包括诸如聚合物、碳、塑料之类的其他材料的层。粒子层902具有足够的厚度以充分地加固晶圆901。它因此可以被视为厚层,例如,具有例如高达100 μm厚度的厚金属层。可以根据如上参考图3所描述的等离子体沉积方法、使用冷法(例如以低于150℃的沉积温度)将粒子层902直接地沉积在硅晶圆901上。在本例中,硅晶圆901被安装框架902(或可替换地,被载体系统)保持在其正面。
图9C示出了晶圆加固过程的第三阶段。
在该第三阶段,去除安装框架902。该结果可以被视为加固的晶圆,包括原始薄晶圆901和加固粒子层903。
图9D示出了加固的晶圆的进一步处理。
加固的晶圆可以受到进一步处理。例如,可以在与原始薄晶圆901相对应的加固晶圆的表面上形成钝化层904。
如果诸如铜层之类的金属层被用作粒子层903,所述粒子层903用作薄晶圆901的载体,则粒子层903可以被用作热沉以用于进一步处理。另外,在这种情况下,粒子层903能够被用作晶圆901的金属触点。
在下文中参考图10A到10E来描述晶圆加固过程的另一示例。
图10A示出了晶圆加固过程的第一阶段。
在第一阶段中,提供晶圆1001,例如硅晶圆。晶圆1001可以是"厚"晶圆,换言之,晶圆可以具有就所需的载体系统而言允许容易处理的厚度。例如,在第一阶段中,晶圆1001具有超过100 μm的厚度。
图10B示出了晶圆加固过程的第二阶段。
在第二阶段中,通过在以上参考图3描述的方法在晶圆1001的正面上沉积例如聚合物、塑料或碳的(厚)膜以生成加固粒子层1002。
图10C示出了晶圆加固过程的第三阶段。
晶圆1001的背面被研磨以使得晶圆1001具有期望厚度,例如少于150 μm或少于100 μm。借助于用作加固的粒子层1002来为研磨的晶圆1001提供机械稳定性。
图10D示出了晶圆加固过程的第四阶段。
第四阶段对应于加固和研磨的晶圆1001的进一步处理。例如,晶圆1001可以如结构1003所指示的那样被图案化以例如分离在晶圆1001的主体中形成的各个元件并且可以在晶圆1001上形成金属化层1004。
图10E示出了晶圆加固过程的第五阶段。
在诸如图案化(例如用于分离)和金属化之类的期望处理之后,去除粒子层1002。
粒子层1002的期望机械特性(例如相对于下面的晶圆1001的应力中性)可以通过选择适当材料和适当沉积条件来实现(例如通过调整粒子层1002的多孔性)。
粒子层903、1002的结构(以及因此热和/或机械特性)可以通过改变处理参数来调整。膜的多孔性可以根据生产需要在例如5%到30%的范围内调整。
用于沉积混合物的等离子体沉积
根据各种实施例,参考图3描述的等离子体沉积方法可以被用于将两种材料的混合物沉积在半导体晶圆或裸片上。这在图11中图示。
图11示出根据实施例的流程图1100。
流程图1100图示了用于处理半导体晶圆或裸片的方法。
在1101中,至少两种材料的粒子被提供到等离子体以使得通过等离子体激活所述粒子并且使得形成所述至少两种材料的激活的粒子的混合物。
在1102中,将该混合物喷射在半导体裸片上以在半导体晶圆上生成包括至少两种材料的粒子的混合物的层。
说明性地,换言之,等离子体尘埃沉积方法或等离子体尘埃沉积设备被用于沉积粒子混合物,例如两种或更多种材料的混合物,例如用于焊接的金属的混合物。
换言之,在各种实施例中,所述材料是例如形成(以混合物形式)焊接材料的焊接材料。
所述材料例如是不同的材料,例如不同的元素。
在各种实施例中,所述材料是不同的金属。例如,所述两种材料均是铜、银、锡、和锌之一。
在各种实施例中,该方法还包括通过该层将半导体晶圆或裸片附于引线框架。
在各种实施例中,将该混合物喷射在半导体裸片上并且该方法还包括通过该层将半导体晶圆附于另一半导体裸片。
在各种实施例中,将该混合物喷射在半导体晶圆的多个半导体裸片上,并且该方法还包括在将该混合物喷射在多个半导体裸片上之后分离所述半导体裸片。
在各种实施例中,将三种或更多种材料的粒子提供到等离子体以使得粒子被所述等离子体激活并且使得三种或更多种材料的激活的粒子的混合物被形成并且其中将该混合物喷射在半导体晶圆或裸片上以生成包括三种或更多种材料的粒子的混合物的层。
该层可以是多孔层,其中多孔性例如在5%到30%之间。
在各种实施例中,将该混合物喷射在半导体晶圆或裸片的背面上。
两种材料的粒子例如被同时激活。两种材料的粒子例如可以被一起激活。
在各种实施例中,在将两种材料的粒子混合之后激活两种材料的粒子。
在图11中图示的方法例如可以被用于将焊接材料的混合物(也称为焊接系统)带到半导体晶圆或裸片上。
将焊接系统带到半导体裸片上以用于将半导体裸片(即裸片接合)接合到引线框架可能很困难,但是相对于包括将焊接系统带到引线框架上的用于晶圆接合的方法可以具有优点。优点之一例如可以是焊接材料的较低消耗,这是因为焊接材料可以被精确地带到需要它们来将半导体晶圆连接到引线框架的地方。此外,可以实现焊接层的较小厚度并且可以避免芯片浸在(swimming)引线框架的焊接材料上。
可以使用扩散焊接材料将焊接材料带到晶圆或裸片的背面上。可以使用溅射(即溅射沉积)或以合金或金属形式流电地(galvanically)将扩散焊接材料带到裸片上。在这种情况下,焊料的反应速率通常受限于参与焊接过程的材料层之间的扩散。因为扩散是相对缓慢的过程,所以扩散焊接通常需要比普通焊接过程更多的时间。为了增加反应速率,可以使用非常薄的层。然而,如果被用于将裸片接合到引线框架的裸片表面(例如裸片的背面)具有增加的粗糙度,则这可能产生问题。此外,对于流电沉积或溅射,可用的材料系统通常受限。另外,该过程和过程控制通常是复杂且危险的。还将考虑的是,在后续锯切过程中,一个或多个焊层也被锯切。这可能导致额外的要求。
根据各种实施例,以上参考图11描述的方法被用于将焊接材料的混合物带到裸片上,例如用于将裸片接合到引线框架。这允许与用于焊接的材料有关的高灵活性(例如与流电沉积、溅射和扩散接合的使用相比)。因此,焊接系统(即焊接材料的混合物)可以用于不能使用例如流电沉积、溅射和扩散接合而使用的焊接,例如CuSn或CuSnAg。此外,沉积温度能够被降到100℃及更低,以使得具有多种尺寸的粒子的混合物可以在没有焊剂且没有(不需要的)反应的情况下应用。所述焊接另外可以以低成本执行。
此外,使用参考图11所描述的用于沉积焊接系统的方法引起参与材料之间的大的接触面积,这引起高扩散速率并且由此引起高反应速率和低反应时间。
另外,仅少量焊接材料被挤压超过裸片(或芯片)的边缘。此外,可以提多种厚度的焊接层。
在各种实施例中,裸片可以包括多个裸片,所述多个裸片可以被堆叠为一个在另一个之上。因此,在各种实施例中,裸片可以包括多裸片布置(换言之,多芯片布置),其中裸片到引线框架接合和裸片到裸片接合可以使用如参考图11所描述的方法来执行。在下文中,提供了基于如参考图11所描述的等离子体沉积方法的焊接方法可以应用于的裸片的示例。
图12示出了根据实施例的裸片1200的横截面。
如图12所示,在本例中,裸片1200包括多个裸片,所述多个裸片被堆叠为一个在另一个之上。通常,任意数量的裸片可以被堆叠为一个在另一个之上。图12的裸片1200可以包括第一功率半导体裸片1202(例如实施为SiC-JFET(结型场效应晶体管)裸片1202)和第二功率半导体裸片1204(例如被实施为JFET裸片1204)。
如图12中所示,第一功率半导体裸片1202(例如实施为SiC-JFET裸片1202)可以包括形成SiC-JFET裸片1202的漏极区的SiC衬底1208和漏极金属化层1210(作为裸片接合区域的实施方式),例如由AuSn制成。漏极金属化层1210可以位于SiC衬底1208的第一面1212(例如背面1212)上。SiC-JFET裸片1202还可以包括栅极区1218和源极区1220,所述栅极区1218和源极区1220被布置在与SiC衬底1208的第一面1212相对的SiC衬底1208的第二面1216(例如正面1216)上的钛扩散阻挡层1214(例如,具有从大约100 nm到大约200 nm变动的层厚度,例如具有大约150 nm的层厚度)上或之上。如上所述,栅极区1218和源极区1220这二者可以包括铜或铜合金或者由铜或铜合金组成,并且可以具有从大约1 μm到大约10 μm变动的层厚度,例如从大约3 μm到大约8 μm变动的层厚度,例如大约5 μm的层厚度。第一功率半导体裸片1202可以通过模塑材料1222(例如像亚胺)来模塑,其中栅极区1218的表面1224的部分和源极区1220的表面1226的部分保持无模塑材料,换言之保持暴露。
可以使用以上参考图11描述的方法将漏极金属化层1210裸片接合到框架结构1206,例如像引线框架结构,即可以是裸片到引线框架接合。
第二功率半导体裸片1204可以包括形成JFET裸片1204的漏极区的硅衬底1228和漏极金属化层1230(作为裸片接合区域的实施方式),例如由AuSn或铜或铜合金制成。漏极金属化层1230可以位于硅衬底1228的第一面1232(例如背面1232)上。JFET裸片1204还可以包括栅极区1236和源极区1238,所述栅极区1236和源极区1238被布置在与硅衬底1228的第一面1232相对的硅衬底1228的第二面1234(例如正面1234)上的钛扩散阻挡层(未示出)上或之上。如上所述,栅极区1236和源极区1238这二者可以包括铜或铜合金或者由铜或铜合金组成,并且可以具有从大约1 μm到大约10 μm变动的层厚度,例如从大约3 μm到大约8 μm变动的层厚度,例如大约5 μm的层厚度。第二功率半导体裸片1204可以通过模塑材料(例如像亚胺)来模塑,其中栅极区1236的表面1240的部分和源极区1238的表面1242的部分保持无模塑材料,换言之保持暴露。
可以使用参考图11描述的方法将第二功率半导体裸片1204的漏极金属化层1230裸片接合到包含第一功率半导体裸片1202的源极区1220的铜的暴露表面1226,即可以是裸片到裸片接合的。
为了裸片到裸片接合或裸片到引线框架接合,例如为了将第二功率半导体裸片1204的漏极金属化层1230接合到包含第一功率半导体裸片1202的源极区1220的铜的表面1226,并且为了裸片到引线框架接合,例如为了将漏极金属化层1210接合到框架结构1206,根据参考图11所描述的等离子体沉积方法,将用于接合的焊接材料的粒子混合并且将其带到相应的裸片表面(例如漏极金属化层1210、1230)上。
因此,将焊接材料的混合物带到待接合的裸片表面上。根据参考图11所描述的等离子体沉积方法,在各种实施例中,粒子在彼此没有强烈反应的情况下结合在一起,即扩散是严格地本地的并且粒子保持它们的特性。例如,可以将处于所定义的期望混合水平的Cu/Sn或Cu/Sn/Zn的混合物带到裸片上。粒子粘附得很好,并且所产生的层具有大约5到30%的小孔体积。例如两种材料的粒子的浓度比可以被选择为对应于共晶(eutectic)或在共晶附近,从而允许增加反应速率。
在各种实施例中,将接合/焊接材料沉积在晶圆的一个或多个裸片上并且在沉积之后,执行锯切和芯片分离过程。单独的芯片(或裸片)在其背表面上包括具有例如金属材料的期望浓度的焊接混合物。然后可以将芯片置于加热的引线框架(LF)上,或如参考图12所描述的那样,置于另一裸片上,以使得焊料典型地在例如少于一秒的短时间内反应,并且形成金属间相。金属间相例如可以包括多个金属平衡相。这些平衡相可以提供升高的熔点,与例如可能被重新熔融的焊接混合物相比,允许提供热稳定的焊接。
等离子体沉积的多孔层的图案化
根据各种实施例,如参考图3描述的等离子体沉积方法可以用于图案化的过程中,即在用于形成图案化层的过程中沉积粒子层。
这在图13中图示。
图13图示了处理半导体晶圆的方法。
在1301,对半导体晶圆的表面进行图案化。
在1302,通过将粒子提供到等离子体以使得通过等离子体激活所述粒子并且将激活的粒子喷射在图案化的表面上以在图案化的表面之上生成粒子层,来将粒子沉积在图案化表面上。
换言之,在各种实施例中,参考图3描述的方法还可以包括对半导体晶圆或裸片的表面进行图案化,其中将激活的粒子喷射在半导体晶圆或裸片的表面上以在图案化的半导体晶圆或裸片上生成粒子层。
说明性地,在各种实施例中,等离子体尘埃沉积方法被用于在图案化方法中沉积层。例如,如此使用图案化方法以使得使用等离子体尘埃沉积方法所沉积的层被图案化。
在各种实施例中,半导体晶圆或裸片的表面被图案化以包括图案化的掩模。
在各种实施例中,半导体晶圆或裸片的表面被图案化以包括图案化的电介质掩模。
该方法还可以包括对粒子层进行图案化。
在各种实施例中,根据镶嵌或双镶嵌技术来对半导体晶圆或裸片和粒子层进行图案化。
在各种实施例中,根据剥离技术来对半导体晶圆或裸片和粒子层进行图案化。
在各种实施例中,粒子层是金属层或电介质层。
该方法还可以包括沉积阻挡和/或种层,其中将粒子层喷射在阻挡和/或种层上。
根据各种实施例,在图13中图示的方法被用在镶嵌(或双镶嵌)过程或剥离过程中。
使用参考图3所描述的方法形成的金属层可以具有高密度的小孔(例如5%到30%)。使用诸如湿化学蚀刻或等离子体蚀刻之类的方法对这种层进行图案化因此会引起蚀刻结构的糟糕限定的侧面以及对意在留在晶圆上的部分的不希望的蚀刻。
根据各种实施例使用的图案化方法通过基于例如CMP(化学机械抛光)、镶嵌技术和剥离技术提供对厚的多孔金属膜(例如由大气等离子体沉积引起的铜膜)的可靠图案化而允许将使用参考图3所描述的方法所形成的粒子层用于某些应用,例如接合垫加固、厚金属互连和互连再分布。
根据各种实施例的图案化方法还可以用于多孔电介质层,例如陶瓷和聚合物层。
根据各种实施例,使用如参考图3所解释的等离子体沉积方法来形成半导体晶圆上多孔导电路径。为了避免导电路径中的短路或缺口(gap),在湿式蚀刻被用于形成导电部分的情况下将需要大的芯片面积。金属路径的尺寸和金属路径之间的距离这二者与在使用湿式蚀刻形成它们时使用无孔的导电路径相比将需要被增加。从经济观点看这将使得多孔导电路径的使用变得无趣,这是因为可以通过使用如参考图3所解释的等离子体沉积方法形成多孔导电路径而实现的成本优点将因为增加的芯片面积要求而废弃。
在各种实施例中,如参考图3所解释的等离子体沉积方法被用于形成粒子层,例如金属层,其是使用镶嵌技术而被图案化的。在下文中参考图14A到14E来描述基于如参考图3所解释的等离子体沉积方法且基于镶嵌技术来形成图案化金属层的过程。
图14A示出图案化金属层形成过程的第一阶段。
提供具有金属化垫或金属化线1402的硅晶圆1401。
图14B示出图案化金属层形成过程的第二阶段。
根据镶嵌技术,金属间电介质(诸如二氧化硅、氮化硅、光致亚胺(photo imid)、聚合物或光致抗蚀剂)被带到包括金属化垫1402的晶圆1401上并且被图案化。
例如,将可以使用光刻法图案化的聚合物层沉积在包括金属化垫1402的晶圆1401上并且对聚合物掩模进行图案化(使用光刻法)以形成聚合物掩模1403。聚合物掩模的厚度限定了将要形成的图案化金属层的最终厚度。例如,对于5 μm的图案化金属层的最终厚度,聚合物的厚度可以被选择为大约5.5 μm。
图14C示出图案化金属层形成过程的第三阶段。
使用参考图3所描述的等离子体沉积方法将(待图案化的)金属层1404沉积在图案化的金属间电介质层之上,诸如聚合物掩模1403。所述金属例如是铜或钨或钛或钽。金属层可以遍及晶圆1401之上沉积(或遍及晶圆的所考虑的部分,例如与一个或多个裸片相对应的晶圆区域)。金属粒子例如在大气压下吹到晶圆1401上。粒子的尺寸例如被选择为使得它为其上将沉积金属层的结构的尺寸(即在本例中,聚合物掩模1403的结构尺寸)的大约三分之一,以使得该结构完全被金属层填充。图14D示出图案化金属层形成过程的第四阶段。
在等离子体沉积之后,将(多孔)金属层1404抛光到金属间电介质(例如聚合物掩模1403)的高度,以使得金属间电介质被暴露并且金属层表面变平。应该注意到,在该过程结束时金属层1404的图案化的最小结构尺寸由间电介质例如聚合物掩模1403的图案化给出。所述抛光例如化学机械抛光(CMP)。金属层1404位于聚合物掩模1403所形成的沟槽中的部分在抛光之后留下。
图14E示出图案化金属层形成过程的第五阶段。
在抛光之后,去除金属间电介质,例如聚合物掩模1403。可替换地,它能够继续保持在晶圆1401上以作为图案化金属层1404的金属路径之间的隔离。
使用参考图14A到14E所描述的过程,可以形成一个互连金属化层。使用抛光,例如CMP抛光,可以具有以下优点:可以避免多孔金属层的不受控的蚀刻,如在使用刻蚀处理来对金属层1404进行图案化时可能发生的。使用参考图3所描述的等离子体沉积方法所沉积的抛光铜层在上面描述的图7中示出。在图7中金属层的蚀刻不可见。由于金属层的多孔性,与无孔的金属层相比,CMP去除率被提高,以使得CMP过程可用于成本有效地去除甚至厚的层。
在各种实施例中,通向下面的金属层(例如埋于晶圆1401的主体中的金属层)的接触路径的形成与参考图14A到14E所描述的使用双镶嵌的过程类似地执行。
在各种实施例中,在沉积多孔金属层1404以用于增强到埋置的金属层的接触之前,例如通过使用溅射或使用CVD,将阻挡和/或种层系统带到晶圆1401(包括图案化金属间电介质)上。
如上所述,可以在对金属层1404进行图案化之后去除图案化金属层1404的金属路径之间的电介质。因此,金属路径的侧面被暴露以使得与埋置的金属路径或在其侧面被电介质包围的金属路径相比,可以实现更好的散热。对于功率半导体元件而言,这会是有利的。
在各种实施例中,代替聚合物层1403,氧化层或氮化层被沉积并且被图案化。否则,可以如参考图14所描述的那样执行该过程。图案化的氧化物或氮化物可以留在图案化金属层1404的金属路径之间以用作隔离或可以在CMP之后被选择性地去除(同时使图案化金属层1403留下)。
代替金属层1404,可以使用如上所述的镶嵌技术形成诸如陶瓷层或聚合物层之类的图案化电介质层。
在各种实施例中,如参考图3所解释的等离子体沉积方法被用于形成粒子层,例如金属层,其是使用剥离技术而被图案化的。在下文中参考图15A到15E来描述基于如参考图3所解释的等离子体沉积方法且基于剥离技术来形成图案化金属层的过程。
图15A示出图案化金属层形成过程的第一阶段。
提供具有金属化垫1502的硅晶圆1501。
图15B示出图案化金属层形成过程的第二阶段。
例如使用旋压(Spin-On)技术将抗蚀剂(例如光致抗蚀剂)1503带到包括金属化垫1502的晶圆1501上。
图15C示出图案化金属层形成过程的第三阶段。
例如使用光刻法对抗蚀剂1503进行图案化以使得在金属化应该被带到的那些地方去除抗蚀剂。
图15D示出图案化金属层形成过程的第四阶段。
使用以上参考图3描述的等离子体沉积方法,将金属层1504(例如铜或铝)沉积在包括图案化的抗蚀剂1503的晶圆1501上。
图15E示出图案化金属层形成过程的第五阶段。
抗蚀剂被去除,其中金属层1504在晶圆1501被抗蚀剂覆盖的部分之上的部分也被去除。金属层1504的部分留在未被抗蚀剂覆盖的晶圆1501处的表面的那些部分。为了去除抗蚀剂1503(在本例中,被金属层1504覆盖的抗蚀剂),可以利用金属层1504的多孔性以例如使用于去除抗蚀剂1503的流体与抗蚀剂接触。
金属层形成过程的结果是如图15E中所示的暴露的图案化多孔金属层1504。
通过使用以上参考图14A到14E和图15A到15E描述的技术来形成厚的图案化金属层(例如,从10 μm到100 μm的厚度),可以以低成本提供图案化金属层。此外,图案化具有高可靠性并且可以实现高封装密度。可以以相对低处理温度(例如低于150℃的处理温度是可能的)来执行该处理。此外,可以通过使用多孔金属层来将晶圆应力和晶圆弯曲保持为低。金属层可以具有良好的散热能力(例如通过使用厚铜金属化)。
在各种实施例中,不使用种层以使得成本可以被进一步减少。
使用参考图3所描述的等离子体沉积方法,可以形成具有优良的机械、热和电特性的层。
使用具有适应互连的形状的孔
根据各种实施例,参考图3所描述的等离子体沉积方法被用于将互连结构(例如导电路径或导电垫)喷射到诸如半导体晶圆或裸片或还有印刷电路板之类的载体上,以用于例如形成芯片与芯片封装的电连接之间的电互连,例如用于形成从芯片本身到引线框架的互连。例如,使用参考图1或图2所描述的等离子体沉积设备将金属粒子喷射到载体上。为此,在各种实施例中,等离子体沉积设备的孔,例如图1和图2的等离子体沉积设备的孔115、215,例如喷嘴和/或喷口可以适应待形成的互连结构。
因此,在各种实施例中,如图16中所示的那样提供粒子沉积设备。
图16示出根据实施例的颗粒沉积设备1600。
粒子沉积设备1600包括用于将等离子体射流提供到反应室1603的第一提供部件1601、用于将载运气体提供到反应室1603的第二提供部件1602。粒子沉积设备1600还包括用于混合等离子体射流和载运气体以生成混合物的反应室1603,其中所述反应室包括用于发射混合物的出口1604。
粒子沉积设备1600还包括传导通道1605,所述传导通道1605具有由出口1604形成的第一端以及由粒子沉积设备1600的至少一个孔1606形成的第二端,所述至少一个孔具有要沉积在载体上的互连结构的形状。
换言之,可以为视为等离子体沉积设备(例如在各种实施例中的等离子体尘埃沉积设备)的粒子沉积设备1600的开口适应于待形成的互连结构的形状,其中通过所述开口将待沉积的粒子喷射在载体上。
所述载体例如是半导体晶圆、半导体裸片或印刷电路板。
根据各种实施例,所述孔包括多个单独的开口。
在一个实施例中,所述孔的形状的至少一部分对应于金属路径的形状。例如,所述孔的形状的至少一部分对应于互连线的形状和/或所述孔的形状的至少一部分对应于接触垫的形状。
在各种实施例中,所述孔的形状的至少一部分对应于在一端与接触垫连接的金属路径的形状。
所述孔的形状的至少一部分可以对应于在两端与接触垫连接的金属路径的形状。
在各种实施例中,所述孔的形状的至少两个单独部分均对应于在一端与接触垫连接的金属路径的形状。
在各种实施例中,所述孔的形状的至少两个单独部分均对应于在两端与接触垫连接的金属路径的形状。
所述孔例如可以包括至少一个直边。所述孔例如可以包括至少两个直边。
在各种实施例中,所述孔的形状的至少一部分对应于互连结构的形状,所述互连结构具有第一端和第二端和相对于第一端和第二端渐缩的(tapered)中间段。
所述载运气体例如包括铜、银、锡、锌、铑、钌或钽粒子。
与互连结构相对应的粒子沉积设备的孔(例如喷嘴)的形状的例子在图16给出。所图示的形状可以被视为将要在载体上形成的互连结构的顶视图,所述互连结构对应于粒子沉积设备的孔的形状。
图17示出根据各种实施例的孔形状。
第一孔形状1701可以被视为对应于要在载体上形成的金属路径,例如用于连接到位于载体上的半导体器件的金属路径。金属路径的这种孔形状另外可以包括在一端或两端具有与将要在载体上形成的接触垫相对应的形状的一个或两个元件,如由第二孔形状1702和第三孔形状1703所示。具有接触垫的形状的第二孔形状1702和第三孔形状1703的垫元件1710可以被视为通过具有金属路径形状的金属路径元件1711来连接。第二孔形状1702和第二孔形状1703可以被用于形成互连结构,从而允许使用与垫元件相对应的垫对半导体器件的连接,例如经由接合。
在各种实施例中,如在第一孔形状1701、第二孔形状1702和第三孔形状1703的情况下,该孔可以被视为形成一个连接形状。
可替换地,在各种实施例中,所述孔包括多个单独的开口。例如,根据第四孔形状1704,所述孔包括与第四孔形状1704的第一元件1712相对应的第一开口和与第四孔形状1704的第二元件1713相对应的第二开口。第一开口和第二开口彼此分离,即它们不相连接,换言之,它们不形成连续开口。
这样的孔形状还可以包括多于两个单独的部分(即单独的开口)。例如,根据第五孔形状1705,所述孔可以具有与第五孔形状1705的四个元件1714相对应的四个单独的开口。第五孔形状1705可以例如用于形成用于具有四个触点的半导体器件的互连结构。可以使用与第五孔形状1705的内部垫元件1707相对应的垫将这四个触点例如接合到载体。外部垫元件1708然后可以用于连接其他半导体元件或例如用于接合到引线框架。
应该注意到,与单独元件相对应的诸如第四孔形状1704和第五孔形状1705之类的孔形状不一定必须包括垫元件。例如,第六孔形状1706可以被视为对应于第五孔形状1705,其没有垫元件1707、1708而是仅包括(单独的)金属路径元件1715。
应该注意到,孔形状可以甚至比例如第五孔形状1705更复杂。例如,孔形状可以对应于包括多个接触垫和多个金属路径的复杂互连图案。例如,孔形状可以对应于印刷电路板的整个互连图案。
对于粒子沉积设备1600使用将要在诸如半导体晶圆、半导体裸片或印刷电路板(PCB)上形成的互连结构的形状的孔允许容易的形成互连结构。说明性地,互连结构可以通过以下方式形成,即在不是必须"绘制(draw)"该互连结构(即在喷射时相对于载体移动粒子沉积设备1600或相对于粒子沉积设备1600移动载体)的情况下,在将要形成该互连结构的载体位置处使用单次喷射突发。这在图17中图示。
图18示出了根据实施例的互连形成布置1800。
所述互连形成布置包括粒子沉积设备1801(例如对应于参考图16所描述的粒子沉积设备1600)和互连结构将形成于其上的载体1802。
粒子沉积设备1801可以如箭头1803所指示的那样被移动到载体1802的特定位置,例如借助于粒子沉积设备1801的适当支持框架。在粒子沉积设备1801已经被移动到与粒子沉积设备1801的孔的形状相对应的互连结构所处的载体1802的位置时,粒子沉积设备1802被打开,以使得它经由粒子沉积设备1801的孔(例如喷嘴)发射待沉积的粒子。在取决于待沉积的互连结构的层厚度的时间之后,粒子沉积设备1802可以被移动到与粒子沉积设备1801的孔的形状相对应的互连结构将被形成于的载体1802的另一位置。
换言之,在各种实施例中,粒子沉积设备1600被移动到位置,在沉积时段内打开,其中它在沉积时段内保持在该位置,在沉积时段之后被关掉,并且然后移动到另一位置,诸如此类。说明性地,互连结构不是通过在粒子沉积设备1600打开时移动该粒子沉积设备而被绘制到载体上的,而是通过以沉积突发(其间粒子沉积设备1801不移动,即相对于载体1802保持在固定位置)交替移动粒子沉积设备1801来形成的。
应该注意到,在各种实施例中,粒子沉积设备1801可以被保持在固定位置,并且载体可以在突发之间移动。换言之,将粒子沉积设备1801移动到载体1802的位置可以被理解为改变粒子沉积设备1801和载体1802的相对位置,以使得从载体1802的角度看,粒子沉积设备1801被移动到载体1802的位置。
在各种实施例中,粒子沉积设备1600可以被视为提供于以下情况:例如洞形设计的孔(例如喷嘴或喷嘴头)被具有根据待沉积的图案的几何形状的设计的孔所替代。
粒子沉积设备1600可以用于形成互连结构(例如从头开始)或用于修理已经存在于载体上的互连结构。粒子沉积设备1600可以用于形成具有大于1 μm的结构尺寸的互连结构。孔(例如喷嘴)1606和/或传导通道1605的形状例如可以通过模拟来确定和/或优化。
Claims (19)
1.一种用于处理半导体晶圆或裸片的方法,包括:
将粒子提供到等离子体以使得通过等离子体激活所述粒子;
将激活的粒子喷射在半导体晶圆或裸片上以在半导体晶圆或裸片上生成粒子层,
其中通过粒子沉积设备的传导通道将激活的粒子喷射在半导体晶圆或裸片上,所述传导通道的一端由粒子沉积设备的至少一个孔形成,
其中所述孔具有将要沉积在半导体或裸片上的互连结构的形状;
其中至少两种材料的粒子被提供到相同反应室的相同内部空间中的等离子体,使得所述粒子被等离子体激活,并且使得所述至少两种材料的激活的粒子的混合物被形成,其中所述混合物被喷射在半导体晶圆或裸片上以形成包括所述至少两种材料的粒子的混合物的层。
2.根据权利要求1所述的方法,还包括对粒子层进行图案化。
3.根据权利要求1所述的方法,其中通过载运气体将粒子提供到等离子体。
4.根据权利要求1所述的方法,其中在大气压下提供载运气体。
5.根据权利要求1所述的方法,还包括生成等离子体。
6.根据权利要求5所述的方法,其中在大气压下生成等离子体。
7.根据权利要求1所述的方法,其中将激活的粒子喷射在半导体晶圆或裸片的层上以生成粒子层以用于加固所述半导体晶圆或裸片的所述层的至少一部分。
8.根据权利要求7所述的方法,其中将激活的粒子喷射在半导体晶圆或裸片的接触区上以使得所述粒子层加固所述接触区。
9.根据权利要求8所述的方法,其中将激活的粒子喷射在接触区上以形成接触垫。
10.根据权利要求7所述的方法,其中将激活的粒子喷射在半导体晶圆或裸片上以完全覆盖所述半导体或裸片的至少一面。
11.根据权利要求7所述的方法,其中将激活的粒子喷射在未加工的半导体晶圆或裸片上。
12.根据权利要求7所述的方法,其中所述半导体晶圆或裸片的所述层是所述半导体晶圆或裸片的主体层。
13.根据权利要求1所述的方法,其中所述混合物形成焊接材料。
14.根据权利要求13所述的方法,其中所述材料是不同的金属。
15.根据权利要求1所述的方法,还包括对半导体晶圆或裸片的表面进行图案化,其中将激活的粒子喷射在半导体晶圆或裸片上以在图案化的半导体晶圆或裸片上生成粒子层。
16.根据权利要求15所述的方法,其中将半导体晶圆或裸片的表面图案化以包括图案化的掩模。
17.根据权利要求16所述的方法,还包括通过镶嵌技术对粒子层进行图案化。
18.一种粒子沉积设备,包括:
第一提供部件,将等离子体射流提供到反应室;
第二提供部件,将载运气体提供到反应室;
所述反应室用于混合等离子体射流和载运气体以生成混合物,其中所述反应室包括用于发射混合物的出口;
传导通道,其具有由所述出口形成的第一端以及由粒子沉积设备的至少一个孔形成的第二端,所述至少一个孔具有将要沉积在载体上的互连结构的形状,
其中所述载体是半导体晶圆、半导体裸片或印刷电路板;
其中至少两种材料的粒子被提供到相同反应室的相同内部空间中的等离子体,使得所述粒子被等离子体激活,并且使得所述至少两种材料的激活的粒子的混合物被形成,其中所述混合物被喷射在半导体晶圆或裸片上以形成包括所述至少两种材料的粒子的混合物的层。
19.根据权利要求18所述的粒子沉积设备,其中所述孔的形状的至少一部分对应于互连线的形状。
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CN102738040A (zh) | 2012-10-17 |
US8338317B2 (en) | 2012-12-25 |
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US9537056B2 (en) | 2017-01-03 |
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