CN103681609B - 集成电路、芯片封装以及用于制造集成电路的方法 - Google Patents

集成电路、芯片封装以及用于制造集成电路的方法 Download PDF

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Publication number
CN103681609B
CN103681609B CN201310680452.4A CN201310680452A CN103681609B CN 103681609 B CN103681609 B CN 103681609B CN 201310680452 A CN201310680452 A CN 201310680452A CN 103681609 B CN103681609 B CN 103681609B
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carrier
inorganic material
material layer
wafer
layer
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CN103681609A (zh
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K·侯赛尼
J·马勒
A·毛德
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

集成电路、芯片封装以及用于制造集成电路的方法。提供了一种集成电路，该集成电路包括：载体，其包括至少一个电子部件和设置在该载体的第一侧面上的至少一个接触区，其中该至少一个电子部件被电连接至该至少一个接触区；无机材料层，其被晶片结合至载体的第一侧面，其中该载体具有第一热膨胀系数，且其中无机材料层具有第二热膨胀系数，其中第二热膨胀系数相较于第一热膨胀系数具有小于100％的差值；以及至少一个接触孔，其穿过无机材料层形成，其中该至少一个接触孔接触该至少一个接触区。

Description

集成电路、芯片封装以及用于制造集成电路的方法
技术领域
各种实施例总体上涉及一种集成电路、一种芯片封装以及一种用于制造集成电路的方法。
背景技术
功率半导体部件可以在半导体晶片中使用已知工艺来形成或制造。在这些工艺的一部分中，可以采用有机聚合物材料、模塑料或层压体来对半导体部件进行封装，其可以被沉积在半导体晶片表面上方或上面，由此覆盖功率半导体部件的表面。采用聚合物材料的封装可能导致高吸湿性，且导致不能被调整以适应半导体部件的热膨胀系数(CTE)。即，在当前使用的封装材料与功率半导体部件之间的CTE不匹配可能导致可靠性问题。即使有机聚合物材料不包含无机填充微粒，其还是会遭受低热导率。
发明内容
各种实施例提供了一种集成电路，其包括：载体，其包括至少一个电子部件和被设置在该载体的第一侧面上的至少一个接触区，其中该至少一个电子部件被电连接至该至少一个接触区；无机材料层，其被晶片结合至该载体的第一侧面，其中该载体具有第一热膨胀系数，且其中该无机材料层具有第二热膨胀系数，其中该第二热膨胀系数相较于第一热膨胀系数具有小于100％的差值；以及至少一个接触孔，其穿过无机材料层形成，其中该至少一个接触孔接触该至少一个接触区。
附图说明
在附图中，贯穿不同的视图，相似的参考标记一般指代相同的部分。附图不必按比例，而是一般地将重点放在示出本发明的原理上。在下列描述中，本发明的各种实施例参考下列附图来描述，其中：
图1示出了根据一个实施例的用于制造集成电路的方法；
图2A至2I示出了根据各种实施例的用于制造集成电路的方法；
图3A和3B、2A示出了根据各种实施例的用于制造集成电路的方法的一部分；以及
图4示出了根据一个实施例的集成电路。
具体实施方式
以下的详细描述引用附图，所述附图借助图示示出了其中可以实施本发明的特定的细节和实施例。
本文使用词“示例性的”来意指“用作实例，例子，或者示例”等。本文描述为“示例性的”的任何实施例或者设计不一定被解释为比其它实施例或者设计优选或者有利。
关于在侧面或者表面的“上面”形成的沉积材料而使用的词“上面”可以在本文被用来表示沉积材料可以“直接”形成在暗指的侧面或者表面“上”，例如与暗指的侧面或者表面直接接触。关于在侧面或者表面的“上面”形成的沉积材料而使用的词“上面”可以在本文被用来表示沉积材料可以“间接”形成在暗指的侧面或者表面“上”，其中在暗指的侧面或者表面和沉积材料之间布置一个或者多个另外的层。
当前，由于当前使用的封装材料的限制导致的CTE不匹配和吸湿性，用于封装芯片的已知方法仍然受到稳定性问题的困扰。除了为半导体部件提供包围结构，封装材料还需要电隔离可以被连接至半导体部件的电互连。
已经熟知封装材料被用作覆盖材料，其可以被结合至半导体晶片之上。覆盖材料可由玻璃或引线框材料制造，且如果需要的话，甚至可以被提供有导电材料。封装材料可以包括无机或有机材料也可以是可能的，其可以用于电钝化和绝缘，并可以提供气密密封。电气布线或重新布线可以一般地形成在半导体晶片的表面上面，在覆盖材料下方的区域中。
各种实施例可以处理与可靠性相关联的问题，例如通过改善在半导体部件与外壳封装材料之间的热膨胀系数(CTE)不匹配。各种实施例可以提供用于半导体部件的封装材料作为外壳材料，其中该封装材料可以是无机材料。该无机材料可以减小或消除吸湿性，并可以降低在封装材料，有源电部件与在其中可以形成有源电部件的半导体晶片之间的CTE不匹配。外壳封装材料可以是晶片载体，例如，硅晶片，其可以为半导体部件的晶片的背面的变薄提供结构支撑。外壳封装可以，除了覆盖或至少部分地包围半导体晶片的有源电部件以外，还提供用于穿过该外壳封装材料形成用于接触该半导体部件的接触孔的装置。
图1示出了根据一个实施例的用于制造集成电路的方法100。该方法100可以包括：
将无机材料层晶片结合至载体的第一侧面，该载体包括至少一个电子部件和被设置在该载体的第一侧面上面的至少一个接触区，其中至少一个电子部件被电连接至该至少一个接触区(在110中)；以及
穿过该无机材料层形成至少一个接触孔，其中该至少一个接触孔接触至少一个接触区(在120中)。
图2A至2I示出了根据一个实施例的用于制造集成电路的方法中的处理阶段的各示意性截面图。
在视图210中，图2A示出了根据一个实施例的载体202。载体202可以包括半导体晶片，例如半导体晶片衬底。根据各种实施例，载体202可以包括下述中的至少一个：硅(Si)，例如，掺杂或未掺杂的硅；锗(Ge)；砷化镓(GaAs)；磷化铟(InP)；氮化镓(GaN)；碳化硅(SiC)；和砷化铟镓(InGaAs)。
视图210示出了载体202，其包括在载体202中形成的一个或多个电部件214。这些电部件214可以典型地在半导体前端工艺期间被制造，其中一个或多个电部件的电学有源区域可以在载体202中形成。
有源电路区域可以一般地形成在载体202的顶面处，例如在第一芯片侧面206处，且可以包括具有不同的电导率、掺杂类型、掺杂浓度和尺寸的不同区域。这些有源电路区域可以包括，例如源极区和／或栅极区和／或沟道区。
作为实例，为说明根据各种实施例的根本原理，电部件214可以是单个垂直场效应晶体管，例如功率金属氧化物半导体场效应晶体管(MOSFET)，其可以包括源极／漏极区，体区和绝缘栅，其未在图中示出，但可以被共同称为电部件214。载体202可以包括至少一个接触区204，例如，接触焊盘，其可以在第一芯片侧面206上方或上面形成。(多个)接触区(204)可以被形成在有源电路区上方，并与电部件214的有源电路区电接触。(多个)接触区204可以被称为(多个)接触焊盘或(多个)正面电极。载体202可以包括正面电极，作为实例，源极电极204S和栅极电极204G。源极电极204S可以被设置在电部件的源极区上方并与其电连接。栅极电极204G可以被设置在栅极绝缘层上方，并与电部件的体区电绝缘。在功率MOSFET中，以及通常在功率器件中，电流可以在功率晶体管中垂直地流动，例如在第一芯片侧面206与第二芯片侧面208之间。电流，例如电子，可以在设置在第一芯片侧面206上方或直接设置在第一芯片侧面206上面的(多个)接触区204与可以设置在第二芯片侧面208上方或直接设置在第二芯片侧面208上面的(多个)另外的接触区(未示出)之间流动。作为实例，电流，例如电子，可以在源极电极204S与漏极电极204D(未示出)之间流动。在后续处理阶段中形成的漏极电极204D可以设置在漏极区上方，其可以在载体202的衬底区212中形成，或可以成为载体202的衬底区212的一部分。漏极电极204D可以被称为背面金属化，并可以在后续的处理阶段中形成，例如在从第二芯片侧面208打薄载体202直到得到合适的厚度为止之后。
正如可以理解的那样，上述原理可以应用于其他集成电路或垂直和／或横向的电部件。根据各种其他实施例，电部件214可以包括下述中的至少一种：功率双极型晶体管、功率场效应晶体管、功率绝缘栅双极型晶体管、晶闸管、MOS控制的晶闸管、可控硅整流器、功率肖特基二极管、碳化硅二极管和氮化镓器件。
可以理解，载体202可以包括或可以是在尺寸上变化的半导体晶片。作为实例，载体202可以具有从大约25mm变化至大约500mm的直径，例如从大约100mm变化至大约500mm，例如从大约200mm变化至大约400mm。然而可以理解，该载体202可以不限于这些尺寸，且在本说明书中描述的原理可以适用于这些描述的范围之外的其他尺寸的载体。
视图210示出了载体202，其可以包括两个邻近的电部件214。可以理解，多个电部件214，例如多达两个、或三个、或四个、或甚至几十、几百或几千的电部件，可以形成在单个半导体晶片中，即载体202。作为实例，根据各种实施例，载体202可以包括多个芯片或管芯，每个芯片或管芯包括至少一个电部件。为简单起见，在视图210中示出的邻近的电部件214可以被说明性地示出为属于分开的芯片，例如芯片1和芯片2。即，在后续的芯片切割工艺中，芯片1可以与芯片2分离或分别处理。然而可以理解，依赖于怎样绘制或确定切割线，每一个分别处理的芯片可以包括多于一个的电部件214。作为实例，根据其他实施例，邻近的电子部件214可以是在芯片切割之后的单个芯片的一部分。
可以理解，此处和后面描述的工艺可以应用于单个芯片或应用于晶片级，即，并行地且同时地应用到形成在单个晶片内的多个芯片。
如视图210所示，载体202可以包括形成在载体202的第一侧面206上方的介电层216。在第一侧面206上方形成(多个)介电层216可以是可能的，然而，为简单起见，在图中仅示出了单个介电层216。通常，介电层216可以形成在(多个)接触区204之间的区域中，作为实例，在邻近的(多个)源极电极204S与(多个)栅极电极204G之间，并可以用于将(多个)导电源极电极204S与(多个)栅极电极204G彼此分隔并电隔离。介电层216可以包括氧化硅或由氧化硅构成，例如磷硅酸玻璃(PSG)和／或硼磷硅酸玻璃(BPSG)，其可以使用沉积技术来沉积，例如化学气相沉积(CVD)、溅射、高密度等离子体、或热氧化中的至少一种。介电层216可以形成为形成在载体202的第一侧面206上方的电介质间金属化层的一部分。
图2B至2D，在视图220至240中，示出了无机材料层218是如何被晶片结合至载体202的第一侧面206的。
无机材料层218可以包括晶片，其包括无机材料或由无机材料构成。根据一些实施例，无机材料层218可以包括硅。作为实例，无机材料层218可以包括硅晶片，例如未掺杂的硅晶片。根据其他实施例，无机材料层218可以包括来自以下材料组中的至少一种，该材料组包括：硅(Si)、砷化镓(GaAs)、磷化铟(InP)、氮化镓(GaN)、玻璃、氧化铝(Al2O3)和碳化硅(SiC)。
载体202可以具有从大约250μm变化至大约900μm的厚度tc，例如从大约300μm变化至大约600μm。根据一些实施例，无机材料层218可以具有从大约250μm变化至大约900μm范围的厚度ti，例如，从300μm变化至600μm。然而可以理解，载体202和无机材料218不限于具有这些厚度，并还可以包括不在上述范围内的其他厚度。
无机材料层218可以具有顶面222和底面224，底面224面向与顶面222相反的方向。无机材料层218可以包括形成在底面224上方的另外的介电层226。另外的介电层226可以包括氧化硅或由氧化硅构成，例如磷硅酸玻璃(PSG)和／或硼磷硅酸玻璃(BPSG)。另外的介电层226可以包括与介电层216相同的材料或由与介电层216相同的材料形成。
如在图2C的视图230中所示的，载体202和无机材料层218可以被带到一起。载体202的第一芯片侧面206可以被接合至无机材料层218的底面224。第一芯片侧面206和底面224可以经由介电层216和另外的介电层226接合在一起。
例如通过将无机材料层218直接结合至载体202的第一侧面206，无机材料层218可以被晶片结合至载体202的第一侧面206。作为实例，在图2C中示出了阳极结合。在阳极结合中，有源的硅晶片，例如载体202，在不需要额外的中间粘合剂或胶粘剂的情况下，可以经由二氧化硅介电层和另外的介电层216、226被直接接合至无机材料层218。可以理解，根据其他实施例，可以执行其他用于将载体202晶片结合至无机材料层218的方法。这些方法可以包括共熔结合、热压缩结合和反应结合中的至少一种。
根据其他实施例，在载体202与无机材料218之间使用中间层248，将载体202晶片结合至无机材料218也可以是可能的。用于间接结合的这类方法可以包括共晶结合、玻璃粉结合和粘合剂结合。
作为实例，在图3A和3B示出的，间接结合可以以如在截面图310和320中所示的那样被执行。中间层248可以沉积在另外的介电层226的上方或直接沉积在其上面，例如如视图310中所示，沉积在无机材料层218的底面224上方。作为实例，对于粘合剂结合工艺，中间层248可以包括胶浆或粘合浆248，其可以被沉积，例如均匀地旋涂，至另外的介电层226上面。通过施加将无机材料层218和载体202压在一起的热和压力，无机材料层218和载体202可以被密封在一起。根据其他实施例，例如其中可以应用共晶结合用于将无机材料层218接合至载体202，中间层248可以包括金属或金属合金，例如包括金(Au)或铝(Al)。根据其他实施例，例如玻璃粉结合，中间层248可以包括玻璃粉。
如在视图240和320中所示，无机材料层218载体202可以被气密密封和／或接合至无机材料层218。在视图240中，载体202和无机材料层218被示出为彼此直接接合。在视图320中，载体202和无机材料层218被示出为通过中间层248彼此接合。
可以理解，载体202可以具有第一热膨胀系数(CTE1)，且无机材料层218可以具有第二热膨胀系数(CTE2)。
对于载体202和无机材料层218的材料的典型的CTE值可以如下：
硅可以具有大约2.8×10-6／K的CTE；
砷化镓可以具有大约6.8×10-6／K的CTE；
磷化铟可以具有大约4.75×10-6／K的CTE；
氮化镓可以具有大约5.6×10-6／K的CTE；
碳化硅可以具有大约4.2×10-6／K的CTE。
可以选择载体202和无机材料层218，其中第二热膨胀系数(CTE2)相较于第一热膨胀系数(CTE1)可以具有小于100％的差值。换句话说，其中换句话说，CTE2与CTE1之间的差值可以大约等于或小于CTE1的值，换句话说，其中CTE2-CTE1≤CTE1。可以理解，根据一些实施例，所述差值可以指的是CTE2与CTE1之间的差值的绝对值。
根据一些实施例，载体202和无机材料层218可以由相同的一种或多种材料形成。例如，载体202和无机材料层218可以具有近似相等的CTE，即CTE1可以大约等于CTE2。作为实例，载体202可以包括硅晶片，其可以具有大约2.8(×10-6／K)的CTE，且无机材料层218可以包括硅晶片，其可以具有大约2.8(×10-6／K)的CTE。根据一些实施例，可以选择载体202和无机材料层218，其中CTE2相较于CTE1可以具有小于100％的差值。作为实例，载体202可以包括硅晶片，其可以具有大约2.8(×10-6／K)的CTE，且无机材料层218可以包括碳化硅晶片，其可以具有大约4.2(×10-6／K)的CTE。根据一些实施例，可以选择载体202和无机材料层218，其中CTE2相较于CTE1可以具有大约100％的差值。作为实例，载体202可以包括硅晶片，其可以具有大约2.8(×10-6／K)的CTE。无机材料层218可以包括氮化镓晶片，其可以具有大约5.6(×10-6／K)的CTE。
除了上述用于无机材料218的可能材料，根据其他实施例，无机材料层218还可以包括氧化铝或玻璃。作为实例，氧化铝可以具有大约6×10-6／K至大约8×10-6／K的CTE。玻璃，例如硼硅玻璃，可以具有大约3.0×10-6／K的CTE。石英玻璃可以具有大约0.5×10-6／K的CTE。钠钙玻璃可以具有大约7.6×10-6／K的CTE。
作为实例，载体202可以包括碳化硅晶片，其可以具有大约4.2(×10-6／K)的CTE，且无机材料层218可以包括硼硅玻璃，其可以具有大约3(×10-6／K)的CTE。
图2E，在视图250中，示出了有源的晶片(载体202)的背面打薄。载体202可以从载体202的第二芯片侧面208打薄，直到得到所需的最终厚度tf为止。根据一些实施例，所需的最终厚度，tf，可以是大约100μm。根据一些实施例，所需的最终厚度，tf，可以小于大约100μm；作为实例，从大约50μm变化至大约100μm。在打薄期间，无机材料层218可以是载体或载体202的支撑支架，且在载体202打薄之后是平坦的。根据一些实施例，随后，无机材料层218也可以被打薄，例如从顶面222或无机材料层218，直到得到所需的最终厚度tfi为止。无机材料层218的最终厚度可以是大约100μm，或小于大约100μm；作为实例，从大约50μm变化至大约100μm。可以理解，给出的范围仅是充当实例，且根据其他实施例，处于这些范围之外的其他最终厚度也可以是可能的。
图2F在视图260中示出了在晶片结合和/或打薄之后的被晶片结合的结构。如在视图260所示，无机材料层的至少一部分可以被选择性地去除以在(多个)接触区204上方形成(多个)孔或(多个)沟道228。可以穿过无机材料层218形成(多个)沟道228，并可以穿过无机材料层218的选择性去除的部分来形成(多个)沟道228。(多个)沟道228可以从无机材料层218的顶面222向下延伸至形成在载体202的第一芯片侧面206上面的(多个)接触区204。作为实例，通过无机材料层218的选择性去除的部分，可以暴露出源极电极204S和栅极电极204G。作为实例，在源极电极204S上方形成沟道228S，由于去除了覆盖源极电极204S的无机材料层218的一部分，由此暴露源极电极204S。作为另一个实例，在栅极电极204G上方形成沟道228G，由于去除了覆盖栅极电极204G的无机材料层218的另外的一部分，由此暴露栅极电极204G。
在并行的或后续的工艺中，可以穿过载体202和无机材料层218两者，并另外地穿过介电层216和另外的介电层226形成通孔或直通沟道232D。直通沟道232D可以从无机材料层218的顶面222延伸至载体202的第二芯片侧面208。根据一些实施例，可以通过蚀刻，例如通过Bosch工艺，来执行无机材料层218的(多个)部分的选择性去除。根据其他实施例，可以通过机械去除过程，例如通过打孔或激光打孔，来执行无机材料层218的(多个)部分的选择性去除。
图2G在视图270中示出了在(多个)接触区204上方以及无机材料层218的正面222和载体202的第二芯片侧面208上方的金属晶种层235的沉积。金属晶种层235可以具有从大约50nm变化至大约140nm的厚度，例如从大约75变化至大约110nm。金属晶种层236可以包括来自下列材料组中的至少一种金属，元素或合金，该组包括：铜、铝、银、锡、金、钯、锌、镍、铁。可以理解，金属晶种层235可以被图案化或构造，为将导电材料234电流沉积或电镀至金属晶种层235上做准备。
图2H在视图280中示出了例如通过电流沉积，例如电镀将导电材料234沉积在金属晶种层235上面。
可以在晶种层235的上方以及正面222和第二芯片侧面208的上方形成导电材料234。可以在(多个)沟道228，例如228S、228G和沟道232D中形成导电材料234，且可以在(多个)沟道228和232D中至少部分地填充或充分地填充导电材料234。可以在第二芯片侧面208上方，例如在设置在第二芯片侧面208上方的金属晶种层235的上方形成导电材料234的一部分234B。可以在正面222的上方形成导电材料234的一部分234F。
在(多个)沟道228、232D中沉积导电材料234，可以导致形成在沟道228S、228G和232D中形成的(多个)导电孔236的形成。(多个)导电孔236，例如236S、236G，可以包括导电材料234或由导电材料234构成。(多个)导电孔236S、236G可以穿过无机材料层218形成，或穿过无机材料层218延伸。(多个)导电孔236S、236G可以与(多个)接触区204物理和电连接。
作为实例，在沟道228S中形成的导电材料234可以形成接触孔236S，其可以穿过无机材料层218延伸。可以在接触区204S上方形成接触孔236S，且接触孔236S可以与接触区204S物理和电连接。相似地，在沟道228G中形成的导电材料234可以形成接触孔236G，其可以穿过无机材料层218延伸。可以在接触区204G上方形成接触孔236G，且接触孔236G可以与接触区204G物理和电连接。
在沟道232D内形成的导电材料234可以形成另外的接触孔236D，其可以穿过无机材料层218、介电层216、另外的介电层226和载体202延伸。另外的接触孔236D可以与在载体202的第二侧面208上方形成的部分234B连接。可以理解，部分234B可以覆盖形成在载体202的第二侧面208上面的另外的接触区238的至少一部分。另外的接触区238可以通常指的是载体202的第二侧面208上面的区域，其中可以形成前述的背面金属化或漏极电极204D(未示出)。可以理解，导电材料234的部分234B可以是漏极电极204D(未示出)或形成在载体的第二侧面208上面的背面金属化的一部分，其中234B可以被电耦合至电部件214，例如至形成在衬底区域212内的电部件214的漏极区。另外的接触孔236D，被电连接至234B，可以将部分234B从第二芯片侧面208上面的另外的接触区238电重定向至顶面222。
导电材料234(以及接触孔236S、236D、236G)可以包括来自下列材料组中的至少一种材料、元素或合金，该组包括：铜、铝、银、锡、金、钯、锌、镍、铁。
可以理解，可以执行电镀工艺，以将导电材料234电镀在金属晶种层235的多个结构部分上方。电镀的导电材料234可以形成普通的连续导电材料或层，基本上无缝地接合在一起。作为实例，(多个)接触孔236以及另外的接触孔236D可以连续地接合至部分234F和234B。
随后，还可以可选地例如通过电镀在导电材料234的一部分234F的上方或直接在其上面沉积焊接材料242。换句话说是在无机材料层218的顶面222的上方。可以在无机材料层218的顶面222处在(多个)接触孔236S和／或236G和／或236D的上方形成焊接材料242。
图2I，在视图290中，示出了结构化和随后的单体化工艺。可以首先执行结构化，用来分离用于芯片的金属化接触。这之后可以是例如通过执行切割工艺使分别处理的部件单体化。
为了结构化和分离金属化接触，可以使用掩模，例如光刻。可以在导电材料234中，例如在导电材料234的一部分234F中，可以形成、例如蚀刻一个或多个孔244。孔244或间隙可以将接触孔236、236D彼此分开。作为实例，可以被电连接至源极电极204S的接触孔236S可以与可以被电连接至栅极电极204G的接触孔236G电隔离。这样，被连接至源极电极204S和栅极电极204G的接触金属化孔可以不被短路。此外，接触孔236S和236G还可以均通过孔244与另外的接触孔236D分开，并因此与可以被电连接至第二芯片侧面208上面的另外的接触区238的另外的接触孔236D电隔离。另外的接触孔236D可以经由部分234B被电连接至另外的接触区238，其可以形成或者是形成在另外的接触区238上方的背面金属化的至少一部分，其可以与电部件214的漏极区电连接。
为了分开芯片1与芯片2，可以通过蚀刻或者选择性地去除另外的接触孔236D的一部分形成从无机材料层218的顶面222延伸至载体202的第二芯片侧面208的通孔246。通孔246的形成可以分开芯片封装1与芯片封装2。
随后，被分别处理的半导体部件，例如芯片封装1和／或芯片封装2，可以被接触，例如一个一个单独地接触至外部电路，例如至印刷电路板。可以理解，无机材料层218的顶面222可以是芯片封装1的侧面，该侧面可以被接合至外部电路，例如至印刷电路板。(多个)接触孔236S、236G、236D，在用焊接材料242完成或没有用焊接材料242完成的情况下，可以均被焊接或接合至印刷电路板的单独的引脚。
可以执行根据各种实施例的方法200，以制造根据各种实施例的集成电路或芯片封装。芯片封装1，如在视图290所示，其可以由方法200制造，可以包括半导体晶片202，其可以包括至少一个电子电路214和形成在晶片第一侧面206上方的至少一个接触焊盘204。电子电路214可以被电连接至接触焊盘204。芯片封装1可以包括层218，其可以具有相较于半导体晶片202的热膨胀系数小于100％的热膨胀系数差值。层218可以在至少一个接触焊盘204的上方被晶片结合至半导体晶片202。芯片封装1可以包括至少一个电互连236，其穿过层218形成并电接触接触焊盘204。
图4示出了根据各种实施例制造的集成电路452的截面图410。集成电路452可以包括已经关于芯片封装1描述的一个或多个或者所有的特征。集成电路452可以包括：载体202，其包括至少一个电子部件214和设置在载体202的第一侧面206上面的至少一个接触区204。电子部件214可以被电连接至接触区204。集成电路452可以包括被晶片结合至载体202的第一侧面206的无机材料层218。载体202可以具有第一热膨胀系数CTE1。无机材料层218可以具有第二热膨胀系数CTE2。第二热膨胀系数CTE2相较于第一热膨胀系数CTE2可以具有小于100％的差值。可以穿过无机材料层218形成至少一个接触孔236。接触孔236可以接触接触区204。
各种实施例提供了一种连接技术，其可能需要减少数目的外壳工艺。根据各种实施例，晶片，可以起嵌入材料的作用，并可以起载体材料的作用，用于承载有源电部件的半导体晶片的背面打薄。此外，晶片还可以用作钝化材料，其可以将金属互连彼此分隔或电隔离。由于各种实施例提供了从典型的有机封装材料的偏离，可以减小与吸湿性相关联的挑战。良好的热冷却可以被实现，并由于调整的CTE，例如在有源的半导体晶片与封装晶片之间匹配的CTE，可以实现更高的部件可靠性。此外，在外壳级的许多串行工艺可以由更少的并行工艺替代。
特别地，可以采用无机材料，例如硅，在晶片级封装半导体晶片或部件。无机材料，即封装介质，可以用作支撑背面的打薄的晶片载体。此外，未掺杂的硅，在无离子注入区的情况下，作为嵌入和覆盖材料，例如还作为载体，可以允许穿过覆盖材料形成直通接触孔。因此，可以在有源晶片处从电接触的正面得到垂直(持续)电流，以及还可以穿过封装的半导体晶片得到垂直信号流。封装硅晶片可以被提供有横向的和／或垂直的隔离层，且可以使用典型的晶片处理工艺，例如热氧化，沉积工艺。
各种实施例提供了一种集成电路，包括：载体，其包括至少一个电子部件和设置在载体的第一侧面上的至少一个接触区，其中该至少一个电子部件被电连接至该至少一个接触区；无机材料层，其被晶片结合至该载体的第一侧面，其中该载体具有第一热膨胀系数，且其中无机材料层具有第二热膨胀系数，其中第二热膨胀系数相较于第一热膨胀系数具有小于100％的差值；以及至少一个接触孔，其穿过无机材料层形成，其中该至少一个接触孔接触该至少一个接触区。
根据一个实施例，该载体包括半导体晶片。
根据一个实施例，该载体包括来自下列材料组中的至少一种材料，该材料组包括：硅、砷化镓、磷化铟、氮化镓和碳化硅。
根据一个实施例，该第二热膨胀系数小于或者大约等于第一热膨胀系数。
根据一个实施例，该无机材料层包括半导体晶片。
根据一个实施例，该无机材料层包括来自下列材料组中的至少一种材料，该材料组包括：硅、砷化镓、磷化铟、氮化镓、玻璃、氧化铝和碳化硅。
根据一个实施例，该无机材料层由与该载体相同的材料形成。
根据一个实施例，该无机材料层被直接晶片结合至该载体的第一侧面。
根据一个实施例，该载体和无机材料层均包括硅晶片。
根据一个实施例，该无机材料具有相较于该载体材料的CTE小于100％的CTE差值。
根据一个实施例，该无机材料层通过共熔结合、热压缩结合、反应结合以及阳极结合中的至少一种被直接晶片结合至该载体的第一侧面。
根据一个实施例，该无机材料层通过共晶结合、玻璃粉结合和粘合剂结合中的至少一种被晶片结合至该载体的第一侧面。
根据一个实施例，该无机材料层包括从大约20μm变化至500μm的厚度。
根据一个实施例，该载体包括从大约20μm变化至250μm的厚度。
根据一个实施例，在该无机材料层的上方形成该至少一个接触孔的至少一部分。
根据一个实施例，该至少一个接触孔包括导电材料。
根据一个实施例，该至少一个接触孔包括导电材料。
根据一个实施例，该至少一个接触孔包括来自以下材料组中的至少一种材料、元素或合金，该组包括：铜、铝、银、锡、金、钯、锌、镍、铁。
根据一个实施例，该集成电路进一步包括至少一个另外的接触孔，其穿过该无机材料层形成，该至少一个另外的接触孔在该无机材料层的顶面与该载体的第二侧面之间延伸；以及该至少一个另外的接触孔覆盖形成在该载体的第二侧面上面的另外的接触孔的至少一部分。
根据一个实施例，该集成电路进一步包括在无机材料层的顶面处该至少一个接触孔上方设置的焊接材料。
根据一个实施例，该集成电路进一步包括在无机材料层的顶面处该至少一个接触孔以及该至少一个另外的接触孔上方设置的焊接材料。
各种实施例提供一种芯片封装，其包括：半导体晶片，其包括至少一个电子电路和形成在晶片第一侧面上方的至少一个接触焊盘，其中该至少一个电子部件被电连接至该至少一个接触焊盘；层，其具有相较于半导体晶片的热膨胀系数小于100％的热膨胀系数差值，其中该层在该至少一个接触焊盘的上方被晶片结合至半导体晶片；以及至少一个电互连，其穿过该层形成，并电接触该至少一个接触焊盘。
根据一个实施例，该半导体晶片包括来自下列材料组中的至少一种材料，该材料组包括：硅、砷化镓、磷化铟、氮化镓和碳化硅。
根据一个实施例，该层包括由与半导体晶片相同的材料形成的衬底。
根据一个实施例，该层包括来自下列材料组中的至少一种材料，该材料组包括：硅、砷化镓、磷化铟、氮化镓、玻璃、氧化铝和碳化硅。
各种实施例提供了一种用于制造集成电路的方法，该方法包括：将无机材料层晶片结合至载体的第一侧面，该载体包括至少一个电子部件和设置在该载体的第一侧面上面的至少一个接触区，其中该至少一个电子部件被电连接至该至少一个接触区；以及穿过该无机材料层形成至少一个接触孔，其中该至少一个接触孔接触该至少一个接触区。
根据一个实施例，将无机材料层晶片结合至载体的第一侧面包括将该无机材料层直接结合至该载体的第一侧面。
根据一个实施例，将无机材料层晶片结合至该载体的第一侧面包括通过阳极结合、共熔结合、热压缩结合、反应结合、共晶结合、玻璃粉结合和粘合剂结合中的至少一种将无机材料层晶片结合至该载体的第一侧面。
根据一个实施例，将无机材料层晶片结合至载体的第一侧面包括将包括半导体晶片的无机材料层晶片结合至该载体的第一侧面。
根据一个实施例，将无机材料层晶片结合至载体的第一侧面包括将包括硅、砷化镓、磷化铟、氮化镓、玻璃、氧化铝或碳化硅中的至少一种的无机材料层晶片结合至该载体的第一侧面。
根据一个实施例，穿过该无机材料层形成该至少一个接触孔包括选择性地去除该无机材料层的至少一部分，以形成从该至少一个接触区延伸至该无机材料层的顶面的沟道，并在该沟道中沉积导电材料，其中导电材料接触该至少一个接触区。
根据一个实施例，该方法进一步包括：穿过该无机材料层形成至少一个另外的接触孔，该至少一个另外的接触孔在该无机材料层的顶面与该载体的第二侧面之间延伸，该至少一个另外的接触孔覆盖形成在该载体的第二侧面上面的另外的接触区的至少一部分。
根据一个实施例，该方法进一步包括在该无机材料层的顶面处该至少一个接触孔的上方设置焊接材料。
根据一个实施例，该载体具有第一热膨胀系数，且其中该无机材料层具有第二热膨胀系数，其中该第二热膨胀系数相较于第一热膨胀系数具有小于100％的差值。
虽然已经参照特定实施例具体示出和描述了本发明，但是本领域技术人员应该理解在不脱离如由所附权利要求限定的本发明的精神和范围的情况下，可以在其中作出各种形式和细节上的变化。本发明的范围因而由所附权利要求表明，并且因此在权利要求的等同物的含义和范围内的所有改变旨在被包含。

Claims (33)

1.一种集成电路，包括：
载体，该载体包括至少一个电子部件和设置在载体的第一侧面的至少一个接触区，其中该至少一个电子部件电连接至该至少一个接触区；
无机材料层，其被晶片结合至该载体的第一侧面，其中该载体具有第一热膨胀系数，且其中该无机材料层具有第二热膨胀系数，其中第二热膨胀系数相较于第一热膨胀系数具有小于100%的差值；
至少一个接触孔，其穿过无机材料层形成，其中该至少一个接触孔接触该至少一个接触区；以及
中间层，在无机材料层和载体的第一侧面之间，其中该中间层包括来自下述材料组中的一种材料，该材料组包括金、铝和玻璃粉。
2.根据权利要求1的集成电路，
其中载体包括半导体晶片。
3.根据权利要求1的集成电路，
其中载体包括来自下列材料组中的至少一种材料，该材料组包括：硅、砷化镓、磷化铟、氮化镓和碳化硅。
4.根据权利要求1的集成电路，
其中第二热膨胀系数小于或大约等于第一热膨胀系数。
5.根据权利要求1的集成电路，
其中无机材料层包括半导体晶片。
6.根据权利要求1的集成电路，
其中无机材料层包括来自下列材料组中的至少一种材料，该材料组包括：硅、砷化镓、磷化铟、氮化镓、玻璃、氧化铝和碳化硅。
7.根据权利要求1的集成电路，
其中无机材料层由与载体相同的材料形成。
8.根据权利要求1的集成电路，
其中无机材料层被直接晶片结合至载体的第一侧面。
9.根据权利要求1的集成电路，
其中载体和无机材料层均包括硅晶片。
10.根据权利要求1的集成电路，
其中无机材料具有相较于载体的材料的CTE小于100%的CTE差值。
11.根据权利要求1的集成电路，
其中无机材料层通过共熔结合、热压缩结合、反应结合和阳极结合中的至少一种直接晶片结合至载体的第一侧面。
12.根据权利要求1的集成电路，
其中无机材料层通过共晶结合、玻璃粉结合和粘合剂结合中的至少一种晶片结合至载体的第一侧面。
13.根据权利要求1的集成电路，
其中无机材料层包括从大约20μm变化至500μm的厚度。
14.根据权利要求1的集成电路，
其中载体包括从大约20μm变化至250μm的厚度。
15.根据权利要求1的集成电路，
其中在无机材料层上方形成该至少一个接触孔的至少一部分。
16.根据权利要求1的集成电路，
其中该至少一个接触孔包括导电材料。
17.根据权利要求1的集成电路，
其中该至少一个接触孔包括来自下列材料组的至少一种材料、元素或合金，该组包括：铜、铝、银、锡、金、钯、锌、镍、铁。
18.根据权利要求1的集成电路，进一步包括
至少一个另外的接触孔，其穿过无机材料层形成，该至少一个另外的接触孔在无机材料层的顶面和载体的第二侧面之间延伸；且
其中该至少一个另外的接触孔覆盖形成在载体的第二侧面上面的另外的接触区的至少一部分。
19.根据权利要求1的集成电路，进一步包括
焊接材料，其设置在无机材料层的顶面处的该至少一个接触孔上方。
20.根据权利要求18的集成电路，进一步包括
在无机材料层的顶面处设置在该至少一个接触孔和该至少一个另外的接触孔上方的焊接材料。
21.一种芯片封装，包括：
半导体晶片，其包括至少一个电子电路和形成在晶片第一侧面上方的至少一个接触焊盘，其中该至少一个电子部件被电连接至该至少一个接触焊盘；
层，其具有相较于半导体晶片的热膨胀系数小于100%的热膨胀系数差值，其中该层在该至少一个接触焊盘上方被晶片结合至半导体晶片；
至少一个电互连，其穿过该层形成，并电接触该至少一个接触焊盘；以及
中间层，在该层和半导体晶片的第一侧面之间，其中该中间层包括来自下述材料组中的一种材料，该材料组包括金、铝和玻璃粉。
22.根据权利要求21的芯片封装，其中该半导体晶片包括来自以下材料组中的至少一种材料，该材料组包括：硅、砷化镓、磷化铟、氮化镓和碳化硅。
23.根据权利要求21的芯片封装，
其中该层包括由与半导体晶片相同材料形成的衬底。
24.根据权利要求21的芯片封装，
其中该层包括来自以下材料组中的至少一种材料，该材料组包括：硅、砷化镓、磷化铟、氮化镓、玻璃、氧化铝和碳化硅。
25.一种用于制造集成电路的方法，该方法包括：
将无机材料层晶片结合至载体的第一侧面，该载体包括至少一个电子部件和设置在载体的第一侧面上面的至少一个接触区，其中该至少一个电子部件被电连接至该至少一个接触区；
穿过无机材料层形成至少一个接触孔，其中该至少一个接触孔接触该至少一个接触区；以及
中间层形成在该无机材料层和半导体晶片的第一侧面之间，其中该中间层包括来自下述材料组中的一种材料，该材料组包括金、铝和玻璃粉。
26.根据权利要求25的方法，其中
将无机材料层晶片结合至载体的第一侧面包括将无机材料层直接结合到载体的第一侧面。
27.根据权利要求25的方法，其中
将无机材料层晶片结合至载体的第一侧面包括通过阳极结合、共熔结合、热压缩结合、反应结合、共晶结合、玻璃粉结合和粘合剂结合中的至少一种将无机材料层晶片结合至载体的第一侧面。
28.根据权利要求25的方法，其中
将无机材料层晶片结合至载体的第一侧面包括将包括半导体晶片的无机材料层晶片结合至载体的第一侧面。
29.根据权利要求25的方法，其中
将无机材料层晶片结合至载体的第一侧面包括将包括硅、砷化镓、磷化铟、氮化镓、玻璃、氧化铝或碳化硅中的至少一种的无机材料层晶片结合至载体的第一侧面。
30.如权利要求25的方法，其中
穿过无机材料层形成至少一个接触孔包括选择性地去除无机材料层的至少一部分，以形成从该至少一个接触区至无机材料层的顶面延伸的沟道，以及
在沟道中沉积导电材料，其中导电材料接触该至少一个接触区。
31.如权利要求25的方法，进一步包括
穿过无机材料层形成至少一个另外的接触孔，该至少一个另外的接触孔在无机材料层的顶面与载体的第二侧面之间延伸，该至少一个另外的接触孔覆盖在该载体的第二侧面上面形成的另外的接触区的至少一部分。
32.如权利要求25的方法，进一步包括
在无机材料层的顶面处该至少一个接触孔的上方设置焊接材料。
33.如权利要求25的方法，其中
载体具有第一热膨胀系数，且其中无机材料层具有第二热膨胀系数，其中第二热膨胀系数相较于第一热膨胀系数具有小于100%的差值。
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