CN1738023A - 三维集成电路及其设计方法 - Google Patents
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Abstract
一种三维(3D)集成电路(IC)、3DIC芯片、以及制造3DIC芯片的方法。此芯片包括多个电路层，例如各包括电路元件的绝缘体上硅(SOI)CMOSIC层。这些层可以被同时制作，且一个层固定到另一个层以形成层叠的3D芯片。
Description
技术领域
本发明涉及到集成电路(IC)的设计，更确切地说是涉及到三维(3D)IC的设计与制造。
背景技术
半导体技术和芯片制造的进展已经导致芯片特征尺寸的不断减小，以便提高芯片上电路的开关频率(电路性能)和晶体管的数目(电路密度)。通常，所有其它因素恒定时，给定单元消耗的有源功率随开关频率而线性增大。于是，尽管芯片电源电压降低了，芯片功率消耗还是增大。由于芯片功率的这一增大，无论在芯片层面还是在系统层面，冷却和封装成本都已经增大。对于电池寿命至关重要的低端系统(例如手持系统、便携式系统、以及移动系统)，降低净功率消耗是重要的，但这一功率降低必须不使芯片/电路性能退化到可接受水平以下。
为了尽量减小半导体电路的功率消耗，以所谓CMOS的熟知的互补绝缘栅场效应晶体管(FET)技术来制作大多数集成电路(IC)。典型的CMOS电路包括通常用相同的信号来栅控的成对的互补器件，亦即n型FET(NFET)与相应的p型FET(PFET)配对。由于成对的器件具有彼此基本上相反的工作特性，故当一个器件(例如NFET)被开通并导电(简单地模型化为一个开通的开关)时，另一个器件(PFET)被断开而不导电(理想地模型化为一个断开的开关)，反之亦然。例如，CMOS倒相器是一个串联连接在电源电压(Vdd)和地(GND)之间的PFET和NFET对。二者由同一个输入栅控，且二者驱动同一个输出，典型是电容性负载，且理想的情况是，典型的CMOS电路仅仅消耗过渡即转换功率。
改善密度(单位面积的FET更多)的典型方法是缩小最小设计尺寸。但此方法经常受到最小尺寸的限制。增加了密度的芯片可以被层叠成双重或三重器件密度，可以称为三维(3D)芯片。但简单地层叠芯片要求保持正常的芯片电路边界。故芯片边界之间通过的信号仍然遭遇归咎于芯片间通信的障碍。形成对照的是，在可以称为基本的自上而下的方法中，各层FET，例如PFET和NFET的各个交替层，被各自形成并键合在另一个的顶部，以便形成3D IC芯片。例如，论文Kunio et al.，“Three Dimensional ICs，Having Four Stacked ActiveDevice Layers”，IEEE，1989描述了一种自上而下的CMOS芯片，此芯片利用多晶硅互连将相邻层上的FET连接成为电路。在此例子中，CMOS静态随机存取存储器(SRAM)、可编程逻辑阵列(PLA)、以及I/O缓冲器的CMOS门阵列，被包括在同一个3D IC芯片上。对于具有短距离例如交叉耦合各个SRAM单元倒相器的多晶硅可忽略其固有电阻，但当驱动任何显著的负载时，增大了延迟(亦即来自驱动大电容性负载的驱动器的多晶硅连接电阻组合起来增加了路径的RC延迟)，且长的多晶硅引线起分布RC的作用，这也增大了分布延迟。
但在现有技术的自上而下的3D芯片中，各个电路/宏被装配或置于一个或多个电路层上。各个电路层可以包括局部布线，以便将各个器件连接到一起成为电路(例如AND、OR、NAND、NOR门)，并在某些情况下将各个电路连接到一起成为更高阶功能(例如n×n位倍增器)或宏。各个电路层被连接到一起，以便形成单个多层3D芯片。但若各个电路层对准得不恰当或不准确，则芯片功能可能失效。而且，一个层上的布线可以例如通过串扰或因为信号无法在各层之间通信而在电学上干扰另一层上的布线。因此，为了在各个电路层之间避免布线问题和适当地分配布线资源，严格的布线限制通常是必须的。而且，各个结构和系统必须是必要的、最佳的布线资源的。对这种自上而下层状芯片的最佳逻辑和存储器结构的分隔和定位的理解不很充分。而且，如上所述，在层叠宏的逻辑分隔过程中，可能出现时控的问题。因此，不可能在定位和分隔之后例如从时控、热问题、和/或噪声的观点来弥合设计。最后，在多层中设计随机逻辑可能非常耗费，要求特殊的工具和复杂得多的模拟。
在有时称为自下而上的方法中，在一层电路被设计成具有宏/层输入和输出(I/O)组之后，开始设计下一层。因此，例如电路被常规地制造在最下层上，例如被制造在本体硅衬底上或绝缘体上硅(SOI)晶片上的硅表面层上。然后，在基底晶片上形成第二电路层(例如外延硅(epi Si)生长、非晶硅再结晶、或晶片键合)并在此第二层上完成器件加工。然后，重复此过程以产生额外的超结构电路层。通常，一旦完成了一个电路层相继设计考虑的定位和连接(例如作为时控分析结果的选择性激励逻辑门)，若例如为激励缓冲器保留的空间不够，则必须重新定位和重新连接此层。而且，形成在自下而上3D芯片的上层中的FET质量很差且电路性能退化。此外，由于形成上层而使先前形成的下层经受热循环，相继形成后续各个层也使底部基底电路层的特性退化。例如，热循环能够引起掺杂剂从完全确定的源/漏扩散到相邻的沟道区中，这使即使在基底电路层之外的层中不包括器件的那些电路的性能也退化。结果，对于自下而上设计，虽然可以形成密度非常高的芯片，但材料的选择受到限制，FET的质量与高性能不能共存。
于是，对于密度非常高的高性能集成电路以及设计这种电路，使电路功能可以被分布到一些电路层中而不对电路性能造成不利影响的方法，存在着需求。
发明内容
本发明的目的是改进集成电路(IC)芯片的密度；
本发明的另一目的是简化IC设计；
本发明的另一目的是提高IC芯片的功能性；
本发明的另一目的是提高IC芯片的功能性以及改进IC芯片的密度而不使IC芯片设计复杂化和不损害芯片的性能。
本发明涉及到三维(3D)集成电路(IC)、3D IC芯片、以及制造3D IC芯片的方法。此芯片包括多个电路层，例如各包括电路元件的绝缘体上硅(SOI)CMOS IC层。这些层可以被同时形成，且一层固定到另一层，以形成层叠的3D芯片。本发明还涉及到3D芯片设计方法，此方法最佳地利用了一个以上的有源器件层。
附图说明
参照附图，从本发明优选实施方案的下列详细描述，可以更好地理解上述和其它的目的、情况、以及优点，其中：
图1示出了根据本发明制作的优选实施方案三维(3D)集成电路(IC)芯片的一个例子；
图2A-B示出了制作优选实施方案3D芯片的各个步骤的一个例子；
图3A-C示出了固定图2A-B中的晶片的步骤的一个例子。
具体实施方式
现在参照附图，确切地说，图1示出了根据本发明制作的优选实施方案三维(3D)集成电路(IC)芯片100的一个例子。在此例子中，第一电路层102支持着第二电路层104，其中，第一层102例如是同步逻辑或管道线层，而第二层104包括第一层102的时钟分布(时钟树)。应该指出的是，此处所指的电路层是一种器件结构或电路，其中包含了完整的各个有源和/或无源器件，并可以被连接到一起。于是，电路层中的各个电路可以包括诸如去耦电容器之类的电容器、电感器、电阻器等。在此例子中，电路层102和104被夹在其间的在此例子中是为布线层的可选的第三电路层106连接到一起。第一层102上的电路元件108，例如场效应晶体管(FET)、逻辑门、宏、或任何适当的电路元件或电学器件，通过布线层106连接到第二电路层104中的可能是例如驱动器网格112中的驱动器的电路元件阵列的电路元件110。虽然本例子中所示的各个相继的层106和104小于(表面面积更小)其下方的层102和106，但这仅仅是作为例子。典型地说，所有的层102、106、104是共同扩张覆盖相同的面积并形成厚度均匀的芯片100。而且，虽然本例子的3D IC芯片100包括3个电路层102、104、106，但这仅仅是被设计选择作为例子。任何适当的电路层数目都可以被选择。
图2A示出了制作芯片，例如制作根据本发明优选实施方案的芯片100的过程中各个步骤的例子120。在步骤122中提供了逻辑或电路设计，并在步骤124中进行了定位和连接。确切地说，在定位和布线步骤124中，此设计可以被分隔，以便选择性地将某些功能定位在一个电路层上，或将各个器件和逻辑门等分布在各个电路层中。在步骤126中，同时制造各个层晶片，例如以各个电路层面于单个晶片上或成批晶片上。在步骤128中，各个电路层被组合以形成单个多层3D电路，例如，各层的晶片彼此层叠形成单个3D晶片。此层叠的3D晶片通常在步骤130中被切割，以便分离各个优选实施方案3D芯片。
图2B示出了图1例子的双(2)电路层变种的例子140，具有同样标注的相似步骤。再次在步骤122中提供了例如标准单元逻辑库的逻辑设计的初始设计，并在步骤1242中被优选定位和布线在单个电路层上。对于后续电路层上的定位可以选择性地省略缓冲器。对于逻辑定位，考虑了逻辑与省略的缓冲器之间的边界。然后，在此例子中，逻辑(减去缓冲器)被定位和布线在单个电路层上。在步骤1244中，例如用典型的现有技术性能分析工具，此单个电路层设计被通过性能分析。此性能分析典型地确认必须被激励或紧密定位在一起的第一电路层上的各个逻辑元件，例如定位驱动(源)缓冲器或第二(沉)的输入以满足性能要求的第一单元。若有空间，则缓冲器可以与此逻辑一起定位在第一层上。否则，在步骤1246中，缓冲器和激励驱动器等就被定位在第二电路层上。由于缓冲器和激励驱动器被定位在第二层上，故即使当特定的第一层电路附近没有可用的空间，缓冲器和激励驱动器也被容易地定位到接近其缓冲或激励的电路。而且，可以通过第二层可选地对第一层设计进行后期改变(例如所谓工程改变即EC)。因此，原先在第一层定位之后可能无法正常得到空间的情况下，基于优选实施方案设计在第二层中相应的重叠位置处可得到足够的空间，例如定位成单独的逻辑元件或选自单元阵列或驱动器阵列中的一个或多个单元。
一旦在步骤1244中完成了性能分析，并已经在步骤1246中在第二电路层上定位和布线；就在步骤1262和1264中，在晶片上优选同时形成各个电路层，例如各层面于单独的SOI晶片或成批SOI晶片中的诸晶片上。典型地说，这些SOI晶片被常规地形成到最终的或后端金属化。例如，借助于用聚合物粘合剂将各个第二层晶片固定到玻璃处置晶片而开始步骤128。然后，可以例如借助于研磨和腐蚀晶片衬底并停止于埋置的氧化物(BOX)层上，对第二层晶片进行减薄。由于减薄而透明的各第二层晶片被对准并例如用胶固定到第一电路层晶片。由于第二层晶片是透明的，故可以在原来的基底衬底上设计具有相同的公共取向(都“面朝上”)的特定的3D IC芯片的所有电路层，以方便各个电路层的直接层叠。于是，以相似于光刻技术中的掩模-晶片对准的方式，可以用重叠套准使各个后续层晶片对准于其直接的前面的层。这一对准保证了预先制造的3D电路的电学整体性，从而促成了良好的高性能3D IC。一旦被固定，就在层叠的各个层之间形成连接，例如腐蚀层间通孔和金属化，以便在通孔中形成通道。最后，在步骤130中，层叠的晶片叠层被常规地切割，以便分离各个优选实施方案3D芯片，并使热应力和机械应力最小。
对于原先的设计不适合在单个芯片覆盖面积内的更大的设计，在步骤1242中，逻辑被分割在第一和第二电路层之间，使大部分电路元件位于第一层中。然后在步骤1244中，传统的物理拼合对最终设计的二个电路层进行优化。在这一性能分析步骤1244中，额外的电路元件被确认，且若有空间，就定位在第一层晶片的适当位置处；否则，若无法在第一电路层上得到足够的空间，或若额外的元件无法被定位而不招致不可接受的性能损失，则电路元件被定位在第二电路层上，优选是使二个层上的各个位置对准，例如在源的紧邻上方具有附加的沉。如上所述，附加的元件可以选自第二层上现有常规阵列的诸元件，或可以在第二层上产生的新的电路元件。
图3A-C示出了图2A-B中固定晶片的步骤128的例子。图3A示出了完成了的第二层晶片150，例如一个在上表面154上具有用来固定玻璃处置晶片156的键合层152的200mm的SOI晶片。此玻璃处置晶片156为电路层提供了结构稳定性，使得能够清除原先的衬底。正如利用典型的SOI晶片，例如硅的衬底层158支持着例如BOX层的绝缘层160。硅器件层162已经被分割以形成器件小岛，源/漏区164形成在小岛中，而栅166形成在源/漏区之间。键合层152可以是任何适当的材料，用来将玻璃处置层156固定到晶片，使其在衬底层158被清除时仍然被固定。借助于研磨和腐蚀晶片衬底层158并停止于BOX层160上，来清除衬底层158。确切地说，第二层的厚度小于50微米，更确切地说是小于15微米。然后在图3B中，在固定玻璃处置层156和清除衬底层之后，例如用聚合物粘合剂170将第二层晶片150固定到各自的第一层晶片168，将各个层晶片键合到一起。因此，第一电路层已经从其原来的衬底层158被转移到了第一电路层168，以第一电路层168作为第二电路层的衬底。在图3C中，处置晶片156和键合层152被清除，且借助于在导电元件之间形成互连174或在层叠的电路层之间形成布线而垂直完成了3D电路晶片172。确切地说，层晶片150和168上的连接以及其间的互连174二者可以是铜、钨、或金属化栓塞和通道。
有利的是，在优选实施方案的自上而下方法中，所有的电路层能够用常规的IC制造工艺同时制造。各个电路层上的电路元件组合形成更高水平的电路元件，或者将激励缓冲器加到其它功率不足的逻辑电路，或者将I/O驱动器连接到宏以完成宏I/O边界。在装配3D IC之前，可以在图2A的步骤126中对各个分立的电路层进行测试。与将功能测试推迟到整个3D IC完成时相比，这促成了可接受的芯片成品率并降低了制造成本。借助于减小芯片覆盖面积而改善了晶体管的封装密度，这是由于电路的第三维才成为可能的。对于重视硅占用面积的军用电子产品以及无线或便携式电子产品，这是特别有吸引力的。
此外，由于与典型的单层芯片相比，代替迂回在电路之间的长的布线，电路层之间垂直行进的短布线降低了平均互连长度，故提高了优选实施方案3D IC的电路性能。利用减小了的电学距离，减小了在特征尺寸按比例减小时可能严重限制性能的与布线长度有关的性能潜伏状态。这导致了例如在一个层上的存储器与另一层上的微处理器之间的改进了的通信，对于某些应用提供了显著的性能改进。特别是在具有深管道的同步芯片中，例如借助于将时钟级层叠在比较小的水平区域内，时钟走线长度被大幅度减小，与分散在单个电路层上的相同逻辑功能可能得到的相比，这提高了在单个时钟周期内可存取的芯片面积在大得多的逻辑控制时段内的分额。此外，执行推测性任务的深管道要求从给定数据源的高的扇出。由于典型FET电路的扇出被限制在每周期固定的电容性增益量，故这一限制由于非固有负载(例如布线)被减小而被增大。
而且，由于布线长度和管芯尺寸更短，诸如来自平行的信号线或时钟线的长迂回(比较大的电容性信号负载)的串扰之类的噪声以及功率被大幅度降低。同样，例如由于全局布线较少，比等效的水平电路功能的短得多，故各个输入门处的噪声抗扰性得到了改善，且所需的时钟转发器更少。另一优点是，其它典型地不可兼容的各种技术的混合提供了单个芯片功能的丰富选择。借助于在单个优选实施方案3D芯片中层叠各个电路层，例如在一个电路层上提供CMOS逻辑，而其它的一个或多个层包括光子/电子电路、存储器、模拟和/或射频(RF)电路，形成了混合电路。于是，异质材料、器件、以及信号能够与SOICMOS电路集成而不削弱芯片和/或模块连接的性能，且在电路和器件结构、系统设计、以及路径选择方面的灵活性大得多。
虽然就优选实施方案而言已经描述了本发明，但本技术领域的熟练人员可以理解的是，可以按所附权利要求的构思与范围内的修正来实施本发明。
Claims (32)
1.一种集成电路，它包含：
电路层的叠层，它至少包括连接到一起成为电路元件的晶体管的第一电路层和第二电路层；
所述第二电路层上的多个所述电路元件直接排列在第一层上多个所述电路元件上；以及
多个层间连接通道，各个层间连接通道具有终止在所述第一层和所述第二层上所述电路元件之一上的末端，所述第一层上的各个所述电路元件通过所述多个层间连接通道被连接到所述第二层上的相应的各个所述电路元件，所述电路元件到所述相应电路元件的连接在所述集成电路内形成三维较高层面的电路元件。
2.权利要求1的集成电路，其中，至少一个所述电路层的叠层是排列在一对相邻的所述电路层之间的布线层，所述各个所述多个层间连接通道的另一端被连接到所述布线层上的布线。
3.权利要求1的集成电路，其中，所述第一电路层上的至少一个电路元件与所述第二电路层上的相应电路元件共用一个层间连接通道。
4.权利要求1的集成电路，其中，所述第一电路层是绝缘体上硅CMOS电路层。
5.权利要求4的集成电路，其中，所述第二电路层包括有源电路元件阵列。
6.权利要求5的集成电路，其中，所述绝缘体上硅CMOS电路层上的所述电路元件包含组合逻辑电路，且所述有源电路元件阵列是CMOS驱动器网格，所述驱动器网格的选定驱动器是所述绝缘体上硅CMOS电路层上相应的组合逻辑门的激励缓冲器。
7.权利要求4的集成电路，其中，所述第二层包含所述绝缘体上硅CMOS电路层的时钟分布。
8.权利要求7的集成电路，其中，所述时钟分布包含多个CMOS时钟驱动器。
9.权利要求4的集成电路，其中，大多数集成电路芯片所述电路元件位于所述绝缘体上硅CMOS电路层上。
10.权利要求4的集成电路，其中，所述第二层是绝缘体上硅CMOS电路层。
11.一种集成电路芯片，它包含：
衬底层；
所述衬底层上的第一绝缘层；
所述第一绝缘层上的第一半导体层，晶体管由所述第一半导体层制作；
固定到所述第一半导体层的第二绝缘层；
所述第二绝缘层上的第二半导体层，晶体管由所述第二半导体层制作，在所述第一半导体层和所述第二半导体层中每一个处的所述晶体管被一起连接成为电路层内的电路元件；以及
多个层间连接通道，各个层间连接通道具有终止于所述第一半导体层和所述第二半导体层上的所述电路元件之一并从其延伸的末端，所述第一半导体层上的各个所述电路元件通过所述多个层间连接通道被连接到所述第二半导体层上的相应的各个所述电路元件，所述电路元件到所述相应电路元件的连接，在所述集成电路内形成三维较高层面的电路元件。
12.权利要求11的集成电路芯片，其中，所述第一半导体层是硅层，且所述衬底层、所述第一绝缘层、以及所述硅层是绝缘体上硅CMOS电路层中的层。
13.权利要求12的集成电路芯片，其中，所述绝缘体上硅CMOS电路层还包含所述硅层上的布线层，所述晶体管被所述布线层中的布线连接到一起，且所述集成电路还包含键合所述第二绝缘层和所述绝缘体上硅CMOS电路层的聚合物粘合层，所述聚合物粘合层将所述第二半导体层固定到所述绝缘体上硅CMOS电路层，所述多个层间连接通道在所述电路元件与所述相应电路元件之间直线延伸。
14.权利要求12的集成电路芯片，还包含排列在所述绝缘体上硅CMOS电路层与所述第二半导体层之间的布线层，各个所述多个层间连接的另一端被连接到所述布线层上的布线。
15.权利要求11的集成电路芯片，其中，所述第二半导体层包括电路元件阵列。
16.权利要求15的集成电路芯片，其中，所述绝缘体上硅CMOS电路层上的所述电路元件包含组合逻辑电路，且所述电路元件阵列是CMOS驱动器网格，所述CMOS驱动器网格的选定驱动器是所述绝缘体上硅CMOS电路层上相应的组合逻辑门的激励缓冲器。
17.权利要求14的集成电路芯片，其中，所述第二半导体层包括所述绝缘体上硅CMOS电路层的时钟分布。
18.权利要求17的集成电路芯片，其中，所述时钟分布包括多个CMOS时钟驱动器。
19.权利要求14的集成电路芯片，其中，大多数集成电路芯片元件位于所述绝缘体上硅CMOS电路层上。
20.权利要求14的集成电路芯片，其中，所述第二绝缘层和所述第二半导体层是第二绝缘体上硅CMOS电路层中的层。
21.一种制造集成电路芯片的方法，所述方法包含下列步骤：
a)提供集成电路设计；
b)定位和布线所述集成电路设计，电路元件被定位在至少二个电路层上，所述至少二个电路层的第一电路层的选定的所述电路元件被连接到所述至少二个电路层的第二电路层上相应的电路元件；
c)制造所述至少二个电路层；
d)将所述第二电路层固定到所述第一电路层；以及
e)形成从所述第一电路层中和所述第二电路层中的电路元件延伸的连接通道，三维集成电路由所述第一电路层中的所述电路元件连接到所述第二电路层中的所述电路元件而形成。
22.权利要求21的方法，其中，定位和布线的步骤(b)包含下列步骤：
i)将大多数电路元件定位在所述第一电路层中；以及
ii)将其余的电路元件定位在所述第二电路层上。
23.权利要求22的方法，其中，定位大多数元件的步骤(i)包含下列步骤：
A)先将所述集成电路设计的逻辑电路定位和布线在单个层上；
B)对定位和布线的所述逻辑电路进行性能分析；以及
C)将所述缓冲器定位和布线在所述第二电路层上。
24.权利要求23的方法，其中，定位和布线的步骤(C)包括对初始定位在所述单层上的选定的所述电路元件进行定位和布线。
25.权利要求22的方法，其中，所述第二电路层是电路元件阵列，且定位所述其余电路元件的步骤(ii)包含从所述阵列中选择一些电路元件。
26.权利要求21的方法，其中，制造所述至少二个层的步骤(c)包含在第一绝缘体上硅晶片上制造所述至少二个层中的第一层以及在第二绝缘体上硅晶片上制造所述至少二个层中的第二层。
27.权利要求26的方法，其中，固定的步骤(d)包含下列步骤：
i)将玻璃处置晶片固定到所述第二绝缘体上硅晶片；
ii)从所述第二绝缘体上硅晶片清除衬底层；以及
iii)将所述第二绝缘体上硅晶片固定到所述第一绝缘体上硅晶片，所述第一绝缘体上硅晶片为所述第二绝缘体上硅晶片提供了衬底。
28.权利要求27的方法，还包含下述步骤：
e)将层叠的第二绝缘体上硅晶片和所述第一绝缘体上硅晶片切割成各个单独的三维层叠芯片。
29.一种定位和布线电路设计的方法，所述方法包含下列步骤：
a)接收集成电路设计；
b)先将大多数设计电路元件定位和布线在所述第一电路层中；
c)对定位和布线的所述第一电路层进行性能分析；
d)选择性地清除定位在所述第一电路层上的电路元件；
e)在所述第二电路层上定位其余的电路元件并清除所述电路元件；以及
f)布线所述第二层，所述第二电路层上的元件被连接到所述第一电路层上相应的元件。
30.权利要求29的方法，其中，在先定位和布线的步骤(b)之后保留的所述电路元件是所述第一电路层上组合逻辑电路的缓冲器。
31.权利要求29的方法，其中，定位所述其余的电路元件的步骤(e)包含从电路元件阵列选择电路元件。
32.权利要求31的方法，其中，所述电路元件阵列是驱动器阵列。
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| US10/919,121 US7312487B2 (en) | 2004-08-16 | 2004-08-16 | Three dimensional integrated circuit |
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| CN101866371B (zh) * | 2009-04-16 | 2012-05-02 | 奇景光电股份有限公司 | 立体集成电路的验证方法 |
| CN103681609A (zh) * | 2012-09-25 | 2014-03-26 | 英飞凌科技股份有限公司 | 集成电路、芯片封装以及用于制造集成电路的方法 |
| CN103681609B (zh) * | 2012-09-25 | 2017-01-04 | 英飞凌科技股份有限公司 | 集成电路、芯片封装以及用于制造集成电路的方法 |
| CN103853861A (zh) * | 2012-11-30 | 2014-06-11 | 国际商业机器公司 | 评估3d ic的电源供应的方法和装置 |
| CN103853861B (zh) * | 2012-11-30 | 2016-12-21 | 国际商业机器公司 | 评估3d ic的电源供应的方法和装置 |
| CN104617101A (zh) * | 2013-11-05 | 2015-05-13 | 台湾积体电路制造股份有限公司 | 具有多个半导体器件层的半导体结构的系统和方法 |
| CN106463522A (zh) * | 2014-01-14 | 2017-02-22 | 麻省理工学院 | 形成集成电路的方法及相关的集成电路 |
| US10324256B2 (en) | 2014-01-14 | 2019-06-18 | Massachusetts Institute Of Technology | Method of forming an integrated circuit and related integrated circuit |
| CN106463522B (zh) * | 2014-01-14 | 2019-12-03 | 麻省理工学院 | 形成集成电路的方法及相关的集成电路 |
| CN113809070A (zh) * | 2021-08-11 | 2021-12-17 | 中国科学院微电子研究所 | 一种基带rf一体化集成结构及集成方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20070287224A1 (en) | 2007-12-13 |
| US20080042140A1 (en) | 2008-02-21 |
| US7723207B2 (en) | 2010-05-25 |
| US7312487B2 (en) | 2007-12-25 |
| TW200629538A (en) | 2006-08-16 |
| CN100424853C (zh) | 2008-10-08 |
| US20060033110A1 (en) | 2006-02-16 |
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